Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2100

1

T2

4

T6

10

T9

11

auto[1]

582

1

T9

15

T28

3

T22

11

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2014

1

T2

4

T9

24

T28

9

auto[1]

668

1

T6

10

T9

2

T28

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2055

1

T2

4

T6

10

T9

22

auto[1]

627

1

T9

4

T41

16

T22

4

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2021

1

T2

3

T6

10

T9

15

auto[1]

661

1

T2

1

T9

11

T41

8

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2405

1

T2

3

T6

10

T9

26

auto[1]

277

1

T2

1

T41

18

T42

5

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2444

1

T2

4

T6

10

T9

26

auto[1]

238

1

T41

14

T43

1

T100

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2479

1

T2

3

T6

10

T9

26

auto[1]

203

1

T2

1

T43

3

T35

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2491

1

T2

4

T6

10

T9

26

auto[1]

191

1

T28

3

T41

6

T42

5

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2373

1

T2

4

T6

10

T9

26

auto[1]

309

1

T41

24

T42

5

T43

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2034

1

T2

4

T9

22

T28

12

auto[1]

648

1

T6

10

T9

4

T22

9

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	971	1			T6	10		T9	26		T22	30
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	63	1			T76	3		T257	1		T277	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	78	1			T76	3		T126	6		T356	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	50	1			T41	10		T76	3		T96	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	59	1			T96	3		T256	5		T257	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	16	1			T222	3		T357	6		T358	6
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	30	1			T100	3		T359	3		T360	16
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	10	1			T42	5		T43	2		T361	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	26	1			T258	2		T220	4		T362	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	69	1			T2	1		T82	6		T222	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	18	1			T35	3		T126	2		T100	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T247	1		T359	1		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	5	1			T275	3		T363	2		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	5	1			T43	3		T78	2		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	8	1			T355	7		T364	1		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	79	1			T43	1		T83	12		T247	8
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	2	1			T78	1		T365	1		-	-
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	33	1			T82	3		T359	8		T360	6
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	18	1			T41	8		T360	2		T366	4
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	17	1			T100	3		T367	5		T260	8
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	6	1			T41	6		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	28	1			T368	2		T369	5		T260	11
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	3	1			T370	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	6	1			T369	3		T371	3		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	6	1			T367	4		T251	2		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

142

1

T9

13

T22

11

T162

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

141

1

T34

12

T257

1

T83

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

57

1

T103

5

T179

7

T264

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

155

1

T2

1

T9

9

T41

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

59

1

T279

8

T179

2

T372

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

49

1

T112

3

T97

8

T373

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

26

1

T143

3

T292

2

T281

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

111

1

T41

6

T128

10

T76

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T100

3

T240

6

T374

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

73

1

T22

1

T128

4

T143

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T9

2

T263

1

T347

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

66

1

T96

1

T347

4

T292

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

27

1

T347

2

T152

2

T82

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T112

3

T281

5

T159

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T43

1

T351

2

T375

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

136

1

T22

10

T42

5

T256

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

45

1

T96

3

T126

2

T143

9

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

93

1

T6

10

T22

5

T43

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T152

2

T197

2

T107

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T34

4

T35

3

T76

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T126

3

T100

2

T278

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

27

1

T99

1

T376

4

T348

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T49

1

T145

1

T377

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

71

1

T41

10

T46

9

T43

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T162

2

T378

4

T108

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

25

1

T22

3

T222

3

T350

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T258

2

T351

2

T350

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T128

3

T143

3

T278

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T34

2

T232

1

T267

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

12

1

T9

2

T277

1

T356

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T46

2

T278

1

T170

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded