Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T17

9

T29

4

T25

13

auto[1]

1089

1

T17

11

T29

16

T25

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

536

1

T17

5

T29

5

T25

4

from_0to1

530

1

T17

4

T29

5

T25

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T17

11

T29

10

T25

10

auto[1]

1125

1

T17

9

T29

10

T25

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1104

1

T17

8

T29

12

T25

8

auto[1]

1116

1

T17

12

T29

8

T25

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T17

1

T71

1

T73

2

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T29

1

T25

3

T72

2

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T17

1

T72

1

T73

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T17

1

T71

1

T72

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T17

1

T73

1

T22

1

auto[0]

from_0to1

auto[0]

auto[1]

81

1

T71

3

T72

1

T22

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T17

2

T25

2

T71

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T72

2

T55

1

T49

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T17

1

T71

1

T22

2

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T17

1

T29

1

T55

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T29

1

T72

1

T73

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T29

2

T25

1

T71

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T29

2

T25

1

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T17

1

T22

1

T49

1

auto[1]

from_0to1

auto[1]

auto[0]

77

1

T29

3

T73

1

T55

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T25

1

T71

1

T72

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1105

1

T17

7

T29

9

T25

9

auto[1]

1115

1

T17

13

T29

11

T25

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

512

1

T17

4

T29

4

T25

5

from_0to1

518

1

T17

4

T29

4

T25

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139

1

T17

11

T29

9

T25

12

auto[1]

1081

1

T17

9

T29

11

T25

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T17

12

T29

8

T25

6

auto[1]

1111

1

T17

8

T29

12

T25

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T72

1

T73

2

T55

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T385

3

T37

1

T69

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T17

1

T29

1

T49

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T17

1

T25

2

T73

1

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T17

2

T25

1

T73

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T29

1

T73

2

T22

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T17

1

T29

2

T73

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T25

1

T151

2

T37

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T17

2

T22

1

T55

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T29

2

T25

3

T71

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T71

1

T73

3

T55

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T29

1

T71

1

T73

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T17

1

T71

1

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T72

2

T22

1

T55

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T25

1

T71

1

T73

3

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T29

1

T25

2

T71

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1106

1

T17

8

T29

7

T25

8

auto[1]

1114

1

T17

12

T29

13

T25

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T17

6

T29

3

T25

4

from_0to1

521

1

T17

5

T29

4

T25

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1141

1

T17

9

T29

11

T25

11

auto[1]

1079

1

T17

11

T29

9

T25

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T17

14

T29

11

T25

10

auto[1]

1093

1

T17

6

T29

9

T25

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T29

1

T22

1

T115

2

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T72

2

T151

1

T37

3

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T17

2

T25

1

T115

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T25

1

T71

1

T115

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T17

1

T73

1

T115

1

auto[0]

from_0to1

auto[0]

auto[1]

82

1

T17

1

T29

1

T72

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T17

1

T29

1

T72

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T22

2

T151

1

T385

2

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T17

2

T22

1

T115

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T29

1

T25

1

T71

1

auto[1]

from_1to0

auto[1]

auto[0]

91

1

T17

1

T29

1

T71

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T17

1

T25

1

T73

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T17

1

T29

1

T25

2

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T29

1

T73

1

T49

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T17

1

T25

2

T71

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T71

2

T115

1

T49

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1101

1

T17

7

T29

9

T25

9

auto[1]

1119

1

T17

13

T29

11

T25

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

533

1

T17

5

T29

2

T25

3

from_0to1

532

1

T17

6

T29

2

T25

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1146

1

T17

10

T29

12

T25

13

auto[1]

1074

1

T17

10

T29

8

T25

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1104

1

T17

9

T29

8

T25

9

auto[1]

1116

1

T17

11

T29

12

T25

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T25

1

T72

1

T22

1

auto[0]

from_1to0

auto[0]

auto[1]

77

1

T22

1

T55

1

T115

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T17

1

T71

1

T73

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T25

1

T72

1

T73

1

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T17

1

T25

1

T71

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T17

2

T71

1

T55

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T71

1

T22

1

T115

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T29

1

T25

2

T71

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T17

1

T72

1

T22

2

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T17

2

T29

1

T25

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T49

1

T151

1

T385

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T17

1

T29

1

T71

3

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T17

1

T71

1

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T29

1

T25

1

T72

2

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T73

2

T55

1

T115

2

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T17

2

T71

1

T55

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1141

1

T17

11

T29

7

T25

12

auto[1]

1079

1

T17

9

T29

13

T25

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

526

1

T17

4

T29

4

T25

5

from_0to1

525

1

T17

3

T29

4

T25

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T17

8

T29

9

T25

11

auto[1]

1124

1

T17

12

T29

11

T25

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T17

16

T29

10

T25

11

auto[1]

1098

1

T17

4

T29

10

T25

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T17

2

T29

1

T71

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T55

1

T115

1

T49

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T29

1

T71

1

T72

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T25

1

T72

1

T55

2

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T25

1

T71

1

T72

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T17

1

T25

1

T71

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T17

1

T72

2

T55

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T71

1

T55

1

T115

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T17

1

T25

1

T71

2

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T25

1

T73

1

T22

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T17

1

T25

2

T72

2

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T29

2

T71

3

T22

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T17

1

T29

1

T71

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T29

1

T25

1

T55

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T29

1

T25

1

T71

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T29

1

T71

1

T73

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1106

1

T17

10

T29

10

T25

14

auto[1]

1114

1

T17

10

T29

10

T25

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

545

1

T17

4

T29

5

T25

6

from_0to1

537

1

T17

4

T29

4

T25

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T17

12

T29

13

T25

6

auto[1]

1080

1

T17

8

T29

7

T25

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1093

1

T17

8

T29

10

T25

11

auto[1]

1127

1

T17

12

T29

10

T25

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

81

1

T29

2

T73

3

T55

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T25

1

T71

1

T55

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T29

1

T25

2

T71

1

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T17

1

T25

1

T72

2

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T17

1

T29

2

T115

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T73

1

T22

1

T115

3

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T17

2

T29

1

T25

2

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T25

2

T71

1

T72

3

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T17

1

T25

1

T73

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T17

1

T29

1

T72

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T72

1

T73

1

T115

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T17

1

T29

1

T25

1

auto[1]

from_0to1

auto[0]

auto[0]

81

1

T17

1

T73

1

T22

2

auto[1]

from_0to1

auto[0]

auto[1]

78

1

T29

1

T72

1

T22

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T71

2

T72

1

T55

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T25

1

T73

2

T115

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1083

1

T17

9

T29

11

T25

7

auto[1]

1137

1

T17

11

T29

9

T25

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

531

1

T17

5

T29

5

T25

4

from_0to1

529

1

T17

5

T29

5

T25

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T17

9

T29

10

T25

13

auto[1]

1125

1

T17

11

T29

10

T25

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1126

1

T17

11

T29

7

T25

9

auto[1]

1094

1

T17

9

T29

13

T25

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T29

1

T71

2

T73

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T29

1

T25

1

T72

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T17

2

T115

1

T49

1

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T71

1

T73

1

T49

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T25

2

T71

1

T72

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T17

1

T71

1

T22

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T17

1

T25

1

T71

3

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T29

2

T72

2

T22

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T29

1

T72

1

T151

2

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T17

1

T29

1

T25

2

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T17

1

T25

1

T72

2

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T17

1

T29

1

T71

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T17

1

T29

2

T73

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T73

1

T22

1

T55

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T17

1

T29

1

T72

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T17

1

T72

1

T55

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T17

11

T29

6

T25

11

auto[1]

1159

1

T17

9

T29

14

T25

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

541

1

T17

4

T29

6

T25

5

from_0to1

549

1

T17

4

T29

5

T25

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T17

7

T29

8

T25

10

auto[1]

1145

1

T17

13

T29

12

T25

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T17

13

T29

12

T25

8

auto[1]

1149

1

T17

7

T29

8

T25

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T17

1

T71

1

T73

2

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T17

1

T25

2

T72

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T17

1

T25

1

T71

1

auto[0]

from_1to0

auto[1]

auto[1]

80

1

T29

1

T72

1

T22

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T17

1

T29

1

T25

2

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T71

1

T72

1

T73

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T17

1

T29

1

T25

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T17

1

T29

1

T71

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T29

1

T73

1

T22

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T25

1

T72

1

T73

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T17

1

T29

3

T72

1

auto[1]

from_1to0

auto[1]

auto[1]

78

1

T29

1

T25

1

T71

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T72

1

T73

1

T55

1

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T17

1

T29

1

T25

1

auto[1]

from_0to1

auto[1]

auto[0]

80

1

T29

1

T72

2

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T73

1

T55

1

T151

1