Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150989	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

114137

1

T4

16

T5

6

T1

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	137681	1			T4	2		T5	9		T1	25
values[0x0]	63144	1			T4	23		T5	2		T1	6
values[0x1]	64301	1			T4	37		T5	2		T1	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	122438	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

142688

1

T4

20

T5

6

T1

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	826	1			T2	4		T6	2		T29	1
valid_sources[0x01]	872	1			T2	1		T6	9		T16	3
valid_sources[0x02]	803	1			T2	6		T17	3		T93	1
valid_sources[0x03]	1848	1			T2	3		T6	1		T95	7
valid_sources[0x04]	966	1			T2	1		T28	6		T41	53
valid_sources[0x05]	794	1			T2	6		T16	1		T17	2
valid_sources[0x06]	965	1			T2	1		T6	1		T25	2
valid_sources[0x07]	928	1			T2	4		T13	1		T17	1
valid_sources[0x08]	1032	1			T2	6		T16	1		T72	1
valid_sources[0x09]	972	1			T2	3		T16	1		T12	2
valid_sources[0x0a]	779	1			T2	2		T17	3		T25	1
valid_sources[0x0b]	878	1			T2	5		T15	1		T28	5
valid_sources[0x0c]	989	1			T4	1		T2	1		T6	7
valid_sources[0x0d]	1052	1			T2	7		T17	2		T28	5
valid_sources[0x0e]	969	1			T2	3		T13	1		T17	1
valid_sources[0x0f]	958	1			T2	1		T16	1		T27	9
valid_sources[0x10]	1056	1			T2	2		T14	15		T6	3
valid_sources[0x11]	1015	1			T2	1		T6	1		T17	7
valid_sources[0x12]	1015	1			T2	5		T28	4		T59	1
valid_sources[0x13]	795	1			T2	5		T6	3		T29	3
valid_sources[0x14]	1024	1			T1	1		T2	4		T13	1
valid_sources[0x15]	943	1			T2	1		T17	1		T29	3
valid_sources[0x16]	897	1			T2	2		T93	1		T27	3
valid_sources[0x17]	772	1			T2	1		T6	1		T134	1
valid_sources[0x18]	2211	1			T4	1		T1	3		T2	5
valid_sources[0x19]	816	1			T2	6		T134	2		T28	4
valid_sources[0x1a]	1394	1			T2	1		T16	1		T21	2
valid_sources[0x1b]	868	1			T2	3		T15	2		T21	1
valid_sources[0x1c]	780	1			T2	2		T13	1		T12	1
valid_sources[0x1d]	835	1			T4	6		T2	4		T29	3
valid_sources[0x1e]	938	1			T13	1		T29	1		T27	12
valid_sources[0x1f]	754	1			T13	1		T72	1		T28	4
valid_sources[0x20]	967	1			T93	1		T12	2		T27	8
valid_sources[0x21]	723	1			T2	2		T17	2		T93	1
valid_sources[0x22]	867	1			T1	1		T2	1		T29	1
valid_sources[0x23]	772	1			T2	4		T6	6		T17	2
valid_sources[0x24]	1415	1			T2	2		T6	1		T17	2
valid_sources[0x25]	829	1			T2	2		T29	2		T58	1
valid_sources[0x26]	1741	1			T2	3		T13	1		T6	24
valid_sources[0x27]	1244	1			T2	2		T6	1		T29	7
valid_sources[0x28]	776	1			T2	2		T21	1		T28	1
valid_sources[0x29]	967	1			T2	4		T6	5		T15	1
valid_sources[0x2a]	933	1			T2	2		T29	3		T21	1
valid_sources[0x2b]	970	1			T2	3		T6	6		T29	2
valid_sources[0x2c]	849	1			T1	2		T2	7		T6	19
valid_sources[0x2d]	937	1			T2	8		T29	3		T25	1
valid_sources[0x2e]	777	1			T2	4		T17	4		T27	12
valid_sources[0x2f]	1978	1			T4	2		T2	8		T15	1
valid_sources[0x30]	1010	1			T4	4		T1	2		T2	4
valid_sources[0x31]	1091	1			T2	1		T13	2		T6	14
valid_sources[0x32]	890	1			T2	8		T93	2		T21	1
valid_sources[0x33]	672	1			T6	2		T17	1		T29	3
valid_sources[0x34]	793	1			T2	1		T3	17		T17	1
valid_sources[0x35]	2308	1			T2	4		T6	15		T15	1
valid_sources[0x36]	883	1			T2	6		T16	1		T72	2
valid_sources[0x37]	634	1			T6	2		T21	1		T28	2
valid_sources[0x38]	774	1			T2	1		T15	1		T29	4
valid_sources[0x39]	884	1			T2	3		T72	1		T28	2
valid_sources[0x3a]	847	1			T2	4		T6	4		T25	1
valid_sources[0x3b]	969	1			T4	1		T2	3		T72	1
valid_sources[0x3c]	729	1			T2	2		T6	9		T28	2
valid_sources[0x3d]	708	1			T2	3		T16	1		T17	1
valid_sources[0x3e]	2150	1			T1	1		T2	2		T29	1
valid_sources[0x3f]	894	1			T2	5		T72	2		T28	6
valid_sources[0x40]	848	1			T1	1		T2	2		T13	1
valid_sources[0x41]	1192	1			T21	2		T28	3		T41	32
valid_sources[0x42]	782	1			T2	6		T12	1		T25	3
valid_sources[0x43]	839	1			T4	7		T1	2		T2	5
valid_sources[0x44]	977	1			T2	5		T6	1		T15	2
valid_sources[0x45]	1086	1			T72	1		T28	4		T41	11
valid_sources[0x46]	1548	1			T2	4		T6	1		T16	1
valid_sources[0x47]	746	1			T4	1		T2	6		T16	1
valid_sources[0x48]	1016	1			T2	5		T6	6		T25	1
valid_sources[0x49]	1025	1			T72	2		T28	5		T41	14
valid_sources[0x4a]	935	1			T2	4		T6	6		T29	1
valid_sources[0x4b]	1187	1			T2	4		T133	3		T28	6
valid_sources[0x4c]	1780	1			T2	4		T6	1		T25	1
valid_sources[0x4d]	1160	1			T2	5		T29	1		T21	1
valid_sources[0x4e]	975	1			T2	3		T25	2		T21	1
valid_sources[0x4f]	946	1			T2	8		T6	7		T27	8
valid_sources[0x50]	729	1			T1	2		T2	3		T13	1
valid_sources[0x51]	1005	1			T1	1		T2	6		T6	1
valid_sources[0x52]	982	1			T2	5		T29	2		T28	3
valid_sources[0x53]	831	1			T2	2		T72	1		T28	3
valid_sources[0x54]	931	1			T72	1		T28	4		T41	6
valid_sources[0x55]	968	1			T1	4		T2	4		T17	2
valid_sources[0x56]	896	1			T21	1		T63	4		T28	4
valid_sources[0x57]	821	1			T2	1		T17	2		T29	2
valid_sources[0x58]	1421	1			T2	7		T6	24		T17	2
valid_sources[0x59]	944	1			T2	6		T13	1		T6	2
valid_sources[0x5a]	822	1			T2	2		T27	3		T134	3
valid_sources[0x5b]	998	1			T2	2		T6	9		T21	1
valid_sources[0x5c]	920	1			T2	8		T17	1		T27	11
valid_sources[0x5d]	915	1			T2	1		T13	1		T27	7
valid_sources[0x5e]	989	1			T2	3		T13	1		T17	1
valid_sources[0x5f]	1074	1			T2	3		T6	1		T16	1
valid_sources[0x60]	885	1			T2	4		T15	2		T25	1
valid_sources[0x61]	778	1			T2	1		T25	1		T58	1
valid_sources[0x62]	863	1			T2	2		T93	1		T27	3
valid_sources[0x63]	841	1			T2	1		T28	2		T41	1
valid_sources[0x64]	1965	1			T2	4		T15	3		T21	1
valid_sources[0x65]	1015	1			T2	4		T15	1		T17	3
valid_sources[0x66]	854	1			T2	3		T13	1		T6	4
valid_sources[0x67]	1226	1			T2	2		T29	2		T72	1
valid_sources[0x68]	736	1			T2	3		T13	1		T6	5
valid_sources[0x69]	1791	1			T2	1		T132	1		T72	1
valid_sources[0x6a]	731	1			T1	1		T2	4		T16	1
valid_sources[0x6b]	844	1			T2	4		T11	6		T27	14
valid_sources[0x6c]	786	1			T2	8		T17	1		T29	1
valid_sources[0x6d]	930	1			T6	6		T17	1		T27	21
valid_sources[0x6e]	923	1			T2	2		T6	5		T25	1
valid_sources[0x6f]	1382	1			T2	4		T25	2		T28	4
valid_sources[0x70]	1530	1			T1	2		T2	5		T6	5
valid_sources[0x71]	880	1			T2	8		T28	2		T41	17
valid_sources[0x72]	842	1			T2	4		T25	2		T72	1
valid_sources[0x73]	846	1			T2	5		T6	16		T16	1
valid_sources[0x74]	1919	1			T2	3		T25	1		T28	2
valid_sources[0x75]	873	1			T2	3		T13	2		T15	1
valid_sources[0x76]	1566	1			T2	5		T29	1		T25	1
valid_sources[0x77]	957	1			T1	2		T2	1		T15	1
valid_sources[0x78]	902	1			T2	2		T6	6		T21	1
valid_sources[0x79]	1810	1			T2	7		T29	2		T72	1
valid_sources[0x7a]	959	1			T2	4		T6	4		T16	1
valid_sources[0x7b]	892	1			T2	2		T16	1		T72	1
valid_sources[0x7c]	819	1			T1	1		T2	5		T25	1
valid_sources[0x7d]	928	1			T1	2		T2	1		T29	3
valid_sources[0x7e]	1355	1			T1	1		T2	1		T27	14
valid_sources[0x7f]	672	1			T27	4		T21	2		T28	1
valid_sources[0x80]	1260	1			T2	3		T15	1		T17	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62110

1

T4

2

T5

5

T1

9

values[0x0]

all_enables

biggest_size

30336

1

T4

8

T5

1

T1

3

values[0x1]

all_enables

biggest_size

21691

1

T4

6

T1

1

T2

51