Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T14,T22,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T14,T22,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T14,T22,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T22,T26
1	0	Covered	T4,T5,T1
1	1	Covered	T14,T22,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T22,T26
0	1	Covered	T81,T106,T109
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T22,T26
0	1	Covered	T14,T22,T26
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T22,T26
1	-	Covered	T14,T22,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T22,T26
DetectSt	168	Covered	T14,T22,T26
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T14,T22,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T22,T26
DebounceSt->IdleSt	163	Covered	T22,T26,T38
DetectSt->IdleSt	186	Covered	T81,T106,T109
DetectSt->StableSt	191	Covered	T14,T22,T26
IdleSt->DebounceSt	148	Covered	T14,T22,T26
StableSt->IdleSt	206	Covered	T14,T22,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T22,T26
0	1	Covered	T14,T22,T26
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T22,T26
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T22,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T57
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T22,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T26,T38
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T22,T26
DetectSt	-	-	-	-	1	-	-	Covered	T81,T106,T109
DetectSt	-	-	-	-	0	1	-	Covered	T14,T22,T26
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T22,T26
StableSt	-	-	-	-	-	-	0	Covered	T14,T22,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	258	0	0
CntIncr_A	8161287	129085	0	0
CntNoWrap_A	8161287	7522488	0	0
DetectStDropOut_A	8161287	4	0	0
DetectedOut_A	8161287	736	0	0
DetectedPulseOut_A	8161287	116	0	0
DisabledIdleSt_A	8161287	7387788	0	0
DisabledNoDetection_A	8161287	7390074	0	0
EnterDebounceSt_A	8161287	142	0	0
EnterDetectSt_A	8161287	120	0	0
EnterStableSt_A	8161287	116	0	0
PulseIsPulse_A	8161287	116	0	0
StayInStableSt	8161287	620	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8161287	6745	0	0
gen_low_level_sva.LowLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	115	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	258	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	0	0	0
T14	790	2	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	13	0	0
T24	0	2	0	0
T26	0	3	0	0
T29	4208	0	0	0
T38	0	13	0	0
T47	0	4	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	407	0	0	0
T92	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	129085	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	0	0	0
T14	790	75	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	338	0	0
T24	0	48	0	0
T26	0	127	0	0
T29	4208	0	0	0
T36	0	1776	0	0
T38	0	2247	0	0
T47	0	173	0	0
T48	0	89	0	0
T49	0	106	0	0
T50	0	56	0	0
T51	407	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522488	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	387	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	4	0	0
T81	754	1	0	0
T106	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T116	756	0	0	0
T117	484	0	0	0
T118	3626	0	0	0
T119	1038	0	0	0
T120	502	0	0	0
T121	44246	0	0	0
T122	527	0	0	0
T123	722	0	0	0
T124	674	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	736	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	0	0	0
T14	790	12	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	50	0	0
T24	0	6	0	0
T26	0	7	0	0
T29	4208	0	0	0
T38	0	28	0	0
T47	0	8	0	0
T48	0	1	0	0
T49	0	4	0	0
T50	0	5	0	0
T51	407	0	0	0
T92	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	116	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	0	0	0
T14	790	1	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	6	0	0
T24	0	1	0	0
T26	0	1	0	0
T29	4208	0	0	0
T38	0	6	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	407	0	0	0
T92	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7387788	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	267	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7390074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	267	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	142	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	0	0	0
T14	790	1	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	7	0	0
T24	0	1	0	0
T26	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T38	0	8	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	407	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	120	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	0	0	0
T14	790	1	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	6	0	0
T24	0	1	0	0
T26	0	1	0	0
T29	4208	0	0	0
T38	0	6	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	407	0	0	0
T92	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	116	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	0	0	0
T14	790	1	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	6	0	0
T24	0	1	0	0
T26	0	1	0	0
T29	4208	0	0	0
T38	0	6	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	407	0	0	0
T92	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	116	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	0	0	0
T14	790	1	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	6	0	0
T24	0	1	0	0
T26	0	1	0	0
T29	4208	0	0	0
T38	0	6	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	407	0	0	0
T92	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	620	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	0	0	0
T14	790	11	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	44	0	0
T24	0	5	0	0
T26	0	6	0	0
T29	4208	0	0	0
T38	0	22	0	0
T47	0	6	0	0
T49	0	2	0	0
T50	0	4	0	0
T51	407	0	0	0
T92	0	6	0	0
T127	0	6	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6745	0	0
T1	960	5	0	0
T2	9426	29	0	0
T3	554	0	0	0
T4	523	5	0	0
T5	855	4	0	0
T6	26577	11	0	0
T7	903	0	0	0
T13	436	1	0	0
T14	790	3	0	0
T15	524	5	0	0
T16	0	4	0	0
T17	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	115	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	0	0	0
T14	790	1	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	6	0	0
T24	0	1	0	0
T26	0	1	0	0
T29	4208	0	0	0
T38	0	6	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	407	0	0	0
T92	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T10,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T58,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T21
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T10,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T58,T59
0	1	Covered	T89,T90,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T58,T59
0	1	Unreachable
1	0	Covered	T21,T58,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T21
DetectSt	168	Covered	T21,T58,T59
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T21,T58,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T58,T59
DebounceSt->IdleSt	163	Covered	T1,T10,T135
DetectSt->IdleSt	186	Covered	T89,T90,T91
DetectSt->StableSt	191	Covered	T21,T58,T59
IdleSt->DebounceSt	148	Covered	T1,T10,T21
StableSt->IdleSt	206	Covered	T21,T58,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T21
0	1	Covered	T1,T10,T21
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T58,T59
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T58,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T10,T135
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T21
DetectSt	-	-	-	-	1	-	-	Covered	T89,T90,T91
DetectSt	-	-	-	-	0	1	-	Covered	T21,T58,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T58,T59
StableSt	-	-	-	-	-	-	0	Covered	T21,T58,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	170	0	0
CntIncr_A	8161287	87973	0	0
CntNoWrap_A	8161287	7522576	0	0
DetectStDropOut_A	8161287	6	0	0
DetectedOut_A	8161287	486217	0	0
DetectedPulseOut_A	8161287	57	0	0
DisabledIdleSt_A	8161287	6247971	0	0
DisabledNoDetection_A	8161287	6250298	0	0
EnterDebounceSt_A	8161287	107	0	0
EnterDetectSt_A	8161287	63	0	0
EnterStableSt_A	8161287	57	0	0
PulseIsPulse_A	8161287	57	0	0
StayInStableSt	8161287	486160	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8161287	6745	0	0
gen_low_level_sva.LowLevelEvent_A	8161287	7525074	0	0
gen_sticky_sva.StableStDropOut_A	8161287	156374	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	170	0	0
T1	960	1	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T22	0	2	0	0
T36	0	2	0	0
T38	0	2	0	0
T58	0	2	0	0
T59	0	2	0	0
T60	0	6	0	0
T77	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	87973	0	0
T1	960	33	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	89	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	44	0	0
T22	0	40	0	0
T36	0	60	0	0
T38	0	64	0	0
T58	0	100	0	0
T59	0	47	0	0
T60	0	135	0	0
T77	0	97	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522576	0	0
T1	960	558	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6	0	0
T89	2532	4	0	0
T90	0	1	0	0
T91	0	1	0	0
T98	5058	0	0	0
T136	422	0	0	0
T137	499	0	0	0
T138	424	0	0	0
T139	425	0	0	0
T140	423	0	0	0
T141	510	0	0	0
T142	492	0	0	0
T143	30921	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	486217	0	0
T21	327524	179	0	0
T22	0	78	0	0
T33	483	0	0	0
T36	0	539	0	0
T38	0	251	0	0
T49	0	15	0	0
T58	2551	462	0	0
T59	0	183	0	0
T60	0	290	0	0
T62	782	0	0	0
T63	2318	0	0	0
T71	1304	0	0	0
T72	504	0	0	0
T77	0	533	0	0
T129	0	60	0	0
T132	404	0	0	0
T133	432	0	0	0
T134	450	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	57	0	0
T21	327524	1	0	0
T22	0	1	0	0
T33	483	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T49	0	1	0	0
T58	2551	1	0	0
T59	0	1	0	0
T60	0	3	0	0
T62	782	0	0	0
T63	2318	0	0	0
T71	1304	0	0	0
T72	504	0	0	0
T77	0	1	0	0
T129	0	1	0	0
T132	404	0	0	0
T133	432	0	0	0
T134	450	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6247971	0	0
T1	960	432	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6250298	0	0
T1	960	433	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	107	0	0
T1	960	1	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	3	0	0
T77	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	63	0	0
T21	327524	1	0	0
T22	0	1	0	0
T33	483	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T49	0	1	0	0
T58	2551	1	0	0
T59	0	1	0	0
T60	0	3	0	0
T62	782	0	0	0
T63	2318	0	0	0
T71	1304	0	0	0
T72	504	0	0	0
T77	0	1	0	0
T129	0	1	0	0
T132	404	0	0	0
T133	432	0	0	0
T134	450	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	57	0	0
T21	327524	1	0	0
T22	0	1	0	0
T33	483	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T49	0	1	0	0
T58	2551	1	0	0
T59	0	1	0	0
T60	0	3	0	0
T62	782	0	0	0
T63	2318	0	0	0
T71	1304	0	0	0
T72	504	0	0	0
T77	0	1	0	0
T129	0	1	0	0
T132	404	0	0	0
T133	432	0	0	0
T134	450	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	57	0	0
T21	327524	1	0	0
T22	0	1	0	0
T33	483	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T49	0	1	0	0
T58	2551	1	0	0
T59	0	1	0	0
T60	0	3	0	0
T62	782	0	0	0
T63	2318	0	0	0
T71	1304	0	0	0
T72	504	0	0	0
T77	0	1	0	0
T129	0	1	0	0
T132	404	0	0	0
T133	432	0	0	0
T134	450	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	486160	0	0
T21	327524	178	0	0
T22	0	77	0	0
T33	483	0	0	0
T36	0	538	0	0
T38	0	250	0	0
T49	0	14	0	0
T58	2551	461	0	0
T59	0	182	0	0
T60	0	287	0	0
T62	782	0	0	0
T63	2318	0	0	0
T71	1304	0	0	0
T72	504	0	0	0
T77	0	532	0	0
T129	0	59	0	0
T132	404	0	0	0
T133	432	0	0	0
T134	450	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6745	0	0
T1	960	5	0	0
T2	9426	29	0	0
T3	554	0	0	0
T4	523	5	0	0
T5	855	4	0	0
T6	26577	11	0	0
T7	903	0	0	0
T13	436	1	0	0
T14	790	3	0	0
T15	524	5	0	0
T16	0	4	0	0
T17	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	156374	0	0
T21	327524	141	0	0
T22	0	143	0	0
T33	483	0	0	0
T36	0	93	0	0
T38	0	131	0	0
T49	0	92	0	0
T58	2551	147	0	0
T59	0	110	0	0
T60	0	218	0	0
T62	782	0	0	0
T63	2318	0	0	0
T71	1304	0	0	0
T72	504	0	0	0
T77	0	97	0	0
T129	0	289	0	0
T132	404	0	0	0
T133	432	0	0	0
T134	450	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T10,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T21
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T10,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T58
0	1	Covered	T77,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T58
0	1	Unreachable
1	0	Covered	T1,T10,T58

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T21
DetectSt	168	Covered	T1,T10,T58
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T10,T58

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T58
DebounceSt->IdleSt	163	Covered	T21,T60,T22
DetectSt->IdleSt	186	Covered	T77,T87,T88
DetectSt->StableSt	191	Covered	T1,T10,T58
IdleSt->DebounceSt	148	Covered	T1,T10,T21
StableSt->IdleSt	206	Covered	T1,T10,T58

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T21
0	1	Covered	T1,T10,T21
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T58
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T60,T22
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T21
DetectSt	-	-	-	-	1	-	-	Covered	T77,T87,T88
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T58
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T58
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T58
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	189	0	0
CntIncr_A	8161287	57362	0	0
CntNoWrap_A	8161287	7522557	0	0
DetectStDropOut_A	8161287	17	0	0
DetectedOut_A	8161287	8351	0	0
DetectedPulseOut_A	8161287	42	0	0
DisabledIdleSt_A	8161287	6247971	0	0
DisabledNoDetection_A	8161287	6250298	0	0
EnterDebounceSt_A	8161287	130	0	0
EnterDetectSt_A	8161287	59	0	0
EnterStableSt_A	8161287	42	0	0
PulseIsPulse_A	8161287	42	0	0
StayInStableSt	8161287	8309	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_sticky_sva.StableStDropOut_A	8161287	765143	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	189	0	0
T1	960	2	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	2	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	5	0	0
T22	0	2	0	0
T36	0	2	0	0
T38	0	2	0	0
T58	0	2	0	0
T59	0	2	0	0
T60	0	5	0	0
T77	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	57362	0	0
T1	960	59	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	26	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	55	0	0
T22	0	84	0	0
T36	0	63	0	0
T38	0	51	0	0
T58	0	22	0	0
T59	0	49	0	0
T60	0	500	0	0
T77	0	370	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522557	0	0
T1	960	557	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	17	0	0
T36	13569	0	0	0
T43	16359	0	0	0
T47	748	0	0	0
T48	726	0	0	0
T49	7206	0	0	0
T65	494	0	0	0
T77	2339	5	0	0
T87	0	3	0	0
T88	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	1	0	0
T148	0	3	0	0
T149	595	0	0	0
T150	408	0	0	0
T151	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	8351	0	0
T1	960	6	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	9	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T36	0	498	0	0
T38	0	299	0	0
T58	0	180	0	0
T59	0	167	0	0
T87	0	1	0	0
T89	0	575	0	0
T102	0	410	0	0
T131	0	396	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	42	0	0
T1	960	1	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T87	0	1	0	0
T89	0	2	0	0
T102	0	1	0	0
T131	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6247971	0	0
T1	960	432	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6250298	0	0
T1	960	433	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	130	0	0
T1	960	1	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	5	0	0
T22	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	5	0	0
T77	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	59	0	0
T1	960	1	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T77	0	5	0	0
T87	0	4	0	0
T88	0	1	0	0
T89	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	42	0	0
T1	960	1	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T87	0	1	0	0
T89	0	2	0	0
T102	0	1	0	0
T131	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	42	0	0
T1	960	1	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T87	0	1	0	0
T89	0	2	0	0
T102	0	1	0	0
T131	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	8309	0	0
T1	960	5	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	8	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T36	0	497	0	0
T38	0	298	0	0
T58	0	179	0	0
T59	0	166	0	0
T89	0	573	0	0
T102	0	409	0	0
T131	0	395	0	0
T152	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	765143	0	0
T1	960	42	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	80	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T36	0	139	0	0
T38	0	101	0	0
T58	0	507	0	0
T59	0	133	0	0
T87	0	32	0	0
T89	0	599	0	0
T102	0	98442	0	0
T131	0	384	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T10,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T21,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T21
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T10,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T21,T58
0	1	Covered	T38,T84,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T21,T58
0	1	Unreachable
1	0	Covered	T1,T21,T58

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T21
DetectSt	168	Covered	T1,T21,T58
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T21,T58

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T21,T58
DebounceSt->IdleSt	163	Covered	T10,T59,T22
DetectSt->IdleSt	186	Covered	T38,T84,T85
DetectSt->StableSt	191	Covered	T1,T21,T58
IdleSt->DebounceSt	148	Covered	T1,T10,T21
StableSt->IdleSt	206	Covered	T1,T21,T58

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T21
0	1	Covered	T1,T10,T21
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T21,T58
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T21,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T59,T22
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T21
DetectSt	-	-	-	-	1	-	-	Covered	T38,T84,T85
DetectSt	-	-	-	-	0	1	-	Covered	T1,T21,T58
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T21,T58
StableSt	-	-	-	-	-	-	0	Covered	T1,T21,T58
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	176	0	0
CntIncr_A	8161287	153370	0	0
CntNoWrap_A	8161287	7522570	0	0
DetectStDropOut_A	8161287	12	0	0
DetectedOut_A	8161287	499316	0	0
DetectedPulseOut_A	8161287	51	0	0
DisabledIdleSt_A	8161287	6247971	0	0
DisabledNoDetection_A	8161287	6250298	0	0
EnterDebounceSt_A	8161287	113	0	0
EnterDetectSt_A	8161287	63	0	0
EnterStableSt_A	8161287	51	0	0
PulseIsPulse_A	8161287	51	0	0
StayInStableSt	8161287	499265	0	0
gen_high_event_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_sticky_sva.StableStDropOut_A	8161287	318409	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	176	0	0
T1	960	2	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T22	0	2	0	0
T36	0	3	0	0
T38	0	6	0	0
T58	0	2	0	0
T59	0	3	0	0
T60	0	6	0	0
T77	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	153370	0	0
T1	960	53	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	15	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	28	0	0
T22	0	198	0	0
T36	0	184	0	0
T38	0	296	0	0
T58	0	74	0	0
T59	0	228	0	0
T60	0	189	0	0
T77	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522570	0	0
T1	960	557	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	12	0	0
T36	13569	0	0	0
T38	14538	2	0	0
T43	16359	0	0	0
T47	748	0	0	0
T48	726	0	0	0
T65	494	0	0	0
T77	2339	0	0	0
T84	0	2	0	0
T85	0	1	0	0
T115	502	0	0	0
T149	595	0	0	0
T150	408	0	0	0
T153	0	2	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	499316	0	0
T1	960	11	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	214	0	0
T36	0	279	0	0
T49	0	79	0	0
T58	0	588	0	0
T60	0	302	0	0
T77	0	238	0	0
T87	0	550	0	0
T129	0	249	0	0
T130	0	155	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	51	0	0
T1	960	1	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T36	0	1	0	0
T49	0	1	0	0
T58	0	1	0	0
T60	0	3	0	0
T77	0	1	0	0
T87	0	2	0	0
T129	0	1	0	0
T130	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6247971	0	0
T1	960	432	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6250298	0	0
T1	960	433	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	113	0	0
T1	960	1	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T10	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T36	0	2	0	0
T38	0	4	0	0
T58	0	1	0	0
T59	0	3	0	0
T60	0	3	0	0
T77	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	63	0	0
T1	960	1	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T49	0	1	0	0
T58	0	1	0	0
T60	0	3	0	0
T77	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	51	0	0
T1	960	1	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T36	0	1	0	0
T49	0	1	0	0
T58	0	1	0	0
T60	0	3	0	0
T77	0	1	0	0
T87	0	2	0	0
T129	0	1	0	0
T130	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	51	0	0
T1	960	1	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T36	0	1	0	0
T49	0	1	0	0
T58	0	1	0	0
T60	0	3	0	0
T77	0	1	0	0
T87	0	2	0	0
T129	0	1	0	0
T130	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	499265	0	0
T1	960	10	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	213	0	0
T36	0	278	0	0
T49	0	78	0	0
T58	0	587	0	0
T60	0	299	0	0
T77	0	237	0	0
T87	0	548	0	0
T129	0	248	0	0
T130	0	154	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	318409	0	0
T1	960	56	0	0
T2	9426	0	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	141	0	0
T36	0	199	0	0
T49	0	31	0	0
T58	0	57	0	0
T60	0	168	0	0
T77	0	454	0	0
T87	0	111	0	0
T129	0	59	0	0
T130	0	154	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T8,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T8,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T21
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T21
0	1	Covered	T8,T21,T157
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T21
1	-	Covered	T8,T21,T157

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T21
DetectSt	168	Covered	T3,T8,T21
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T8,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T21
DebounceSt->IdleSt	163	Covered	T158,T159,T160
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T8,T21
IdleSt->DebounceSt	148	Covered	T3,T8,T21
StableSt->IdleSt	206	Covered	T8,T21,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T21
0	1	Covered	T3,T8,T21
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T21
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T158,T159,T160
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T21
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T21,T157
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	59	0	0
CntIncr_A	8161287	75103	0	0
CntNoWrap_A	8161287	7522687	0	0
DetectStDropOut_A	8161287	0	0	0
DetectedOut_A	8161287	5231	0	0
DetectedPulseOut_A	8161287	28	0	0
DisabledIdleSt_A	8161287	7127732	0	0
DisabledNoDetection_A	8161287	7130014	0	0
EnterDebounceSt_A	8161287	31	0	0
EnterDetectSt_A	8161287	28	0	0
EnterStableSt_A	8161287	28	0	0
PulseIsPulse_A	8161287	28	0	0
StayInStableSt	8161287	5189	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	59	0	0
T3	554	2	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	4	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	4	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T56	0	2	0	0
T157	0	4	0	0
T161	0	4	0	0
T162	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	75103	0	0
T3	554	10	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	34	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	160	0	0
T24	0	89	0	0
T29	4208	0	0	0
T36	0	13	0	0
T39	0	49110	0	0
T56	0	19	0	0
T157	0	118	0	0
T161	0	72	0	0
T162	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522687	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	151	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	5231	0	0
T3	554	120	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	170	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	85	0	0
T24	0	38	0	0
T29	4208	0	0	0
T36	0	41	0	0
T39	0	43	0	0
T56	0	22	0	0
T157	0	83	0	0
T161	0	136	0	0
T162	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	28	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	2	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T56	0	1	0	0
T157	0	2	0	0
T161	0	2	0	0
T162	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7127732	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	3	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	4	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7130014	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	3	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	4	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	31	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	2	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T56	0	1	0	0
T157	0	2	0	0
T161	0	2	0	0
T162	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	28	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	2	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T56	0	1	0	0
T157	0	2	0	0
T161	0	2	0	0
T162	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	28	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	2	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T56	0	1	0	0
T157	0	2	0	0
T161	0	2	0	0
T162	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	28	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	2	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T56	0	1	0	0
T157	0	2	0	0
T161	0	2	0	0
T162	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	5189	0	0
T3	554	118	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	167	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	82	0	0
T24	0	36	0	0
T29	4208	0	0	0
T36	0	39	0	0
T39	0	41	0	0
T56	0	21	0	0
T157	0	81	0	0
T161	0	133	0	0
T162	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	12	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	1	0	0
T25	503	0	0	0
T51	407	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T124	0	1	0	0
T157	0	2	0	0
T158	0	1	0	0
T161	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T7,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T12
1	0	Covered	T4,T13,T6
1	1	Covered	T3,T7,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T36
0	1	Covered	T80,T167,T168
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T36
0	1	Covered	T3,T79,T39
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T36
1	-	Covered	T3,T79,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T24
DetectSt	168	Covered	T3,T7,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T7,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T36
DebounceSt->IdleSt	163	Covered	T24,T157,T169
DetectSt->IdleSt	186	Covered	T80,T167,T168
DetectSt->StableSt	191	Covered	T3,T7,T36
IdleSt->DebounceSt	148	Covered	T3,T7,T24
StableSt->IdleSt	206	Covered	T3,T36,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T24
0	1	Covered	T3,T7,T24
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T36
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T157,T169
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T24
DetectSt	-	-	-	-	1	-	-	Covered	T80,T167,T168
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T79,T39
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	110	0	0
CntIncr_A	8161287	204398	0	0
CntNoWrap_A	8161287	7522636	0	0
DetectStDropOut_A	8161287	4	0	0
DetectedOut_A	8161287	242329	0	0
DetectedPulseOut_A	8161287	48	0	0
DisabledIdleSt_A	8161287	6953425	0	0
DisabledNoDetection_A	8161287	6955702	0	0
EnterDebounceSt_A	8161287	58	0	0
EnterDetectSt_A	8161287	52	0	0
EnterStableSt_A	8161287	48	0	0
PulseIsPulse_A	8161287	48	0	0
StayInStableSt	8161287	242258	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8161287	2495	0	0
gen_low_level_sva.LowLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	110	0	0
T3	554	2	0	0
T6	26577	0	0	0
T7	903	2	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T24	0	1	0	0
T29	4208	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T79	0	4	0	0
T157	0	5	0	0
T169	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	204398	0	0
T3	554	10	0	0
T6	26577	0	0	0
T7	903	89	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T24	0	89	0	0
T29	4208	0	0	0
T36	0	69	0	0
T37	0	53117	0	0
T39	0	49110	0	0
T40	0	41492	0	0
T79	0	54	0	0
T157	0	177	0	0
T169	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522636	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	151	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	500	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	4	0	0
T80	6125	1	0	0
T105	33870	0	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T170	27479	0	0	0
T171	408	0	0	0
T172	643	0	0	0
T173	13868	0	0	0
T174	430	0	0	0
T175	524	0	0	0
T176	422	0	0	0
T177	1458	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	242329	0	0
T3	554	4	0	0
T6	26577	0	0	0
T7	903	212	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T29	4208	0	0	0
T36	0	13	0	0
T37	0	59314	0	0
T39	0	74667	0	0
T40	0	65391	0	0
T79	0	111	0	0
T157	0	155	0	0
T162	0	289	0	0
T178	0	212	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	48	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T79	0	2	0	0
T157	0	2	0	0
T162	0	2	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6953425	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	3	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	4	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6955702	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	3	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	4	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	58	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T24	0	1	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T79	0	2	0	0
T157	0	3	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	52	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T79	0	2	0	0
T157	0	2	0	0
T162	0	2	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	48	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T79	0	2	0	0
T157	0	2	0	0
T162	0	2	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	48	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T79	0	2	0	0
T157	0	2	0	0
T162	0	2	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	242258	0	0
T3	554	3	0	0
T6	26577	0	0	0
T7	903	210	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T29	4208	0	0	0
T36	0	11	0	0
T37	0	59312	0	0
T39	0	74666	0	0
T40	0	65389	0	0
T79	0	108	0	0
T157	0	152	0	0
T162	0	286	0	0
T178	0	211	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	2495	0	0
T1	960	0	0	0
T2	9426	0	0	0
T3	554	1	0	0
T4	523	5	0	0
T5	855	0	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	0	2	0	0
T13	436	3	0	0
T14	790	0	0	0
T15	524	3	0	0
T16	0	7	0	0
T17	0	7	0	0
T29	0	8	0	0
T93	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	23	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T29	4208	0	0	0
T39	0	1	0	0
T79	0	1	0	0
T119	0	1	0	0
T157	0	1	0	0
T162	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0