Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T11,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T11,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T11,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T21
1	0	Covered	T4,T5,T1
1	1	Covered	T8,T11,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T21
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T21
0	1	Covered	T8,T79,T179
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T11,T21
1	-	Covered	T8,T79,T179

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T21
DetectSt	168	Covered	T8,T11,T21
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T11,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T21
DebounceSt->IdleSt	163	Covered	T178,T86
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T11,T21
IdleSt->DebounceSt	148	Covered	T8,T11,T21
StableSt->IdleSt	206	Covered	T8,T21,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T21
0	1	Covered	T8,T11,T21
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T21
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T178,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T21
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T79,T179
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	58	0	0
CntIncr_A	8161287	61503	0	0
CntNoWrap_A	8161287	7522688	0	0
DetectStDropOut_A	8161287	0	0	0
DetectedOut_A	8161287	124115	0	0
DetectedPulseOut_A	8161287	28	0	0
DisabledIdleSt_A	8161287	6974325	0	0
DisabledNoDetection_A	8161287	6976607	0	0
EnterDebounceSt_A	8161287	30	0	0
EnterDetectSt_A	8161287	28	0	0
EnterStableSt_A	8161287	28	0	0
PulseIsPulse_A	8161287	28	0	0
StayInStableSt	8161287	124070	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	58	0	0
T8	650	2	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	2	0	0
T12	1513	0	0	0
T21	0	4	0	0
T25	503	0	0	0
T36	0	2	0	0
T51	407	0	0	0
T56	0	2	0	0
T79	0	4	0	0
T80	0	4	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T161	0	2	0	0
T178	0	1	0	0
T179	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	61503	0	0
T8	650	17	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	28	0	0
T12	1513	0	0	0
T21	0	47612	0	0
T25	503	0	0	0
T36	0	53	0	0
T51	407	0	0	0
T56	0	19	0	0
T79	0	54	0	0
T80	0	190	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T161	0	91	0	0
T178	0	96	0	0
T179	0	85	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522688	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	124115	0	0
T8	650	43	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	38	0	0
T12	1513	0	0	0
T21	0	104256	0	0
T25	503	0	0	0
T36	0	40	0	0
T51	407	0	0	0
T56	0	22	0	0
T79	0	80	0	0
T80	0	80	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T161	0	42	0	0
T179	0	181	0	0
T182	0	259	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	28	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	1	0	0
T12	1513	0	0	0
T21	0	2	0	0
T25	503	0	0	0
T36	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T79	0	2	0	0
T80	0	2	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T161	0	1	0	0
T179	0	1	0	0
T182	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6974325	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6976607	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	30	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	1	0	0
T12	1513	0	0	0
T21	0	2	0	0
T25	503	0	0	0
T36	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T79	0	2	0	0
T80	0	2	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T161	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	28	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	1	0	0
T12	1513	0	0	0
T21	0	2	0	0
T25	503	0	0	0
T36	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T79	0	2	0	0
T80	0	2	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T161	0	1	0	0
T179	0	1	0	0
T182	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	28	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	1	0	0
T12	1513	0	0	0
T21	0	2	0	0
T25	503	0	0	0
T36	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T79	0	2	0	0
T80	0	2	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T161	0	1	0	0
T179	0	1	0	0
T182	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	28	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	1	0	0
T12	1513	0	0	0
T21	0	2	0	0
T25	503	0	0	0
T36	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T79	0	2	0	0
T80	0	2	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T161	0	1	0	0
T179	0	1	0	0
T182	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	124070	0	0
T8	650	42	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	36	0	0
T12	1513	0	0	0
T21	0	104252	0	0
T25	503	0	0	0
T36	0	38	0	0
T51	407	0	0	0
T56	0	21	0	0
T79	0	78	0	0
T80	0	77	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T161	0	40	0	0
T179	0	180	0	0
T182	0	256	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	9	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T25	503	0	0	0
T51	407	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T164	0	1	0	0
T165	0	1	0	0
T179	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T11
1	0	Covered	T4,T3,T13
1	1	Covered	T7,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T12
0	1	Covered	T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T12
0	1	Covered	T8,T12,T21
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T12
1	-	Covered	T8,T12,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T11
DetectSt	168	Covered	T7,T8,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T8,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T12
DebounceSt->IdleSt	163	Covered	T11,T161,T168
DetectSt->IdleSt	186	Covered	T79
DetectSt->StableSt	191	Covered	T7,T8,T12
IdleSt->DebounceSt	148	Covered	T7,T8,T11
StableSt->IdleSt	206	Covered	T8,T12,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T11
0	1	Covered	T7,T8,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T161,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T79
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T12,T21
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	89	0	0
CntIncr_A	8161287	147902	0	0
CntNoWrap_A	8161287	7522657	0	0
DetectStDropOut_A	8161287	1	0	0
DetectedOut_A	8161287	19454	0	0
DetectedPulseOut_A	8161287	42	0	0
DisabledIdleSt_A	8161287	6954782	0	0
DisabledNoDetection_A	8161287	6957068	0	0
EnterDebounceSt_A	8161287	46	0	0
EnterDetectSt_A	8161287	43	0	0
EnterStableSt_A	8161287	42	0	0
PulseIsPulse_A	8161287	42	0	0
StayInStableSt	8161287	19395	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8161287	2877	0	0
gen_low_level_sva.LowLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	89	0	0
T7	903	2	0	0
T8	650	4	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	4	0	0
T24	0	4	0	0
T29	4208	0	0	0
T36	0	2	0	0
T39	0	4	0	0
T51	407	0	0	0
T79	0	6	0	0
T93	418	0	0	0
T94	406	0	0	0
T157	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	147902	0	0
T7	903	89	0	0
T8	650	34	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	0	28	0	0
T12	0	91	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	47612	0	0
T24	0	178	0	0
T29	4208	0	0	0
T36	0	13	0	0
T39	0	98220	0	0
T51	407	0	0	0
T79	0	81	0	0
T93	418	0	0	0
T94	406	0	0	0
T157	0	118	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522657	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	500	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	1	0	0
T79	714	1	0	0
T135	535391	0	0	0
T184	402	0	0	0
T185	502	0	0	0
T186	450	0	0	0
T187	495	0	0	0
T188	526	0	0	0
T189	425	0	0	0
T190	715	0	0	0
T191	654	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	19454	0	0
T7	903	345	0	0
T8	650	145	0	0
T9	27399	0	0	0
T10	561	0	0	0
T12	0	74	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	15961	0	0
T24	0	75	0	0
T29	4208	0	0	0
T36	0	41	0	0
T39	0	44	0	0
T51	407	0	0	0
T79	0	86	0	0
T93	418	0	0	0
T94	406	0	0	0
T157	0	256	0	0
T161	0	188	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	42	0	0
T7	903	1	0	0
T8	650	2	0	0
T9	27399	0	0	0
T10	561	0	0	0
T12	0	1	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	2	0	0
T51	407	0	0	0
T79	0	2	0	0
T93	418	0	0	0
T94	406	0	0	0
T157	0	2	0	0
T161	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6954782	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	4	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6957068	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	4	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	46	0	0
T7	903	1	0	0
T8	650	2	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	2	0	0
T51	407	0	0	0
T79	0	3	0	0
T93	418	0	0	0
T94	406	0	0	0
T157	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	43	0	0
T7	903	1	0	0
T8	650	2	0	0
T9	27399	0	0	0
T10	561	0	0	0
T12	0	1	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	2	0	0
T51	407	0	0	0
T79	0	3	0	0
T93	418	0	0	0
T94	406	0	0	0
T157	0	2	0	0
T161	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	42	0	0
T7	903	1	0	0
T8	650	2	0	0
T9	27399	0	0	0
T10	561	0	0	0
T12	0	1	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	2	0	0
T51	407	0	0	0
T79	0	2	0	0
T93	418	0	0	0
T94	406	0	0	0
T157	0	2	0	0
T161	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	42	0	0
T7	903	1	0	0
T8	650	2	0	0
T9	27399	0	0	0
T10	561	0	0	0
T12	0	1	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	2	0	0
T51	407	0	0	0
T79	0	2	0	0
T93	418	0	0	0
T94	406	0	0	0
T157	0	2	0	0
T161	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	19395	0	0
T7	903	343	0	0
T8	650	142	0	0
T9	27399	0	0	0
T10	561	0	0	0
T12	0	73	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	15959	0	0
T24	0	72	0	0
T29	4208	0	0	0
T36	0	39	0	0
T39	0	41	0	0
T51	407	0	0	0
T79	0	83	0	0
T93	418	0	0	0
T94	406	0	0	0
T157	0	254	0	0
T161	0	186	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	2877	0	0
T1	960	0	0	0
T2	9426	0	0	0
T3	554	2	0	0
T4	523	5	0	0
T5	855	0	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	0	2	0	0
T13	436	3	0	0
T14	790	0	0	0
T15	524	5	0	0
T16	0	7	0	0
T17	0	6	0	0
T29	0	9	0	0
T93	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	23	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	1	0	0
T21	0	2	0	0
T24	0	1	0	0
T25	503	0	0	0
T39	0	1	0	0
T51	407	0	0	0
T79	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T157	0	2	0	0
T161	0	2	0	0
T179	0	1	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T8,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T21
1	0	Covered	T4,T5,T1
1	1	Covered	T7,T8,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T24
0	1	Covered	T8,T193,T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T24
0	1	Covered	T21,T24,T79
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T21,T24
1	-	Covered	T21,T24,T79

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T21
DetectSt	168	Covered	T7,T8,T21
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T21,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T21
DebounceSt->IdleSt	163	Covered	T7,T162,T194
DetectSt->IdleSt	186	Covered	T8,T193,T166
DetectSt->StableSt	191	Covered	T7,T21,T24
IdleSt->DebounceSt	148	Covered	T7,T8,T21
StableSt->IdleSt	206	Covered	T21,T24,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T21
0	1	Covered	T7,T8,T21
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T21
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T21
DetectSt	-	-	-	-	1	-	-	Covered	T8,T193,T166
DetectSt	-	-	-	-	0	1	-	Covered	T7,T21,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T24,T79
StableSt	-	-	-	-	-	-	0	Covered	T7,T21,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	96	0	0
CntIncr_A	8161287	193043	0	0
CntNoWrap_A	8161287	7522650	0	0
DetectStDropOut_A	8161287	4	0	0
DetectedOut_A	8161287	139404	0	0
DetectedPulseOut_A	8161287	43	0	0
DisabledIdleSt_A	8161287	6968001	0	0
DisabledNoDetection_A	8161287	6970290	0	0
EnterDebounceSt_A	8161287	50	0	0
EnterDetectSt_A	8161287	47	0	0
EnterStableSt_A	8161287	43	0	0
PulseIsPulse_A	8161287	43	0	0
StayInStableSt	8161287	139341	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	96	0	0
T7	903	3	0	0
T8	650	2	0	0
T9	27399	0	0	0
T10	561	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	6	0	0
T24	0	4	0	0
T29	4208	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T51	407	0	0	0
T79	0	4	0	0
T93	418	0	0	0
T94	406	0	0	0
T191	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	193043	0	0
T7	903	178	0	0
T8	650	17	0	0
T9	27399	0	0	0
T10	561	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	95144	0	0
T24	0	178	0	0
T29	4208	0	0	0
T36	0	53	0	0
T37	0	53117	0	0
T38	0	61	0	0
T40	0	41492	0	0
T51	407	0	0	0
T79	0	54	0	0
T93	418	0	0	0
T94	406	0	0	0
T191	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522650	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	499	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	4	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T25	503	0	0	0
T51	407	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T166	0	1	0	0
T193	0	1	0	0
T195	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	139404	0	0
T7	903	212	0	0
T8	650	0	0	0
T9	27399	0	0	0
T10	561	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	77733	0	0
T24	0	75	0	0
T29	4208	0	0	0
T36	0	40	0	0
T37	0	59314	0	0
T38	0	43	0	0
T40	0	39	0	0
T51	407	0	0	0
T79	0	164	0	0
T93	418	0	0	0
T94	406	0	0	0
T157	0	264	0	0
T191	0	173	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	43	0	0
T7	903	1	0	0
T8	650	0	0	0
T9	27399	0	0	0
T10	561	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	3	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T51	407	0	0	0
T79	0	2	0	0
T93	418	0	0	0
T94	406	0	0	0
T157	0	1	0	0
T191	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6968001	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	4	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6970290	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	4	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	50	0	0
T7	903	2	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	3	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T51	407	0	0	0
T79	0	2	0	0
T93	418	0	0	0
T94	406	0	0	0
T191	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	47	0	0
T7	903	1	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	3	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T51	407	0	0	0
T79	0	2	0	0
T93	418	0	0	0
T94	406	0	0	0
T191	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	43	0	0
T7	903	1	0	0
T8	650	0	0	0
T9	27399	0	0	0
T10	561	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	3	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T51	407	0	0	0
T79	0	2	0	0
T93	418	0	0	0
T94	406	0	0	0
T157	0	1	0	0
T191	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	43	0	0
T7	903	1	0	0
T8	650	0	0	0
T9	27399	0	0	0
T10	561	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	3	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T51	407	0	0	0
T79	0	2	0	0
T93	418	0	0	0
T94	406	0	0	0
T157	0	1	0	0
T191	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	139341	0	0
T7	903	210	0	0
T8	650	0	0	0
T9	27399	0	0	0
T10	561	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	77730	0	0
T24	0	72	0	0
T29	4208	0	0	0
T36	0	38	0	0
T37	0	59312	0	0
T38	0	41	0	0
T40	0	37	0	0
T51	407	0	0	0
T79	0	161	0	0
T93	418	0	0	0
T94	406	0	0	0
T157	0	263	0	0
T191	0	171	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	21	0	0
T21	327524	3	0	0
T24	0	1	0	0
T33	483	0	0	0
T58	2551	0	0	0
T62	782	0	0	0
T63	2318	0	0	0
T71	1304	0	0	0
T72	504	0	0	0
T79	0	1	0	0
T80	0	1	0	0
T132	404	0	0	0
T133	432	0	0	0
T134	450	0	0	0
T157	0	1	0	0
T161	0	1	0	0
T163	0	1	0	0
T178	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T21,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T21,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T21,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T21
1	0	Covered	T4,T5,T1
1	1	Covered	T8,T21,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T21,T24
0	1	Covered	T198
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T21,T24
0	1	Covered	T21,T24,T39
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T21,T24
1	-	Covered	T21,T24,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T21,T24
DetectSt	168	Covered	T8,T21,T24
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T21,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T21,T24
DebounceSt->IdleSt	163	Covered	T178,T199,T200
DetectSt->IdleSt	186	Covered	T198
DetectSt->StableSt	191	Covered	T8,T21,T24
IdleSt->DebounceSt	148	Covered	T8,T21,T24
StableSt->IdleSt	206	Covered	T21,T24,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T21,T24
0	1	Covered	T8,T21,T24
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T21,T24
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T21,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T21,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T178,T199,T200
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T21,T24
DetectSt	-	-	-	-	1	-	-	Covered	T198
DetectSt	-	-	-	-	0	1	-	Covered	T8,T21,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T24,T39
StableSt	-	-	-	-	-	-	0	Covered	T8,T21,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	76	0	0
CntIncr_A	8161287	158364	0	0
CntNoWrap_A	8161287	7522670	0	0
DetectStDropOut_A	8161287	1	0	0
DetectedOut_A	8161287	77066	0	0
DetectedPulseOut_A	8161287	35	0	0
DisabledIdleSt_A	8161287	6906448	0	0
DisabledNoDetection_A	8161287	6908725	0	0
EnterDebounceSt_A	8161287	40	0	0
EnterDetectSt_A	8161287	36	0	0
EnterStableSt_A	8161287	35	0	0
PulseIsPulse_A	8161287	35	0	0
StayInStableSt	8161287	77014	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8161287	6525	0	0
gen_low_level_sva.LowLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	76	0	0
T8	650	2	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	4	0	0
T24	0	2	0	0
T25	503	0	0	0
T39	0	2	0	0
T51	407	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T157	0	2	0	0
T161	0	2	0	0
T162	0	2	0	0
T169	0	2	0	0
T178	0	1	0	0
T179	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	158364	0	0
T8	650	17	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	95064	0	0
T24	0	89	0	0
T25	503	0	0	0
T39	0	49110	0	0
T51	407	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T157	0	59	0	0
T161	0	91	0	0
T162	0	93	0	0
T169	0	31	0	0
T178	0	96	0	0
T179	0	85	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522670	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	1	0	0
T198	741	1	0	0
T201	422	0	0	0
T202	7495	0	0	0
T203	522	0	0	0
T204	57303	0	0	0
T205	514	0	0	0
T206	779	0	0	0
T207	4865	0	0	0
T208	12635	0	0	0
T209	41196	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	77066	0	0
T8	650	128	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	56680	0	0
T24	0	82	0	0
T25	503	0	0	0
T39	0	39	0	0
T51	407	0	0	0
T56	0	21	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T157	0	42	0	0
T161	0	233	0	0
T162	0	44	0	0
T169	0	37	0	0
T179	0	182	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	35	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T25	503	0	0	0
T39	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T157	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T169	0	1	0	0
T179	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6906448	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	3	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6908725	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	3	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	40	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T25	503	0	0	0
T39	0	1	0	0
T51	407	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T157	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T169	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	36	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T25	503	0	0	0
T39	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T157	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T169	0	1	0	0
T179	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	35	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T25	503	0	0	0
T39	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T157	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T169	0	1	0	0
T179	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	35	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T25	503	0	0	0
T39	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T157	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T169	0	1	0	0
T179	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	77014	0	0
T8	650	126	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	56677	0	0
T24	0	81	0	0
T25	503	0	0	0
T39	0	38	0	0
T51	407	0	0	0
T56	0	20	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T157	0	40	0	0
T161	0	231	0	0
T162	0	42	0	0
T169	0	35	0	0
T179	0	181	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6525	0	0
T1	960	5	0	0
T2	9426	31	0	0
T3	554	0	0	0
T4	523	6	0	0
T5	855	4	0	0
T6	26577	10	0	0
T7	903	1	0	0
T13	436	4	0	0
T14	790	0	0	0
T15	524	4	0	0
T16	0	7	0	0
T17	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	16	0	0
T21	327524	1	0	0
T24	0	1	0	0
T33	483	0	0	0
T39	0	1	0	0
T58	2551	0	0	0
T62	782	0	0	0
T63	2318	0	0	0
T71	1304	0	0	0
T72	504	0	0	0
T80	0	1	0	0
T119	0	1	0	0
T132	404	0	0	0
T133	432	0	0	0
T134	450	0	0	0
T145	0	1	0	0
T165	0	1	0	0
T179	0	1	0	0
T183	0	1	0	0
T210	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T2,T3
1	1	Covered	T4,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T11
1	0	Covered	T4,T2,T13
1	1	Covered	T3,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T11
0	1	Covered	T3,T12,T21
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T11
1	-	Covered	T3,T12,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T11
DetectSt	168	Covered	T3,T7,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T7,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T11
DebounceSt->IdleSt	163	Covered	T168,T183,T211
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T7,T11
IdleSt->DebounceSt	148	Covered	T3,T7,T11
StableSt->IdleSt	206	Covered	T3,T12,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T11
0	1	Covered	T3,T7,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T11
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T2,T3
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T168,T183,T211
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T12,T21
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	115	0	0
CntIncr_A	8161287	131232	0	0
CntNoWrap_A	8161287	7522631	0	0
DetectStDropOut_A	8161287	0	0	0
DetectedOut_A	8161287	53231	0	0
DetectedPulseOut_A	8161287	56	0	0
DisabledIdleSt_A	8161287	7062674	0	0
DisabledNoDetection_A	8161287	7064949	0	0
EnterDebounceSt_A	8161287	59	0	0
EnterDetectSt_A	8161287	56	0	0
EnterStableSt_A	8161287	56	0	0
PulseIsPulse_A	8161287	56	0	0
StayInStableSt	8161287	53152	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	115	0	0
T3	554	2	0	0
T6	26577	0	0	0
T7	903	2	0	0
T8	650	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	6	0	0
T29	4208	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T79	0	4	0	0
T157	0	4	0	0
T191	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	131232	0	0
T3	554	10	0	0
T6	26577	0	0	0
T7	903	89	0	0
T8	650	0	0	0
T11	0	28	0	0
T12	0	91	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	95144	0	0
T29	4208	0	0	0
T36	0	53	0	0
T38	0	61	0	0
T79	0	54	0	0
T157	0	118	0	0
T191	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522631	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	151	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	500	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	53231	0	0
T3	554	64	0	0
T6	26577	0	0	0
T7	903	42	0	0
T8	650	0	0	0
T11	0	60	0	0
T12	0	76	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	14849	0	0
T29	4208	0	0	0
T36	0	93	0	0
T38	0	10	0	0
T79	0	177	0	0
T157	0	82	0	0
T191	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	56	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	3	0	0
T29	4208	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T79	0	2	0	0
T157	0	2	0	0
T191	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7062674	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	3	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	4	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7064949	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	3	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	4	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	59	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	3	0	0
T29	4208	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T79	0	2	0	0
T157	0	2	0	0
T191	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	56	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	3	0	0
T29	4208	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T79	0	2	0	0
T157	0	2	0	0
T191	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	56	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	3	0	0
T29	4208	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T79	0	2	0	0
T157	0	2	0	0
T191	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	56	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	3	0	0
T29	4208	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T79	0	2	0	0
T157	0	2	0	0
T191	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	53152	0	0
T3	554	63	0	0
T6	26577	0	0	0
T7	903	40	0	0
T8	650	0	0	0
T11	0	58	0	0
T12	0	75	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	14844	0	0
T29	4208	0	0	0
T36	0	92	0	0
T38	0	9	0	0
T79	0	174	0	0
T157	0	80	0	0
T191	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	31	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T12	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T29	4208	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T79	0	1	0	0
T157	0	2	0	0
T161	0	1	0	0
T179	0	1	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T2,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T38,T79

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T38,T79

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T21,T38
1	0	Covered	T4,T2,T3
1	1	Covered	T8,T38,T79

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T38,T39
0	1	Covered	T193
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T38,T39
0	1	Covered	T119,T164,T212
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T38,T39
1	-	Covered	T119,T164,T212

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T38,T79
DetectSt	168	Covered	T8,T38,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T38,T39
DebounceSt->IdleSt	163	Covered	T79,T157
DetectSt->IdleSt	186	Covered	T193
DetectSt->StableSt	191	Covered	T8,T38,T39
IdleSt->DebounceSt	148	Covered	T8,T38,T79
StableSt->IdleSt	206	Covered	T38,T161,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T38,T79
0	1	Covered	T8,T38,T79
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T38,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T38,T79
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T79,T157
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T38,T79
DetectSt	-	-	-	-	1	-	-	Covered	T193
DetectSt	-	-	-	-	0	1	-	Covered	T8,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T56,T119,T164
StableSt	-	-	-	-	-	-	0	Covered	T8,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	48	0	0
CntIncr_A	8161287	62599	0	0
CntNoWrap_A	8161287	7522698	0	0
DetectStDropOut_A	8161287	1	0	0
DetectedOut_A	8161287	1533	0	0
DetectedPulseOut_A	8161287	22	0	0
DisabledIdleSt_A	8161287	7110964	0	0
DisabledNoDetection_A	8161287	7113251	0	0
EnterDebounceSt_A	8161287	25	0	0
EnterDetectSt_A	8161287	23	0	0
EnterStableSt_A	8161287	22	0	0
PulseIsPulse_A	8161287	22	0	0
StayInStableSt	8161287	1497	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8161287	6193	0	0
gen_low_level_sva.LowLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	6	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	48	0	0
T8	650	2	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T25	503	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T51	407	0	0	0
T56	0	2	0	0
T79	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T119	0	4	0	0
T157	0	3	0	0
T161	0	2	0	0
T192	0	2	0	0
T196	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	62599	0	0
T8	650	17	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T25	503	0	0	0
T38	0	61	0	0
T39	0	49110	0	0
T51	407	0	0	0
T56	0	19	0	0
T79	0	27	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T119	0	150	0	0
T157	0	118	0	0
T161	0	91	0	0
T192	0	88	0	0
T196	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522698	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	1	0	0
T193	803	1	0	0
T213	402	0	0	0
T214	424	0	0	0
T215	28446	0	0	0
T216	39439	0	0	0
T217	423	0	0	0
T218	422	0	0	0
T219	894	0	0	0
T220	17648	0	0	0
T221	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	1533	0	0
T8	650	67	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T25	503	0	0	0
T38	0	43	0	0
T39	0	44	0	0
T51	407	0	0	0
T56	0	20	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T119	0	142	0	0
T124	0	42	0	0
T157	0	124	0	0
T161	0	42	0	0
T192	0	210	0	0
T196	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	22	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T25	503	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T119	0	2	0	0
T124	0	1	0	0
T157	0	1	0	0
T161	0	1	0	0
T192	0	1	0	0
T196	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7110964	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7113251	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	25	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T25	503	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T79	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T119	0	2	0	0
T157	0	2	0	0
T161	0	1	0	0
T192	0	1	0	0
T196	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	23	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T25	503	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T119	0	2	0	0
T124	0	1	0	0
T157	0	1	0	0
T161	0	1	0	0
T192	0	1	0	0
T196	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	22	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T25	503	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T119	0	2	0	0
T124	0	1	0	0
T157	0	1	0	0
T161	0	1	0	0
T192	0	1	0	0
T196	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	22	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T25	503	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T119	0	2	0	0
T124	0	1	0	0
T157	0	1	0	0
T161	0	1	0	0
T192	0	1	0	0
T196	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	1497	0	0
T8	650	65	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T25	503	0	0	0
T38	0	41	0	0
T39	0	42	0	0
T51	407	0	0	0
T56	0	19	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T119	0	139	0	0
T124	0	40	0	0
T157	0	122	0	0
T161	0	40	0	0
T192	0	208	0	0
T196	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6193	0	0
T1	960	0	0	0
T2	9426	30	0	0
T3	554	1	0	0
T4	523	5	0	0
T5	855	0	0	0
T6	26577	12	0	0
T7	903	0	0	0
T8	0	1	0	0
T13	436	5	0	0
T14	790	0	0	0
T15	524	5	0	0
T16	0	7	0	0
T17	0	3	0	0
T29	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6	0	0
T106	671	0	0	0
T119	1038	1	0	0
T120	502	0	0	0
T121	44246	0	0	0
T122	527	0	0	0
T123	722	0	0	0
T124	674	0	0	0
T160	0	1	0	0
T164	0	1	0	0
T198	0	1	0	0
T211	0	1	0	0
T212	0	1	0	0
T222	24674	0	0	0
T223	426	0	0	0
T224	450	0	0	0