Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.34	89.13	90.48		83.33	85.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.34	89.13	90.48		83.33	85.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T2,T3
1	1	Covered	T4,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T12,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T4,T2,T13
1	1	Covered	T3,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T21
0	1	Covered	T86,T225,T226
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T21
0	1	Covered	T3,T24,T161
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T12,T21
1	-	Covered	T3,T24,T161

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T12
DetectSt	168	Covered	T3,T12,T21
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T12,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T12,T21
DebounceSt->IdleSt	163	Covered	T11,T21,T24
DetectSt->IdleSt	186	Covered	T86,T225,T226
DetectSt->StableSt	191	Covered	T3,T12,T21
IdleSt->DebounceSt	148	Covered	T3,T11,T12
StableSt->IdleSt	206	Covered	T3,T24,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T12
0	1	Covered	T3,T11,T12
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T21
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T2,T3
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T12,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T21,T24
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T12
DetectSt	-	-	-	-	1	-	-	Covered	T86,T225,T226
DetectSt	-	-	-	-	0	1	-	Covered	T3,T12,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T24,T161
StableSt	-	-	-	-	-	-	0	Covered	T3,T12,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	108	0	0
CntIncr_A	8161287	115275	0	0
CntNoWrap_A	8161287	7522638	0	0
DetectStDropOut_A	8161287	5	0	0
DetectedOut_A	8161287	41460	0	0
DetectedPulseOut_A	8161287	46	0	0
DisabledIdleSt_A	8161287	7170256	0	0
DisabledNoDetection_A	8161287	7172535	0	0
EnterDebounceSt_A	8161287	58	0	0
EnterDetectSt_A	8161287	51	0	0
EnterStableSt_A	8161287	46	0	0
PulseIsPulse_A	8161287	46	0	0
StayInStableSt	8161287	41392	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	108	0	0
T3	554	4	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	3	0	0
T24	0	3	0	0
T29	4208	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T161	0	6	0	0
T162	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	115275	0	0
T3	554	20	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T11	0	28	0	0
T12	0	91	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	160	0	0
T24	0	178	0	0
T29	4208	0	0	0
T36	0	53	0	0
T39	0	49110	0	0
T40	0	41492	0	0
T161	0	163	0	0
T162	0	245	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522638	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	149	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	5	0	0
T86	1812	1	0	0
T163	713	0	0	0
T199	0	1	0	0
T225	0	1	0	0
T226	0	1	0	0
T227	0	1	0	0
T228	1825	0	0	0
T229	408	0	0	0
T230	21495	0	0	0
T231	9074	0	0	0
T232	38933	0	0	0
T233	34228	0	0	0
T234	531	0	0	0
T235	494	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	41460	0	0
T3	554	69	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T12	0	44	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	42	0	0
T24	0	38	0	0
T29	4208	0	0	0
T36	0	211	0	0
T39	0	44	0	0
T40	0	39	0	0
T161	0	150	0	0
T162	0	223	0	0
T236	0	57	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	46	0	0
T3	554	2	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T12	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T161	0	3	0	0
T162	0	2	0	0
T236	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7170256	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	3	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7172535	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	3	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	58	0	0
T3	554	2	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	51	0	0
T3	554	2	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T12	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T161	0	3	0	0
T162	0	2	0	0
T236	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	46	0	0
T3	554	2	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T12	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T161	0	3	0	0
T162	0	2	0	0
T236	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	46	0	0
T3	554	2	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T12	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T29	4208	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T161	0	3	0	0
T162	0	2	0	0
T236	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	41392	0	0
T3	554	66	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T12	0	42	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	40	0	0
T24	0	37	0	0
T29	4208	0	0	0
T36	0	209	0	0
T39	0	42	0	0
T40	0	37	0	0
T161	0	147	0	0
T162	0	220	0	0
T236	0	55	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	22	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T24	0	1	0	0
T29	4208	0	0	0
T119	0	2	0	0
T161	0	3	0	0
T162	0	1	0	0
T163	0	1	0	0
T179	0	1	0	0
T193	0	1	0	0
T199	0	1	0	0
T210	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T2,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T8,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T4,T2,T13
1	1	Covered	T3,T8,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T21
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T21
0	1	Covered	T3,T21,T24
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T21
1	-	Covered	T3,T21,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T21
DetectSt	168	Covered	T3,T8,T21
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T8,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T21
DebounceSt->IdleSt	163	Covered	T210
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T8,T21
IdleSt->DebounceSt	148	Covered	T3,T8,T21
StableSt->IdleSt	206	Covered	T3,T21,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T21
0	1	Covered	T3,T8,T21
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T21
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T210
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T21
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T21,T24
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	73	0	0
CntIncr_A	8161287	14093	0	0
CntNoWrap_A	8161287	7522673	0	0
DetectStDropOut_A	8161287	0	0	0
DetectedOut_A	8161287	18654	0	0
DetectedPulseOut_A	8161287	36	0	0
DisabledIdleSt_A	8161287	7182861	0	0
DisabledNoDetection_A	8161287	7185135	0	0
EnterDebounceSt_A	8161287	38	0	0
EnterDetectSt_A	8161287	36	0	0
EnterStableSt_A	8161287	36	0	0
PulseIsPulse_A	8161287	36	0	0
StayInStableSt	8161287	18598	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8161287	6099	0	0
gen_low_level_sva.LowLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	73	0	0
T3	554	2	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	2	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T24	0	4	0	0
T29	4208	0	0	0
T56	0	2	0	0
T119	0	4	0	0
T161	0	4	0	0
T162	0	2	0	0
T179	0	2	0	0
T237	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	14093	0	0
T3	554	10	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	17	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	80	0	0
T24	0	178	0	0
T29	4208	0	0	0
T56	0	19	0	0
T119	0	150	0	0
T161	0	72	0	0
T162	0	76	0	0
T179	0	85	0	0
T237	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522673	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	151	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	18654	0	0
T3	554	43	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	40	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	186	0	0
T24	0	78	0	0
T29	4208	0	0	0
T56	0	20	0	0
T119	0	141	0	0
T161	0	56	0	0
T162	0	42	0	0
T179	0	129	0	0
T237	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	36	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T24	0	2	0	0
T29	4208	0	0	0
T56	0	1	0	0
T119	0	2	0	0
T161	0	2	0	0
T162	0	1	0	0
T179	0	1	0	0
T237	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7182861	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	3	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	4	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7185135	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	3	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	4	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	38	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T24	0	2	0	0
T29	4208	0	0	0
T56	0	1	0	0
T119	0	2	0	0
T161	0	2	0	0
T162	0	1	0	0
T179	0	1	0	0
T237	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	36	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T24	0	2	0	0
T29	4208	0	0	0
T56	0	1	0	0
T119	0	2	0	0
T161	0	2	0	0
T162	0	1	0	0
T179	0	1	0	0
T237	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	36	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T24	0	2	0	0
T29	4208	0	0	0
T56	0	1	0	0
T119	0	2	0	0
T161	0	2	0	0
T162	0	1	0	0
T179	0	1	0	0
T237	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	36	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T24	0	2	0	0
T29	4208	0	0	0
T56	0	1	0	0
T119	0	2	0	0
T161	0	2	0	0
T162	0	1	0	0
T179	0	1	0	0
T237	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	18598	0	0
T3	554	42	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	38	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	185	0	0
T24	0	75	0	0
T29	4208	0	0	0
T56	0	19	0	0
T119	0	138	0	0
T161	0	53	0	0
T162	0	41	0	0
T179	0	127	0	0
T237	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6099	0	0
T1	960	0	0	0
T2	9426	31	0	0
T3	554	1	0	0
T4	523	5	0	0
T5	855	0	0	0
T6	26577	7	0	0
T7	903	0	0	0
T8	0	1	0	0
T13	436	3	0	0
T14	790	0	0	0
T15	524	4	0	0
T16	0	5	0	0
T17	0	7	0	0
T29	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	14	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T29	4208	0	0	0
T86	0	1	0	0
T119	0	1	0	0
T158	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T164	0	1	0	0
T167	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T2,T3
1	1	Covered	T4,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T11
1	0	Covered	T4,T2,T13
1	1	Covered	T3,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T11
0	1	Covered	T3,T8,T24
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T11
1	-	Covered	T3,T8,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T11
DetectSt	168	Covered	T3,T8,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T11
DebounceSt->IdleSt	163	Covered	T39,T169,T162
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T8,T11
IdleSt->DebounceSt	148	Covered	T3,T8,T11
StableSt->IdleSt	206	Covered	T3,T8,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T11
0	1	Covered	T3,T8,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T11
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T2,T3
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T169,T238
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T24
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	108	0	0
CntIncr_A	8161287	147602	0	0
CntNoWrap_A	8161287	7522638	0	0
DetectStDropOut_A	8161287	0	0	0
DetectedOut_A	8161287	9934	0	0
DetectedPulseOut_A	8161287	52	0	0
DisabledIdleSt_A	8161287	7122263	0	0
DisabledNoDetection_A	8161287	7124542	0	0
EnterDebounceSt_A	8161287	57	0	0
EnterDetectSt_A	8161287	52	0	0
EnterStableSt_A	8161287	52	0	0
PulseIsPulse_A	8161287	52	0	0
StayInStableSt	8161287	9856	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	108	0	0
T3	554	2	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	2	0	0
T11	0	2	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T24	0	4	0	0
T29	4208	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T75	0	2	0	0
T79	0	2	0	0
T237	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	147602	0	0
T3	554	10	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	17	0	0
T11	0	28	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T24	0	178	0	0
T29	4208	0	0	0
T36	0	69	0	0
T37	0	53117	0	0
T38	0	61	0	0
T75	0	77	0	0
T79	0	27	0	0
T237	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522638	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	151	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	9934	0	0
T3	554	5	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	60	0	0
T11	0	39	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T24	0	206	0	0
T29	4208	0	0	0
T36	0	13	0	0
T37	0	6148	0	0
T38	0	42	0	0
T75	0	39	0	0
T79	0	26	0	0
T237	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	52	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	1	0	0
T11	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T237	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7122263	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	3	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7124542	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	3	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	57	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	1	0	0
T11	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T237	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	52	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	1	0	0
T11	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T237	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	52	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	1	0	0
T11	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T237	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	52	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	1	0	0
T11	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T24	0	2	0	0
T29	4208	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T237	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	9856	0	0
T3	554	4	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	59	0	0
T11	0	37	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T24	0	203	0	0
T29	4208	0	0	0
T36	0	11	0	0
T37	0	6147	0	0
T38	0	40	0	0
T75	0	37	0	0
T79	0	25	0	0
T157	0	50	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	24	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	0	0	0
T8	650	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T24	0	1	0	0
T29	4208	0	0	0
T37	0	1	0	0
T79	0	1	0	0
T157	0	2	0	0
T161	0	1	0	0
T179	0	2	0	0
T237	0	1	0	0
T239	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T2,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T21,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T21,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T21,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T21
1	0	Covered	T4,T2,T3
1	1	Covered	T8,T21,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T21,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T21,T37
0	1	Covered	T180,T193,T165
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T21,T37
1	-	Covered	T180,T193,T165

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T21,T37
DetectSt	168	Covered	T8,T21,T37
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T21,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T21,T37
DebounceSt->IdleSt	163	Covered	T179
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T21,T37
IdleSt->DebounceSt	148	Covered	T8,T21,T37
StableSt->IdleSt	206	Covered	T21,T37,T162

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T21,T37
0	1	Covered	T8,T21,T37
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T21,T37
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T21,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T21,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T179
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T21,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T21,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T56,T180,T193
StableSt	-	-	-	-	-	-	0	Covered	T8,T21,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	51	0	0
CntIncr_A	8161287	101804	0	0
CntNoWrap_A	8161287	7522695	0	0
DetectStDropOut_A	8161287	0	0	0
DetectedOut_A	8161287	105740	0	0
DetectedPulseOut_A	8161287	25	0	0
DisabledIdleSt_A	8161287	7075441	0	0
DisabledNoDetection_A	8161287	7077733	0	0
EnterDebounceSt_A	8161287	26	0	0
EnterDetectSt_A	8161287	25	0	0
EnterStableSt_A	8161287	25	0	0
PulseIsPulse_A	8161287	25	0	0
StayInStableSt	8161287	105701	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8161287	6155	0	0
gen_low_level_sva.LowLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	51	0	0
T8	650	2	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	2	0	0
T25	503	0	0	0
T37	0	2	0	0
T51	407	0	0	0
T56	0	2	0	0
T79	0	2	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T162	0	2	0	0
T179	0	3	0	0
T180	0	2	0	0
T182	0	2	0	0
T196	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	101804	0	0
T8	650	17	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	47532	0	0
T25	503	0	0	0
T37	0	53117	0	0
T51	407	0	0	0
T56	0	19	0	0
T79	0	27	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T162	0	76	0	0
T179	0	170	0	0
T180	0	40	0	0
T182	0	85	0	0
T196	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522695	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	105740	0	0
T8	650	146	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	104212	0	0
T25	503	0	0	0
T37	0	47	0	0
T51	407	0	0	0
T56	0	21	0	0
T79	0	224	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T162	0	46	0	0
T179	0	43	0	0
T180	0	39	0	0
T182	0	86	0	0
T196	0	238	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	25	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	1	0	0
T25	503	0	0	0
T37	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T79	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T162	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T196	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7075441	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7077733	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	26	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	1	0	0
T25	503	0	0	0
T37	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T79	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T162	0	1	0	0
T179	0	2	0	0
T180	0	1	0	0
T182	0	1	0	0
T196	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	25	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	1	0	0
T25	503	0	0	0
T37	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T79	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T162	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T196	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	25	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	1	0	0
T25	503	0	0	0
T37	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T79	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T162	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T196	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	25	0	0
T8	650	1	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	1	0	0
T25	503	0	0	0
T37	0	1	0	0
T51	407	0	0	0
T56	0	1	0	0
T79	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T162	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T196	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	105701	0	0
T8	650	144	0	0
T9	27399	0	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T21	0	104210	0	0
T25	503	0	0	0
T37	0	45	0	0
T51	407	0	0	0
T56	0	20	0	0
T79	0	222	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T162	0	44	0	0
T179	0	41	0	0
T180	0	38	0	0
T182	0	84	0	0
T196	0	236	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6155	0	0
T1	960	0	0	0
T2	9426	34	0	0
T3	554	1	0	0
T4	523	4	0	0
T5	855	0	0	0
T6	26577	15	0	0
T7	903	1	0	0
T13	436	3	0	0
T14	790	0	0	0
T15	524	4	0	0
T16	0	7	0	0
T17	0	4	0	0
T29	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	9	0	0
T165	0	1	0	0
T180	11854	1	0	0
T183	0	1	0	0
T193	0	2	0	0
T195	0	1	0	0
T197	13550	0	0	0
T199	0	1	0	0
T200	0	1	0	0
T210	0	1	0	0
T240	22952	0	0	0
T241	2574	0	0	0
T242	490	0	0	0
T243	526	0	0	0
T244	480	0	0	0
T245	522	0	0	0
T246	490	0	0	0
T247	25927	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T11
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T21
0	1	Covered	T80,T210,T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T21
0	1	Covered	T21,T38,T40
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T21
1	-	Covered	T21,T38,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T11
DetectSt	168	Covered	T3,T7,T21
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T7,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T21
DebounceSt->IdleSt	163	Covered	T11,T158,T248
DetectSt->IdleSt	186	Covered	T80,T210,T166
DetectSt->StableSt	191	Covered	T3,T7,T21
IdleSt->DebounceSt	148	Covered	T3,T7,T11
StableSt->IdleSt	206	Covered	T21,T38,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T11
0	1	Covered	T3,T7,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T21
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T158,T248
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T80,T210,T166
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T38,T40
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	101	0	0
CntIncr_A	8161287	138722	0	0
CntNoWrap_A	8161287	7522645	0	0
DetectStDropOut_A	8161287	3	0	0
DetectedOut_A	8161287	170120	0	0
DetectedPulseOut_A	8161287	46	0	0
DisabledIdleSt_A	8161287	6997779	0	0
DisabledNoDetection_A	8161287	7000059	0	0
EnterDebounceSt_A	8161287	52	0	0
EnterDetectSt_A	8161287	49	0	0
EnterStableSt_A	8161287	46	0	0
PulseIsPulse_A	8161287	46	0	0
StayInStableSt	8161287	170053	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	101	0	0
T3	554	2	0	0
T6	26577	0	0	0
T7	903	2	0	0
T8	650	0	0	0
T11	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	2	0	0
T29	4208	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T161	0	4	0	0
T162	0	2	0	0
T236	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	138722	0	0
T3	554	10	0	0
T6	26577	0	0	0
T7	903	89	0	0
T8	650	0	0	0
T11	0	28	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	80	0	0
T29	4208	0	0	0
T38	0	61	0	0
T39	0	49110	0	0
T40	0	41492	0	0
T161	0	72	0	0
T162	0	76	0	0
T236	0	17	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522645	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	151	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	500	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	3	0	0
T80	6125	1	0	0
T105	33870	0	0	0
T166	0	1	0	0
T170	27479	0	0	0
T171	408	0	0	0
T172	643	0	0	0
T173	13868	0	0	0
T174	430	0	0	0
T175	524	0	0	0
T176	422	0	0	0
T177	1458	0	0	0
T210	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	170120	0	0
T3	554	119	0	0
T6	26577	0	0	0
T7	903	345	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	186	0	0
T29	4208	0	0	0
T38	0	10	0	0
T39	0	123821	0	0
T40	0	23857	0	0
T161	0	133	0	0
T162	0	51	0	0
T179	0	83	0	0
T236	0	56	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	46	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T29	4208	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T161	0	2	0	0
T162	0	1	0	0
T179	0	2	0	0
T236	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6997779	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	3	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	4	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7000059	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	3	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	4	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	52	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T11	0	1	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T29	4208	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T161	0	2	0	0
T162	0	1	0	0
T236	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	49	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T29	4208	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T161	0	2	0	0
T162	0	1	0	0
T179	0	2	0	0
T236	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	46	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T29	4208	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T161	0	2	0	0
T162	0	1	0	0
T179	0	2	0	0
T236	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	46	0	0
T3	554	1	0	0
T6	26577	0	0	0
T7	903	1	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	1	0	0
T29	4208	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T161	0	2	0	0
T162	0	1	0	0
T179	0	2	0	0
T236	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	170053	0	0
T3	554	117	0	0
T6	26577	0	0	0
T7	903	343	0	0
T8	650	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T21	0	185	0	0
T29	4208	0	0	0
T38	0	9	0	0
T39	0	123819	0	0
T40	0	23856	0	0
T161	0	131	0	0
T162	0	50	0	0
T179	0	80	0	0
T236	0	54	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	23	0	0
T21	327524	1	0	0
T33	483	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T58	2551	0	0	0
T62	782	0	0	0
T63	2318	0	0	0
T71	1304	0	0	0
T72	504	0	0	0
T124	0	1	0	0
T132	404	0	0	0
T133	432	0	0	0
T134	450	0	0	0
T161	0	2	0	0
T162	0	1	0	0
T179	0	1	0	0
T181	0	1	0	0
T249	0	1	0	0
T250	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T21,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T11,T21,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T21,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T11
1	0	Covered	T4,T5,T1
1	1	Covered	T11,T21,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T21,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T21,T36
0	1	Covered	T21,T161,T192
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T21,T36
1	-	Covered	T21,T161,T192

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T21,T36
DetectSt	168	Covered	T11,T21,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T21,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T21,T36
DebounceSt->IdleSt	163	Covered	T210
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T21,T36
IdleSt->DebounceSt	148	Covered	T11,T21,T36
StableSt->IdleSt	206	Covered	T21,T36,T161

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T21,T36
0	1	Covered	T11,T21,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T21,T36
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T21,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T21,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T21,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T21,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T161,T192
StableSt	-	-	-	-	-	-	0	Covered	T11,T21,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	80	0	0
CntIncr_A	8161287	163318	0	0
CntNoWrap_A	8161287	7522666	0	0
DetectStDropOut_A	8161287	0	0	0
DetectedOut_A	8161287	139604	0	0
DetectedPulseOut_A	8161287	40	0	0
DisabledIdleSt_A	8161287	6686348	0	0
DisabledNoDetection_A	8161287	6688621	0	0
EnterDebounceSt_A	8161287	41	0	0
EnterDetectSt_A	8161287	40	0	0
EnterStableSt_A	8161287	40	0	0
PulseIsPulse_A	8161287	40	0	0
StayInStableSt	8161287	139540	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8161287	6745	0	0
gen_low_level_sva.LowLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	80	0	0
T11	498	2	0	0
T12	1513	0	0	0
T21	327524	6	0	0
T25	503	0	0	0
T27	5269	0	0	0
T33	483	0	0	0
T36	0	2	0	0
T40	0	2	0	0
T56	0	2	0	0
T58	2551	0	0	0
T61	841	0	0	0
T95	407	0	0	0
T132	404	0	0	0
T157	0	2	0	0
T161	0	8	0	0
T162	0	4	0	0
T192	0	2	0	0
T239	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	163318	0	0
T11	498	28	0	0
T12	1513	0	0	0
T21	327524	95144	0	0
T25	503	0	0	0
T27	5269	0	0	0
T33	483	0	0	0
T36	0	53	0	0
T40	0	41492	0	0
T56	0	19	0	0
T58	2551	0	0	0
T61	841	0	0	0
T95	407	0	0	0
T132	404	0	0	0
T157	0	59	0	0
T161	0	254	0	0
T162	0	169	0	0
T192	0	88	0	0
T239	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7522666	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	139604	0	0
T11	498	39	0	0
T12	1513	0	0	0
T21	327524	119950	0	0
T25	503	0	0	0
T27	5269	0	0	0
T33	483	0	0	0
T36	0	210	0	0
T40	0	40	0	0
T56	0	20	0	0
T58	2551	0	0	0
T61	841	0	0	0
T95	407	0	0	0
T132	404	0	0	0
T157	0	267	0	0
T161	0	165	0	0
T162	0	90	0	0
T192	0	207	0	0
T239	0	83	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	40	0	0
T11	498	1	0	0
T12	1513	0	0	0
T21	327524	3	0	0
T25	503	0	0	0
T27	5269	0	0	0
T33	483	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T56	0	1	0	0
T58	2551	0	0	0
T61	841	0	0	0
T95	407	0	0	0
T132	404	0	0	0
T157	0	1	0	0
T161	0	4	0	0
T162	0	2	0	0
T192	0	1	0	0
T239	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6686348	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	3	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6688621	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	3	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	41	0	0
T11	498	1	0	0
T12	1513	0	0	0
T21	327524	3	0	0
T25	503	0	0	0
T27	5269	0	0	0
T33	483	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T56	0	1	0	0
T58	2551	0	0	0
T61	841	0	0	0
T95	407	0	0	0
T132	404	0	0	0
T157	0	1	0	0
T161	0	4	0	0
T162	0	2	0	0
T192	0	1	0	0
T239	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	40	0	0
T11	498	1	0	0
T12	1513	0	0	0
T21	327524	3	0	0
T25	503	0	0	0
T27	5269	0	0	0
T33	483	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T56	0	1	0	0
T58	2551	0	0	0
T61	841	0	0	0
T95	407	0	0	0
T132	404	0	0	0
T157	0	1	0	0
T161	0	4	0	0
T162	0	2	0	0
T192	0	1	0	0
T239	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	40	0	0
T11	498	1	0	0
T12	1513	0	0	0
T21	327524	3	0	0
T25	503	0	0	0
T27	5269	0	0	0
T33	483	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T56	0	1	0	0
T58	2551	0	0	0
T61	841	0	0	0
T95	407	0	0	0
T132	404	0	0	0
T157	0	1	0	0
T161	0	4	0	0
T162	0	2	0	0
T192	0	1	0	0
T239	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	40	0	0
T11	498	1	0	0
T12	1513	0	0	0
T21	327524	3	0	0
T25	503	0	0	0
T27	5269	0	0	0
T33	483	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T56	0	1	0	0
T58	2551	0	0	0
T61	841	0	0	0
T95	407	0	0	0
T132	404	0	0	0
T157	0	1	0	0
T161	0	4	0	0
T162	0	2	0	0
T192	0	1	0	0
T239	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	139540	0	0
T11	498	37	0	0
T12	1513	0	0	0
T21	327524	119945	0	0
T25	503	0	0	0
T27	5269	0	0	0
T33	483	0	0	0
T36	0	208	0	0
T40	0	38	0	0
T56	0	19	0	0
T58	2551	0	0	0
T61	841	0	0	0
T95	407	0	0	0
T132	404	0	0	0
T157	0	265	0	0
T161	0	159	0	0
T162	0	86	0	0
T192	0	206	0	0
T239	0	80	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	6745	0	0
T1	960	5	0	0
T2	9426	29	0	0
T3	554	0	0	0
T4	523	5	0	0
T5	855	4	0	0
T6	26577	11	0	0
T7	903	0	0	0
T13	436	1	0	0
T14	790	3	0	0
T15	524	5	0	0
T16	0	4	0	0
T17	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	14	0	0
T21	327524	1	0	0
T33	483	0	0	0
T58	2551	0	0	0
T62	782	0	0	0
T63	2318	0	0	0
T71	1304	0	0	0
T72	504	0	0	0
T80	0	1	0	0
T119	0	1	0	0
T132	404	0	0	0
T133	432	0	0	0
T134	450	0	0	0
T145	0	1	0	0
T158	0	1	0	0
T161	0	2	0	0
T164	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T239	0	1	0	0