Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T27,T28
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T27,T28
1	0	Covered	T2,T28,T41
1	1	Covered	T2,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T27,T28
0	1	Covered	T27,T42,T45
1	0	Covered	T42,T35,T96

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T28,T41
0	1	Covered	T2,T28,T41
1	0	Covered	T82,T251

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T28,T41
1	-	Covered	T2,T28,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T27,T28
DetectSt	168	Covered	T2,T27,T28
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T28,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T27,T28
DebounceSt->IdleSt	163	Covered	T56,T252,T253
DetectSt->IdleSt	186	Covered	T27,T42,T45
DetectSt->StableSt	191	Covered	T2,T28,T41
IdleSt->DebounceSt	148	Covered	T2,T27,T28
StableSt->IdleSt	206	Covered	T2,T28,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T27,T28
0	1	Covered	T2,T27,T28
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T27,T28
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T2,T27,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T252,T253
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T27,T42,T45
DetectSt	-	-	-	-	0	1	-	Covered	T2,T28,T41
DetectSt	-	-	-	-	0	0	-	Covered	T2,T27,T28
StableSt	-	-	-	-	-	-	1	Covered	T2,T28,T41
StableSt	-	-	-	-	-	-	0	Covered	T2,T28,T41
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	2940	0	0
CntIncr_A	8161287	86762	0	0
CntNoWrap_A	8161287	7519806	0	0
DetectStDropOut_A	8161287	417	0	0
DetectedOut_A	8161287	64411	0	0
DetectedPulseOut_A	8161287	799	0	0
DisabledIdleSt_A	8161287	7114046	0	0
DisabledNoDetection_A	8161287	7116198	0	0
EnterDebounceSt_A	8161287	1483	0	0
EnterDetectSt_A	8161287	1457	0	0
EnterStableSt_A	8161287	799	0	0
PulseIsPulse_A	8161287	799	0	0
StayInStableSt	8161287	63528	0	0
gen_high_event_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	712	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	2940	0	0
T2	9426	58	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	6	0	0
T28	0	48	0	0
T29	4208	0	0	0
T35	0	30	0	0
T41	0	12	0	0
T42	0	22	0	0
T43	0	18	0	0
T44	0	48	0	0
T45	0	42	0	0
T76	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	86762	0	0
T2	9426	1537	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	156	0	0
T28	0	864	0	0
T29	4208	0	0	0
T35	0	651	0	0
T41	0	312	0	0
T42	0	691	0	0
T43	0	576	0	0
T44	0	1200	0	0
T45	0	987	0	0
T76	0	1325	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7519806	0	0
T1	960	559	0	0
T2	9426	8967	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	417	0	0
T21	327524	0	0	0
T27	5269	3	0	0
T33	483	0	0	0
T35	0	6	0	0
T42	0	8	0	0
T45	0	21	0	0
T58	2551	0	0	0
T61	841	0	0	0
T62	782	0	0	0
T71	1304	0	0	0
T72	504	0	0	0
T82	0	4	0	0
T96	0	5	0	0
T98	0	13	0	0
T100	0	3	0	0
T132	404	0	0	0
T133	432	0	0	0
T254	0	18	0	0
T255	0	26	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	64411	0	0
T2	9426	2865	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T28	0	1954	0	0
T29	4208	0	0	0
T41	0	795	0	0
T43	0	753	0	0
T44	0	1195	0	0
T76	0	1401	0	0
T126	0	137	0	0
T256	0	2068	0	0
T257	0	1448	0	0
T258	0	1389	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	799	0	0
T2	9426	29	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T28	0	24	0	0
T29	4208	0	0	0
T41	0	6	0	0
T43	0	9	0	0
T44	0	24	0	0
T76	0	25	0	0
T126	0	5	0	0
T256	0	27	0	0
T257	0	24	0	0
T258	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7114046	0	0
T1	960	559	0	0
T2	9426	2196	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7116198	0	0
T1	960	560	0	0
T2	9426	2196	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	1483	0	0
T2	9426	29	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	3	0	0
T28	0	24	0	0
T29	4208	0	0	0
T35	0	15	0	0
T41	0	6	0	0
T42	0	11	0	0
T43	0	9	0	0
T44	0	24	0	0
T45	0	21	0	0
T76	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	1457	0	0
T2	9426	29	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	3	0	0
T28	0	24	0	0
T29	4208	0	0	0
T35	0	15	0	0
T41	0	6	0	0
T42	0	11	0	0
T43	0	9	0	0
T44	0	24	0	0
T45	0	21	0	0
T76	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	799	0	0
T2	9426	29	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T28	0	24	0	0
T29	4208	0	0	0
T41	0	6	0	0
T43	0	9	0	0
T44	0	24	0	0
T76	0	25	0	0
T126	0	5	0	0
T256	0	27	0	0
T257	0	24	0	0
T258	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	799	0	0
T2	9426	29	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T28	0	24	0	0
T29	4208	0	0	0
T41	0	6	0	0
T43	0	9	0	0
T44	0	24	0	0
T76	0	25	0	0
T126	0	5	0	0
T256	0	27	0	0
T257	0	24	0	0
T258	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	63528	0	0
T2	9426	2836	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T28	0	1930	0	0
T29	4208	0	0	0
T41	0	786	0	0
T43	0	742	0	0
T44	0	1171	0	0
T76	0	1376	0	0
T126	0	132	0	0
T256	0	2036	0	0
T257	0	1424	0	0
T258	0	1363	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	712	0	0
T2	9426	29	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T28	0	24	0	0
T29	4208	0	0	0
T41	0	3	0	0
T43	0	7	0	0
T44	0	24	0	0
T76	0	25	0	0
T126	0	5	0	0
T256	0	22	0	0
T257	0	24	0	0
T258	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T29,T9
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T29,T9
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T29,T9,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T29,T9,T33

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T33,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T29,T9
1	0	Covered	T2,T6,T29
1	1	Covered	T29,T9,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T33,T28
0	1	Covered	T46,T97,T99
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T33,T28
0	1	Covered	T9,T33,T28
1	0	Covered	T259

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T33,T28
1	-	Covered	T9,T33,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T29,T9,T33
DetectSt	168	Covered	T9,T33,T28
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T33,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T33,T28
DebounceSt->IdleSt	163	Covered	T29,T22,T24
DetectSt->IdleSt	186	Covered	T46,T97,T99
DetectSt->StableSt	191	Covered	T9,T33,T28
IdleSt->DebounceSt	148	Covered	T29,T9,T33
StableSt->IdleSt	206	Covered	T9,T33,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T29,T9,T33
0	1	Covered	T29,T9,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T33,T28
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T9,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T33,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T22,T24
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T9,T33
DetectSt	-	-	-	-	1	-	-	Covered	T46,T97,T99
DetectSt	-	-	-	-	0	1	-	Covered	T9,T33,T28
DetectSt	-	-	-	-	0	0	-	Covered	T9,T33,T28
StableSt	-	-	-	-	-	-	1	Covered	T9,T33,T28
StableSt	-	-	-	-	-	-	0	Covered	T9,T33,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	934	0	0
CntIncr_A	8161287	46226	0	0
CntNoWrap_A	8161287	7521812	0	0
DetectStDropOut_A	8161287	61	0	0
DetectedOut_A	8161287	14946	0	0
DetectedPulseOut_A	8161287	367	0	0
DisabledIdleSt_A	8161287	7174321	0	0
DisabledNoDetection_A	8161287	7175921	0	0
EnterDebounceSt_A	8161287	504	0	0
EnterDetectSt_A	8161287	432	0	0
EnterStableSt_A	8161287	367	0	0
PulseIsPulse_A	8161287	367	0	0
StayInStableSt	8161287	14560	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	341	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	934	0	0
T8	650	0	0	0
T9	27399	4	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	14	0	0
T24	0	8	0	0
T28	0	6	0	0
T29	4208	1	0	0
T33	0	2	0	0
T41	0	6	0	0
T43	0	4	0	0
T46	0	12	0	0
T49	0	2	0	0
T51	407	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	46226	0	0
T8	650	0	0	0
T9	27399	298	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	881	0	0
T24	0	115	0	0
T28	0	168	0	0
T29	4208	20	0	0
T33	0	25	0	0
T41	0	165	0	0
T43	0	118	0	0
T46	0	349	0	0
T49	0	93	0	0
T51	407	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7521812	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	61	0	0
T24	10012	0	0	0
T26	2473	0	0	0
T38	14538	0	0	0
T46	8867	6	0	0
T77	2339	0	0	0
T97	0	8	0	0
T99	0	3	0	0
T101	0	2	0	0
T102	0	4	0	0
T103	0	3	0	0
T104	0	2	0	0
T105	0	1	0	0
T107	0	3	0	0
T108	0	2	0	0
T111	524	0	0	0
T112	10322	0	0	0
T113	522	0	0	0
T114	522	0	0	0
T115	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	14946	0	0
T9	27399	50	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	231	0	0
T24	0	10	0	0
T25	503	0	0	0
T27	5269	0	0	0
T28	0	175	0	0
T33	0	4	0	0
T34	0	166	0	0
T41	0	231	0	0
T43	0	179	0	0
T49	0	77	0	0
T61	841	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T125	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	367	0	0
T9	27399	2	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	6	0	0
T24	0	3	0	0
T25	503	0	0	0
T27	5269	0	0	0
T28	0	3	0	0
T33	0	1	0	0
T34	0	2	0	0
T41	0	3	0	0
T43	0	2	0	0
T49	0	1	0	0
T61	841	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T125	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7174321	0	0
T1	960	559	0	0
T2	9426	6160	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7175921	0	0
T1	960	560	0	0
T2	9426	6161	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	504	0	0
T8	650	0	0	0
T9	27399	2	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	8	0	0
T24	0	5	0	0
T28	0	3	0	0
T29	4208	1	0	0
T33	0	1	0	0
T41	0	3	0	0
T43	0	2	0	0
T46	0	6	0	0
T49	0	1	0	0
T51	407	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	432	0	0
T9	27399	2	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	6	0	0
T24	0	3	0	0
T25	503	0	0	0
T27	5269	0	0	0
T28	0	3	0	0
T33	0	1	0	0
T34	0	2	0	0
T41	0	3	0	0
T43	0	2	0	0
T46	0	6	0	0
T49	0	1	0	0
T61	841	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	367	0	0
T9	27399	2	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	6	0	0
T24	0	3	0	0
T25	503	0	0	0
T27	5269	0	0	0
T28	0	3	0	0
T33	0	1	0	0
T34	0	2	0	0
T41	0	3	0	0
T43	0	2	0	0
T49	0	1	0	0
T61	841	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T125	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	367	0	0
T9	27399	2	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	6	0	0
T24	0	3	0	0
T25	503	0	0	0
T27	5269	0	0	0
T28	0	3	0	0
T33	0	1	0	0
T34	0	2	0	0
T41	0	3	0	0
T43	0	2	0	0
T49	0	1	0	0
T61	841	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T125	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	14560	0	0
T9	27399	48	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	225	0	0
T24	0	7	0	0
T25	503	0	0	0
T27	5269	0	0	0
T28	0	172	0	0
T33	0	3	0	0
T34	0	164	0	0
T41	0	225	0	0
T43	0	176	0	0
T49	0	76	0	0
T61	841	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T125	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	341	0	0
T9	27399	2	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	6	0	0
T24	0	3	0	0
T25	503	0	0	0
T27	5269	0	0	0
T28	0	3	0	0
T33	0	1	0	0
T34	0	2	0	0
T43	0	1	0	0
T49	0	1	0	0
T61	841	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T125	0	1	0	0
T128	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T27,T28
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T27,T28
1	0	Covered	T2,T28,T41
1	1	Covered	T2,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T27,T28
0	1	Covered	T2,T27,T41
1	0	Covered	T2,T41,T35

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T42,T43
0	1	Covered	T28,T42,T43
1	0	Covered	T43,T83,T260

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T42,T43
1	-	Covered	T28,T42,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T27,T28
DetectSt	168	Covered	T2,T27,T28
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T28,T42,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T27,T28
DebounceSt->IdleSt	163	Covered	T56,T252,T253
DetectSt->IdleSt	186	Covered	T2,T27,T41
DetectSt->StableSt	191	Covered	T28,T42,T43
IdleSt->DebounceSt	148	Covered	T2,T27,T28
StableSt->IdleSt	206	Covered	T28,T42,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T27,T28
0	1	Covered	T2,T27,T28
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T27,T28
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T2,T27,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T252,T253
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T2,T27,T41
DetectSt	-	-	-	-	0	1	-	Covered	T28,T42,T43
DetectSt	-	-	-	-	0	0	-	Covered	T2,T27,T28
StableSt	-	-	-	-	-	-	1	Covered	T28,T42,T43
StableSt	-	-	-	-	-	-	0	Covered	T28,T42,T43
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	3005	0	0
CntIncr_A	8161287	91178	0	0
CntNoWrap_A	8161287	7519741	0	0
DetectStDropOut_A	8161287	386	0	0
DetectedOut_A	8161287	76198	0	0
DetectedPulseOut_A	8161287	897	0	0
DisabledIdleSt_A	8161287	7105423	0	0
DisabledNoDetection_A	8161287	7107565	0	0
EnterDebounceSt_A	8161287	1511	0	0
EnterDetectSt_A	8161287	1495	0	0
EnterStableSt_A	8161287	897	0	0
PulseIsPulse_A	8161287	897	0	0
StayInStableSt	8161287	75207	0	0
gen_high_event_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	761	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	3005	0	0
T2	9426	60	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	44	0	0
T28	0	20	0	0
T29	4208	0	0	0
T35	0	30	0	0
T41	0	54	0	0
T42	0	14	0	0
T43	0	62	0	0
T44	0	48	0	0
T45	0	14	0	0
T76	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	91178	0	0
T2	9426	3169	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	1166	0	0
T28	0	640	0	0
T29	4208	0	0	0
T35	0	645	0	0
T41	0	1876	0	0
T42	0	385	0	0
T43	0	2108	0	0
T44	0	1824	0	0
T45	0	328	0	0
T76	0	896	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7519741	0	0
T1	960	559	0	0
T2	9426	8965	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	386	0	0
T2	9426	8	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	22	0	0
T29	4208	0	0	0
T35	0	10	0	0
T41	0	12	0	0
T45	0	7	0	0
T98	0	25	0	0
T255	0	15	0	0
T256	0	8	0	0
T258	0	8	0	0
T261	0	17	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	76198	0	0
T22	49164	0	0	0
T28	7157	37	0	0
T41	22615	0	0	0
T42	0	2039	0	0
T43	0	1356	0	0
T44	0	1959	0	0
T59	799	0	0	0
T60	1155	0	0	0
T64	1597	0	0	0
T73	505	0	0	0
T74	526	0	0	0
T75	673	0	0	0
T76	0	585	0	0
T96	0	231	0	0
T100	0	2699	0	0
T126	0	3158	0	0
T254	0	1414	0	0
T257	0	1683	0	0
T262	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	897	0	0
T22	49164	0	0	0
T28	7157	10	0	0
T41	22615	0	0	0
T42	0	7	0	0
T43	0	31	0	0
T44	0	24	0	0
T59	799	0	0	0
T60	1155	0	0	0
T64	1597	0	0	0
T73	505	0	0	0
T74	526	0	0	0
T75	673	0	0	0
T76	0	14	0	0
T96	0	13	0	0
T100	0	13	0	0
T126	0	30	0	0
T254	0	17	0	0
T257	0	27	0	0
T262	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7105423	0	0
T1	960	559	0	0
T2	9426	3571	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7107565	0	0
T1	960	560	0	0
T2	9426	3571	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	1511	0	0
T2	9426	30	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	22	0	0
T28	0	10	0	0
T29	4208	0	0	0
T35	0	15	0	0
T41	0	27	0	0
T42	0	7	0	0
T43	0	31	0	0
T44	0	24	0	0
T45	0	7	0	0
T76	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	1495	0	0
T2	9426	30	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	22	0	0
T28	0	10	0	0
T29	4208	0	0	0
T35	0	15	0	0
T41	0	27	0	0
T42	0	7	0	0
T43	0	31	0	0
T44	0	24	0	0
T45	0	7	0	0
T76	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	897	0	0
T22	49164	0	0	0
T28	7157	10	0	0
T41	22615	0	0	0
T42	0	7	0	0
T43	0	31	0	0
T44	0	24	0	0
T59	799	0	0	0
T60	1155	0	0	0
T64	1597	0	0	0
T73	505	0	0	0
T74	526	0	0	0
T75	673	0	0	0
T76	0	14	0	0
T96	0	13	0	0
T100	0	13	0	0
T126	0	30	0	0
T254	0	17	0	0
T257	0	27	0	0
T262	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	897	0	0
T22	49164	0	0	0
T28	7157	10	0	0
T41	22615	0	0	0
T42	0	7	0	0
T43	0	31	0	0
T44	0	24	0	0
T59	799	0	0	0
T60	1155	0	0	0
T64	1597	0	0	0
T73	505	0	0	0
T74	526	0	0	0
T75	673	0	0	0
T76	0	14	0	0
T96	0	13	0	0
T100	0	13	0	0
T126	0	30	0	0
T254	0	17	0	0
T257	0	27	0	0
T262	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	75207	0	0
T22	49164	0	0	0
T28	7157	27	0	0
T41	22615	0	0	0
T42	0	2027	0	0
T43	0	1325	0	0
T44	0	1935	0	0
T59	799	0	0	0
T60	1155	0	0	0
T64	1597	0	0	0
T73	505	0	0	0
T74	526	0	0	0
T75	673	0	0	0
T76	0	571	0	0
T96	0	218	0	0
T100	0	2685	0	0
T126	0	3126	0	0
T254	0	1397	0	0
T257	0	1654	0	0
T262	402	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	761	0	0
T22	49164	0	0	0
T28	7157	10	0	0
T41	22615	0	0	0
T42	0	2	0	0
T43	0	7	0	0
T44	0	24	0	0
T59	799	0	0	0
T60	1155	0	0	0
T64	1597	0	0	0
T73	505	0	0	0
T74	526	0	0	0
T75	673	0	0	0
T76	0	14	0	0
T96	0	13	0	0
T100	0	12	0	0
T126	0	28	0	0
T254	0	17	0	0
T257	0	25	0	0
T262	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T9
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T9,T22

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T28
1	0	Covered	T2,T6,T29
1	1	Covered	T6,T9,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T22
0	1	Covered	T97,T101,T102
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T22
0	1	Covered	T6,T9,T22
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T9,T22
1	-	Covered	T6,T9,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T22
DetectSt	168	Covered	T6,T9,T22
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T9,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T22
DebounceSt->IdleSt	163	Covered	T9,T22,T46
DetectSt->IdleSt	186	Covered	T97,T101,T102
DetectSt->StableSt	191	Covered	T6,T9,T22
IdleSt->DebounceSt	148	Covered	T6,T9,T22
StableSt->IdleSt	206	Covered	T6,T9,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T9,T22
0	1	Covered	T6,T9,T22
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T22
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T22,T46
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T22
DetectSt	-	-	-	-	1	-	-	Covered	T97,T101,T102
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T22
DetectSt	-	-	-	-	0	0	-	Covered	T6,T9,T22
StableSt	-	-	-	-	-	-	1	Covered	T6,T9,T22
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	866	0	0
CntIncr_A	8161287	46197	0	0
CntNoWrap_A	8161287	7521880	0	0
DetectStDropOut_A	8161287	63	0	0
DetectedOut_A	8161287	16099	0	0
DetectedPulseOut_A	8161287	338	0	0
DisabledIdleSt_A	8161287	7146495	0	0
DisabledNoDetection_A	8161287	7148107	0	0
EnterDebounceSt_A	8161287	461	0	0
EnterDetectSt_A	8161287	405	0	0
EnterStableSt_A	8161287	338	0	0
PulseIsPulse_A	8161287	338	0	0
StayInStableSt	8161287	15716	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	291	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	866	0	0
T6	26577	20	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	21	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	23	0	0
T29	4208	0	0	0
T34	0	9	0	0
T42	0	10	0	0
T44	0	1	0	0
T46	0	19	0	0
T51	407	0	0	0
T93	418	0	0	0
T112	0	7	0	0
T128	0	9	0	0
T263	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	46197	0	0
T6	26577	1020	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	1608	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	1978	0	0
T29	4208	0	0	0
T34	0	902	0	0
T42	0	535	0	0
T44	0	31	0	0
T46	0	425	0	0
T51	407	0	0	0
T93	418	0	0	0
T112	0	170	0	0
T128	0	405	0	0
T263	0	156	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7521880	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26086	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	63	0	0
T89	2532	0	0	0
T97	3901	2	0	0
T101	0	3	0	0
T102	0	4	0	0
T108	0	4	0	0
T126	13911	0	0	0
T157	926	0	0	0
T161	7993	0	0	0
T179	0	2	0	0
T225	0	2	0	0
T264	0	6	0	0
T265	0	2	0	0
T266	0	7	0	0
T267	0	5	0	0
T268	506	0	0	0
T269	708	0	0	0
T270	496	0	0	0
T271	492	0	0	0
T272	497	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	16099	0	0
T6	26577	489	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	145	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	201	0	0
T29	4208	0	0	0
T34	0	18	0	0
T42	0	253	0	0
T46	0	131	0	0
T51	407	0	0	0
T93	418	0	0	0
T96	0	29	0	0
T112	0	39	0	0
T126	0	70	0	0
T128	0	180	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	338	0	0
T6	26577	10	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	9	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	11	0	0
T29	4208	0	0	0
T34	0	4	0	0
T42	0	5	0	0
T46	0	9	0	0
T51	407	0	0	0
T93	418	0	0	0
T96	0	1	0	0
T112	0	3	0	0
T126	0	1	0	0
T128	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7146495	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	22163	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7148107	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	22163	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	461	0	0
T6	26577	10	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	12	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	12	0	0
T29	4208	0	0	0
T34	0	5	0	0
T42	0	5	0	0
T44	0	1	0	0
T46	0	10	0	0
T51	407	0	0	0
T93	418	0	0	0
T112	0	4	0	0
T128	0	5	0	0
T263	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	405	0	0
T6	26577	10	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	9	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	11	0	0
T29	4208	0	0	0
T34	0	4	0	0
T42	0	5	0	0
T46	0	9	0	0
T51	407	0	0	0
T93	418	0	0	0
T96	0	1	0	0
T97	0	2	0	0
T112	0	3	0	0
T128	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	338	0	0
T6	26577	10	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	9	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	11	0	0
T29	4208	0	0	0
T34	0	4	0	0
T42	0	5	0	0
T46	0	9	0	0
T51	407	0	0	0
T93	418	0	0	0
T96	0	1	0	0
T112	0	3	0	0
T126	0	1	0	0
T128	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	338	0	0
T6	26577	10	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	9	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	11	0	0
T29	4208	0	0	0
T34	0	4	0	0
T42	0	5	0	0
T46	0	9	0	0
T51	407	0	0	0
T93	418	0	0	0
T96	0	1	0	0
T112	0	3	0	0
T126	0	1	0	0
T128	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	15716	0	0
T6	26577	479	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	136	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	190	0	0
T29	4208	0	0	0
T34	0	14	0	0
T42	0	248	0	0
T46	0	122	0	0
T51	407	0	0	0
T93	418	0	0	0
T96	0	28	0	0
T112	0	36	0	0
T126	0	69	0	0
T128	0	176	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	291	0	0
T6	26577	10	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	9	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	11	0	0
T29	4208	0	0	0
T34	0	4	0	0
T42	0	5	0	0
T46	0	9	0	0
T51	407	0	0	0
T93	418	0	0	0
T96	0	1	0	0
T112	0	3	0	0
T126	0	1	0	0
T128	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T27,T28
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T27,T28
1	0	Covered	T2,T28,T41
1	1	Covered	T2,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T27,T28
0	1	Covered	T27,T42,T45
1	0	Covered	T2,T28,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T43,T44
0	1	Covered	T41,T43,T44
1	0	Covered	T273,T274,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T41,T43,T44
1	-	Covered	T41,T43,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T27,T28
DetectSt	168	Covered	T2,T27,T28
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T41,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T27,T28
DebounceSt->IdleSt	163	Covered	T56,T252,T253
DetectSt->IdleSt	186	Covered	T2,T27,T28
DetectSt->StableSt	191	Covered	T41,T43,T44
IdleSt->DebounceSt	148	Covered	T2,T27,T28
StableSt->IdleSt	206	Covered	T41,T43,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T27,T28
0	1	Covered	T2,T27,T28
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T27,T28
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T2,T27,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T252,T253
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T2,T27,T28
DetectSt	-	-	-	-	0	1	-	Covered	T41,T43,T44
DetectSt	-	-	-	-	0	0	-	Covered	T2,T27,T28
StableSt	-	-	-	-	-	-	1	Covered	T41,T43,T44
StableSt	-	-	-	-	-	-	0	Covered	T41,T43,T44
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	3193	0	0
CntIncr_A	8161287	97978	0	0
CntNoWrap_A	8161287	7519553	0	0
DetectStDropOut_A	8161287	381	0	0
DetectedOut_A	8161287	83558	0	0
DetectedPulseOut_A	8161287	963	0	0
DisabledIdleSt_A	8161287	7099671	0	0
DisabledNoDetection_A	8161287	7101778	0	0
EnterDebounceSt_A	8161287	1609	0	0
EnterDetectSt_A	8161287	1584	0	0
EnterStableSt_A	8161287	963	0	0
PulseIsPulse_A	8161287	963	0	0
StayInStableSt	8161287	82466	0	0
gen_high_event_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	830	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	3193	0	0
T2	9426	58	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	44	0	0
T28	0	26	0	0
T29	4208	0	0	0
T35	0	32	0	0
T41	0	16	0	0
T42	0	28	0	0
T43	0	60	0	0
T44	0	62	0	0
T45	0	34	0	0
T76	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	97978	0	0
T2	9426	3072	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	1166	0	0
T28	0	857	0	0
T29	4208	0	0	0
T35	0	656	0	0
T41	0	384	0	0
T42	0	878	0	0
T43	0	2010	0	0
T44	0	1519	0	0
T45	0	802	0	0
T76	0	1175	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7519553	0	0
T1	960	559	0	0
T2	9426	8967	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	381	0	0
T21	327524	0	0	0
T27	5269	22	0	0
T33	483	0	0	0
T42	0	11	0	0
T45	0	17	0	0
T56	0	1	0	0
T58	2551	0	0	0
T61	841	0	0	0
T62	782	0	0	0
T71	1304	0	0	0
T72	504	0	0	0
T98	0	12	0	0
T132	404	0	0	0
T133	432	0	0	0
T255	0	26	0	0
T261	0	10	0	0
T275	0	8	0	0
T276	0	22	0	0
T277	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	83558	0	0
T22	49164	0	0	0
T35	0	1467	0	0
T41	22615	1273	0	0
T42	17868	0	0	0
T43	0	2779	0	0
T44	0	1587	0	0
T45	4966	0	0	0
T52	527	0	0	0
T53	577	0	0	0
T60	1155	0	0	0
T64	1597	0	0	0
T73	505	0	0	0
T74	526	0	0	0
T76	0	1701	0	0
T100	0	1749	0	0
T126	0	1194	0	0
T256	0	895	0	0
T257	0	960	0	0
T258	0	1271	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	963	0	0
T22	49164	0	0	0
T35	0	16	0	0
T41	22615	8	0	0
T42	17868	0	0	0
T43	0	30	0	0
T44	0	31	0	0
T45	4966	0	0	0
T52	527	0	0	0
T53	577	0	0	0
T60	1155	0	0	0
T64	1597	0	0	0
T73	505	0	0	0
T74	526	0	0	0
T76	0	25	0	0
T100	0	18	0	0
T126	0	14	0	0
T256	0	22	0	0
T257	0	11	0	0
T258	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7099671	0	0
T1	960	559	0	0
T2	9426	3571	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7101778	0	0
T1	960	560	0	0
T2	9426	3571	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	1609	0	0
T2	9426	29	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	22	0	0
T28	0	13	0	0
T29	4208	0	0	0
T35	0	16	0	0
T41	0	8	0	0
T42	0	14	0	0
T43	0	30	0	0
T44	0	31	0	0
T45	0	17	0	0
T76	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	1584	0	0
T2	9426	29	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	22	0	0
T28	0	13	0	0
T29	4208	0	0	0
T35	0	16	0	0
T41	0	8	0	0
T42	0	14	0	0
T43	0	30	0	0
T44	0	31	0	0
T45	0	17	0	0
T76	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	963	0	0
T22	49164	0	0	0
T35	0	16	0	0
T41	22615	8	0	0
T42	17868	0	0	0
T43	0	30	0	0
T44	0	31	0	0
T45	4966	0	0	0
T52	527	0	0	0
T53	577	0	0	0
T60	1155	0	0	0
T64	1597	0	0	0
T73	505	0	0	0
T74	526	0	0	0
T76	0	25	0	0
T100	0	18	0	0
T126	0	14	0	0
T256	0	22	0	0
T257	0	11	0	0
T258	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	963	0	0
T22	49164	0	0	0
T35	0	16	0	0
T41	22615	8	0	0
T42	17868	0	0	0
T43	0	30	0	0
T44	0	31	0	0
T45	4966	0	0	0
T52	527	0	0	0
T53	577	0	0	0
T60	1155	0	0	0
T64	1597	0	0	0
T73	505	0	0	0
T74	526	0	0	0
T76	0	25	0	0
T100	0	18	0	0
T126	0	14	0	0
T256	0	22	0	0
T257	0	11	0	0
T258	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	82466	0	0
T22	49164	0	0	0
T35	0	1451	0	0
T41	22615	1260	0	0
T42	17868	0	0	0
T43	0	2748	0	0
T44	0	1556	0	0
T45	4966	0	0	0
T52	527	0	0	0
T53	577	0	0	0
T60	1155	0	0	0
T64	1597	0	0	0
T73	505	0	0	0
T74	526	0	0	0
T76	0	1676	0	0
T100	0	1729	0	0
T126	0	1178	0	0
T256	0	873	0	0
T257	0	949	0	0
T258	0	1243	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	830	0	0
T22	49164	0	0	0
T35	0	16	0	0
T41	22615	3	0	0
T42	17868	0	0	0
T43	0	29	0	0
T44	0	31	0	0
T45	4966	0	0	0
T52	527	0	0	0
T53	577	0	0	0
T60	1155	0	0	0
T64	1597	0	0	0
T73	505	0	0	0
T74	526	0	0	0
T76	0	25	0	0
T100	0	16	0	0
T126	0	12	0	0
T256	0	22	0	0
T257	0	11	0	0
T258	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T9
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T9,T41

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T41
1	0	Covered	T2,T6,T29
1	1	Covered	T6,T9,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T41
0	1	Covered	T6,T22,T46
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T41,T22
0	1	Covered	T9,T22,T34
1	0	Covered	T76,T56,T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T41,T22
1	-	Covered	T9,T22,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T41
DetectSt	168	Covered	T6,T9,T41
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T41,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T41
DebounceSt->IdleSt	163	Covered	T6,T22,T46
DetectSt->IdleSt	186	Covered	T6,T22,T46
DetectSt->StableSt	191	Covered	T9,T41,T22
IdleSt->DebounceSt	148	Covered	T6,T9,T41
StableSt->IdleSt	206	Covered	T9,T41,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T9,T41
0	1	Covered	T6,T9,T41
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T41
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T22,T46
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T41
DetectSt	-	-	-	-	1	-	-	Covered	T6,T22,T46
DetectSt	-	-	-	-	0	1	-	Covered	T9,T41,T22
DetectSt	-	-	-	-	0	0	-	Covered	T6,T9,T41
StableSt	-	-	-	-	-	-	1	Covered	T9,T22,T34
StableSt	-	-	-	-	-	-	0	Covered	T9,T41,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	941	0	0
CntIncr_A	8161287	51013	0	0
CntNoWrap_A	8161287	7521805	0	0
DetectStDropOut_A	8161287	94	0	0
DetectedOut_A	8161287	15434	0	0
DetectedPulseOut_A	8161287	353	0	0
DisabledIdleSt_A	8161287	7146354	0	0
DisabledNoDetection_A	8161287	7147963	0	0
EnterDebounceSt_A	8161287	490	0	0
EnterDetectSt_A	8161287	451	0	0
EnterStableSt_A	8161287	353	0	0
PulseIsPulse_A	8161287	353	0	0
StayInStableSt	8161287	15031	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	299	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	941	0	0
T6	26577	9	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	4	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	28	0	0
T29	4208	0	0	0
T34	0	24	0	0
T35	0	7	0	0
T41	0	2	0	0
T43	0	2	0	0
T46	0	24	0	0
T51	407	0	0	0
T76	0	2	0	0
T93	418	0	0	0
T128	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	51013	0	0
T6	26577	662	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	200	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	2177	0	0
T29	4208	0	0	0
T34	0	1836	0	0
T35	0	187	0	0
T41	0	82	0	0
T43	0	52	0	0
T46	0	707	0	0
T51	407	0	0	0
T76	0	39	0	0
T93	418	0	0	0
T128	0	538	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7521805	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26097	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	94	0	0
T6	26577	4	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	2	0	0
T29	4208	0	0	0
T46	0	11	0	0
T51	407	0	0	0
T93	418	0	0	0
T97	0	9	0	0
T102	0	1	0	0
T103	0	12	0	0
T104	0	10	0	0
T179	0	3	0	0
T265	0	11	0	0
T278	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	15434	0	0
T9	27399	148	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	407	0	0
T25	503	0	0	0
T27	5269	0	0	0
T34	0	680	0	0
T35	0	243	0	0
T41	0	50	0	0
T43	0	96	0	0
T61	841	0	0	0
T76	0	108	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T126	0	161	0	0
T128	0	96	0	0
T143	0	214	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	353	0	0
T9	27399	2	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	11	0	0
T25	503	0	0	0
T27	5269	0	0	0
T34	0	12	0	0
T35	0	3	0	0
T41	0	1	0	0
T43	0	1	0	0
T61	841	0	0	0
T76	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T126	0	2	0	0
T128	0	4	0	0
T143	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7146354	0	0
T1	960	559	0	0
T2	9426	9025	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	22163	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7147963	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	22163	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	490	0	0
T6	26577	5	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	2	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	15	0	0
T29	4208	0	0	0
T34	0	12	0	0
T35	0	4	0	0
T41	0	1	0	0
T43	0	1	0	0
T46	0	13	0	0
T51	407	0	0	0
T76	0	1	0	0
T93	418	0	0	0
T128	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	451	0	0
T6	26577	4	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	2	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	13	0	0
T29	4208	0	0	0
T34	0	12	0	0
T35	0	3	0	0
T41	0	1	0	0
T43	0	1	0	0
T46	0	11	0	0
T51	407	0	0	0
T76	0	1	0	0
T93	418	0	0	0
T128	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	353	0	0
T9	27399	2	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	11	0	0
T25	503	0	0	0
T27	5269	0	0	0
T34	0	12	0	0
T35	0	3	0	0
T41	0	1	0	0
T43	0	1	0	0
T61	841	0	0	0
T76	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T126	0	2	0	0
T128	0	4	0	0
T143	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	353	0	0
T9	27399	2	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	11	0	0
T25	503	0	0	0
T27	5269	0	0	0
T34	0	12	0	0
T35	0	3	0	0
T41	0	1	0	0
T43	0	1	0	0
T61	841	0	0	0
T76	0	1	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T126	0	2	0	0
T128	0	4	0	0
T143	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	15031	0	0
T9	27399	146	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	396	0	0
T25	503	0	0	0
T27	5269	0	0	0
T34	0	668	0	0
T35	0	240	0	0
T41	0	48	0	0
T43	0	94	0	0
T61	841	0	0	0
T76	0	107	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T126	0	157	0	0
T128	0	92	0	0
T143	0	211	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	299	0	0
T9	27399	2	0	0
T10	561	0	0	0
T11	498	0	0	0
T12	1513	0	0	0
T22	0	11	0	0
T25	503	0	0	0
T27	5269	0	0	0
T34	0	12	0	0
T35	0	3	0	0
T61	841	0	0	0
T93	418	0	0	0
T94	406	0	0	0
T95	407	0	0	0
T99	0	12	0	0
T101	0	5	0	0
T128	0	4	0	0
T143	0	3	0	0
T152	0	2	0	0
T279	0	4	0	0