Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T27,T28
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T27,T28
1	0	Covered	T2,T28,T41
1	1	Covered	T2,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T27,T28
0	1	Covered	T27,T42,T45
1	0	Covered	T28,T42,T35

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T41,T43
0	1	Covered	T2,T41,T43
1	0	Covered	T56,T222,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T41,T43
1	-	Covered	T2,T41,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T27,T28
DetectSt	168	Covered	T2,T27,T28
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T41,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T27,T28
DebounceSt->IdleSt	163	Covered	T56,T252,T253
DetectSt->IdleSt	186	Covered	T27,T28,T42
DetectSt->StableSt	191	Covered	T2,T41,T43
IdleSt->DebounceSt	148	Covered	T2,T27,T28
StableSt->IdleSt	206	Covered	T2,T41,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T27,T28
0	1	Covered	T2,T27,T28
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T27,T28
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T2,T27,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T252,T253
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T27,T28,T42
DetectSt	-	-	-	-	0	1	-	Covered	T2,T41,T43
DetectSt	-	-	-	-	0	0	-	Covered	T2,T27,T28
StableSt	-	-	-	-	-	-	1	Covered	T2,T41,T43
StableSt	-	-	-	-	-	-	0	Covered	T2,T41,T43
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	3195	0	0
CntIncr_A	8161287	98670	0	0
CntNoWrap_A	8161287	7519551	0	0
DetectStDropOut_A	8161287	460	0	0
DetectedOut_A	8161287	71916	0	0
DetectedPulseOut_A	8161287	847	0	0
DisabledIdleSt_A	8161287	7109781	0	0
DisabledNoDetection_A	8161287	7111893	0	0
EnterDebounceSt_A	8161287	1611	0	0
EnterDetectSt_A	8161287	1585	0	0
EnterStableSt_A	8161287	847	0	0
PulseIsPulse_A	8161287	847	0	0
StayInStableSt	8161287	70945	0	0
gen_high_event_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	701	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	3195	0	0
T2	9426	32	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	58	0	0
T28	0	8	0	0
T29	4208	0	0	0
T35	0	56	0	0
T41	0	28	0	0
T42	0	20	0	0
T43	0	12	0	0
T44	0	30	0	0
T45	0	16	0	0
T76	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	98670	0	0
T2	9426	848	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	1538	0	0
T28	0	263	0	0
T29	4208	0	0	0
T35	0	1218	0	0
T41	0	546	0	0
T42	0	630	0	0
T43	0	408	0	0
T44	0	1050	0	0
T45	0	372	0	0
T76	0	1887	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7519551	0	0
T1	960	559	0	0
T2	9426	8993	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	460	0	0
T21	327524	0	0	0
T27	5269	29	0	0
T33	483	0	0	0
T35	0	19	0	0
T42	0	7	0	0
T45	0	8	0	0
T58	2551	0	0	0
T61	841	0	0	0
T62	782	0	0	0
T71	1304	0	0	0
T72	504	0	0	0
T76	0	8	0	0
T98	0	4	0	0
T132	404	0	0	0
T133	432	0	0	0
T254	0	17	0	0
T255	0	26	0	0
T256	0	3	0	0
T258	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	71916	0	0
T2	9426	1024	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T29	4208	0	0	0
T41	0	2770	0	0
T43	0	737	0	0
T44	0	443	0	0
T82	0	344	0	0
T96	0	1176	0	0
T100	0	1816	0	0
T126	0	2558	0	0
T257	0	1556	0	0
T280	0	187	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	847	0	0
T2	9426	16	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T29	4208	0	0	0
T41	0	14	0	0
T43	0	6	0	0
T44	0	15	0	0
T82	0	11	0	0
T96	0	31	0	0
T100	0	16	0	0
T126	0	30	0	0
T257	0	25	0	0
T280	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7109781	0	0
T1	960	559	0	0
T2	9426	3368	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26106	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7111893	0	0
T1	960	560	0	0
T2	9426	3368	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	1611	0	0
T2	9426	16	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	29	0	0
T28	0	4	0	0
T29	4208	0	0	0
T35	0	28	0	0
T41	0	14	0	0
T42	0	10	0	0
T43	0	6	0	0
T44	0	15	0	0
T45	0	8	0	0
T76	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	1585	0	0
T2	9426	16	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T27	0	29	0	0
T28	0	4	0	0
T29	4208	0	0	0
T35	0	28	0	0
T41	0	14	0	0
T42	0	10	0	0
T43	0	6	0	0
T44	0	15	0	0
T45	0	8	0	0
T76	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	847	0	0
T2	9426	16	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T29	4208	0	0	0
T41	0	14	0	0
T43	0	6	0	0
T44	0	15	0	0
T82	0	11	0	0
T96	0	31	0	0
T100	0	16	0	0
T126	0	30	0	0
T257	0	25	0	0
T280	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	847	0	0
T2	9426	16	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T29	4208	0	0	0
T41	0	14	0	0
T43	0	6	0	0
T44	0	15	0	0
T82	0	11	0	0
T96	0	31	0	0
T100	0	16	0	0
T126	0	30	0	0
T257	0	25	0	0
T280	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	70945	0	0
T2	9426	1008	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T29	4208	0	0	0
T41	0	2749	0	0
T43	0	730	0	0
T44	0	428	0	0
T82	0	332	0	0
T96	0	1142	0	0
T100	0	1798	0	0
T126	0	2526	0	0
T257	0	1530	0	0
T280	0	183	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	701	0	0
T2	9426	16	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T29	4208	0	0	0
T41	0	7	0	0
T43	0	5	0	0
T44	0	15	0	0
T82	0	10	0	0
T96	0	28	0	0
T100	0	14	0	0
T126	0	28	0	0
T257	0	24	0	0
T280	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T9
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T2,T6,T29
1	1	Covered	T2,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T9
0	1	Covered	T6,T22,T101
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T41
0	1	Covered	T2,T9,T22
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T41
1	-	Covered	T2,T9,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T9
DetectSt	168	Covered	T2,T6,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T9,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T9
DebounceSt->IdleSt	163	Covered	T99,T100,T101
DetectSt->IdleSt	186	Covered	T6,T22,T101
DetectSt->StableSt	191	Covered	T2,T9,T41
IdleSt->DebounceSt	148	Covered	T2,T6,T9
StableSt->IdleSt	206	Covered	T2,T9,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T9
0	1	Covered	T2,T6,T9
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T99,T100,T101
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T9
DetectSt	-	-	-	-	1	-	-	Covered	T6,T22,T101
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T41
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T9
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T22
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8161287	943	0	0
CntIncr_A	8161287	46779	0	0
CntNoWrap_A	8161287	7521803	0	0
DetectStDropOut_A	8161287	49	0	0
DetectedOut_A	8161287	17136	0	0
DetectedPulseOut_A	8161287	397	0	0
DisabledIdleSt_A	8161287	7164067	0	0
DisabledNoDetection_A	8161287	7165689	0	0
EnterDebounceSt_A	8161287	494	0	0
EnterDetectSt_A	8161287	449	0	0
EnterStableSt_A	8161287	397	0	0
PulseIsPulse_A	8161287	397	0	0
StayInStableSt	8161287	16676	0	0
gen_high_level_sva.HighLevelEvent_A	8161287	7525074	0	0
gen_not_sticky_sva.StableStDropOut_A	8161287	332	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	943	0	0
T2	9426	2	0	0
T3	554	0	0	0
T6	26577	4	0	0
T7	903	0	0	0
T9	0	26	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	8	0	0
T29	4208	0	0	0
T41	0	12	0	0
T43	0	2	0	0
T46	0	4	0	0
T96	0	6	0	0
T112	0	6	0	0
T128	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	46779	0	0
T2	9426	65	0	0
T3	554	0	0	0
T6	26577	300	0	0
T7	903	0	0	0
T9	0	1560	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	677	0	0
T29	4208	0	0	0
T41	0	318	0	0
T43	0	68	0	0
T46	0	80	0	0
T96	0	186	0	0
T112	0	144	0	0
T128	0	267	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7521803	0	0
T1	960	559	0	0
T2	9426	9023	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	26102	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	49	0	0
T6	26577	2	0	0
T7	903	0	0	0
T8	650	0	0	0
T9	27399	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	1	0	0
T29	4208	0	0	0
T51	407	0	0	0
T57	0	1	0	0
T93	418	0	0	0
T101	0	4	0	0
T108	0	4	0	0
T197	0	6	0	0
T281	0	6	0	0
T282	0	8	0	0
T283	0	3	0	0
T284	0	14	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	17136	0	0
T2	9426	74	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T9	0	711	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	38	0	0
T29	4208	0	0	0
T41	0	475	0	0
T43	0	81	0	0
T46	0	36	0	0
T96	0	82	0	0
T97	0	37	0	0
T112	0	33	0	0
T128	0	135	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	397	0	0
T2	9426	1	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T9	0	13	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	3	0	0
T29	4208	0	0	0
T41	0	6	0	0
T43	0	1	0	0
T46	0	2	0	0
T96	0	3	0	0
T97	0	8	0	0
T112	0	3	0	0
T128	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7164067	0	0
T1	960	559	0	0
T2	9426	8001	0	0
T3	554	153	0	0
T4	523	122	0	0
T5	855	454	0	0
T6	26577	22163	0	0
T7	903	502	0	0
T13	436	35	0	0
T14	790	389	0	0
T15	524	123	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7165689	0	0
T1	960	560	0	0
T2	9426	8002	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	22163	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	494	0	0
T2	9426	1	0	0
T3	554	0	0	0
T6	26577	2	0	0
T7	903	0	0	0
T9	0	13	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	4	0	0
T29	4208	0	0	0
T41	0	6	0	0
T43	0	1	0	0
T46	0	2	0	0
T96	0	3	0	0
T112	0	3	0	0
T128	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	449	0	0
T2	9426	1	0	0
T3	554	0	0	0
T6	26577	2	0	0
T7	903	0	0	0
T9	0	13	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	4	0	0
T29	4208	0	0	0
T41	0	6	0	0
T43	0	1	0	0
T46	0	2	0	0
T96	0	3	0	0
T112	0	3	0	0
T128	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	397	0	0
T2	9426	1	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T9	0	13	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	3	0	0
T29	4208	0	0	0
T41	0	6	0	0
T43	0	1	0	0
T46	0	2	0	0
T96	0	3	0	0
T97	0	8	0	0
T112	0	3	0	0
T128	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	397	0	0
T2	9426	1	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T9	0	13	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	3	0	0
T29	4208	0	0	0
T41	0	6	0	0
T43	0	1	0	0
T46	0	2	0	0
T96	0	3	0	0
T97	0	8	0	0
T112	0	3	0	0
T128	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	16676	0	0
T2	9426	73	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T9	0	698	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	35	0	0
T29	4208	0	0	0
T41	0	463	0	0
T43	0	80	0	0
T46	0	34	0	0
T96	0	76	0	0
T97	0	29	0	0
T112	0	30	0	0
T128	0	132	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	7525074	0	0
T1	960	560	0	0
T2	9426	9026	0	0
T3	554	154	0	0
T4	523	123	0	0
T5	855	455	0	0
T6	26577	26117	0	0
T7	903	503	0	0
T13	436	36	0	0
T14	790	390	0	0
T15	524	124	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8161287	332	0	0
T2	9426	1	0	0
T3	554	0	0	0
T6	26577	0	0	0
T7	903	0	0	0
T9	0	13	0	0
T13	436	0	0	0
T14	790	0	0	0
T15	524	0	0	0
T16	448	0	0	0
T17	506	0	0	0
T22	0	3	0	0
T29	4208	0	0	0
T43	0	1	0	0
T46	0	2	0	0
T97	0	8	0	0
T112	0	3	0	0
T128	0	3	0	0
T143	0	6	0	0
T279	0	4	0	0