Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1335139790	12024	0	0
auto_block_debounce_ctl_rd_A	1335139790	1803	0	0
auto_block_out_ctl_rd_A	1335139790	2463	0	0
com_det_ctl_0_rd_A	1335139790	4239	0	0
com_det_ctl_1_rd_A	1335139790	4235	0	0
com_det_ctl_2_rd_A	1335139790	4453	0	0
com_det_ctl_3_rd_A	1335139790	4243	0	0
com_out_ctl_0_rd_A	1335139790	4663	0	0
com_out_ctl_1_rd_A	1335139790	4725	0	0
com_out_ctl_2_rd_A	1335139790	4852	0	0
com_out_ctl_3_rd_A	1335139790	4811	0	0
com_pre_det_ctl_0_rd_A	1335139790	1519	0	0
com_pre_det_ctl_1_rd_A	1335139790	1585	0	0
com_pre_det_ctl_2_rd_A	1335139790	1439	0	0
com_pre_det_ctl_3_rd_A	1335139790	1492	0	0
com_pre_sel_ctl_0_rd_A	1335139790	4978	0	0
com_pre_sel_ctl_1_rd_A	1335139790	5156	0	0
com_pre_sel_ctl_2_rd_A	1335139790	5052	0	0
com_pre_sel_ctl_3_rd_A	1335139790	5068	0	0
com_sel_ctl_0_rd_A	1335139790	4889	0	0
com_sel_ctl_1_rd_A	1335139790	4817	0	0
com_sel_ctl_2_rd_A	1335139790	5068	0	0
com_sel_ctl_3_rd_A	1335139790	4874	0	0
ec_rst_ctl_rd_A	1335139790	2671	0	0
intr_enable_rd_A	1335139790	2350	0	0
key_intr_ctl_rd_A	1335139790	3285	0	0
key_intr_debounce_ctl_rd_A	1335139790	1472	0	0
key_invert_ctl_rd_A	1335139790	5502	0	0
pin_allowed_ctl_rd_A	1335139790	5967	0	0
pin_out_ctl_rd_A	1335139790	4662	0	0
pin_out_value_rd_A	1335139790	4895	0	0
regwen_rd_A	1335139790	1695	0	0
ulp_ac_debounce_ctl_rd_A	1335139790	1612	0	0
ulp_ctl_rd_A	1335139790	1614	0	0
ulp_lid_debounce_ctl_rd_A	1335139790	1540	0	0
ulp_pwrb_debounce_ctl_rd_A	1335139790	1555	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	12024	0	0
T22	537971	8	0	0
T23	233678	0	0	0
T24	0	19	0	0
T36	0	20	0	0
T37	0	30	0	0
T38	0	22	0	0
T42	223356	0	0	0
T45	238373	0	0	0
T46	103962	4	0	0
T49	0	2	0	0
T52	55412	0	0	0
T53	144413	0	0	0
T54	53911	0	0	0
T55	112169	2	0	0
T68	0	9	0	0
T70	205112	0	0	0
T310	0	4	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	1803	0	0
T24	474402	0	0	0
T26	136028	0	0	0
T38	174428	0	0	0
T46	103962	0	0	0
T47	0	19	0	0
T55	112169	29	0	0
T70	205112	0	0	0
T80	0	50	0	0
T92	0	8	0	0
T105	0	37	0	0
T111	73325	0	0	0
T112	258062	0	0	0
T113	255757	0	0	0
T114	248395	0	0	0
T152	0	37	0	0
T161	0	22	0	0
T162	0	27	0	0
T311	0	9	0	0
T312	0	10	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	2463	0	0
T24	474402	0	0	0
T26	136028	0	0	0
T38	174428	0	0	0
T46	103962	0	0	0
T47	0	10	0	0
T55	112169	14	0	0
T70	205112	0	0	0
T80	0	58	0	0
T92	0	12	0	0
T105	0	36	0	0
T111	73325	0	0	0
T112	258062	0	0	0
T113	255757	0	0	0
T114	248395	0	0	0
T118	0	6	0	0
T152	0	40	0	0
T161	0	15	0	0
T162	0	37	0	0
T311	0	10	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	4239	0	0
T2	471338	19	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	37	0	0
T29	129204	0	0	0
T34	0	47	0	0
T43	0	47	0	0
T55	0	21	0	0
T76	0	30	0	0
T97	0	48	0	0
T112	0	60	0	0
T126	0	27	0	0
T263	0	67	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	4235	0	0
T2	471338	10	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	36	0	0
T29	129204	0	0	0
T34	0	74	0	0
T43	0	22	0	0
T55	0	23	0	0
T76	0	17	0	0
T97	0	51	0	0
T112	0	67	0	0
T126	0	50	0	0
T263	0	60	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	4453	0	0
T2	471338	23	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	32	0	0
T29	129204	0	0	0
T34	0	63	0	0
T43	0	37	0	0
T55	0	22	0	0
T76	0	24	0	0
T97	0	59	0	0
T112	0	81	0	0
T126	0	42	0	0
T263	0	78	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	4243	0	0
T2	471338	5	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	36	0	0
T29	129204	0	0	0
T34	0	91	0	0
T43	0	34	0	0
T55	0	18	0	0
T76	0	41	0	0
T97	0	50	0	0
T112	0	74	0	0
T126	0	35	0	0
T263	0	62	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	4663	0	0
T2	471338	17	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	25	0	0
T29	129204	0	0	0
T34	0	54	0	0
T43	0	27	0	0
T55	0	21	0	0
T76	0	26	0	0
T97	0	39	0	0
T112	0	60	0	0
T126	0	37	0	0
T263	0	56	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	4725	0	0
T2	471338	23	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	41	0	0
T29	129204	0	0	0
T34	0	42	0	0
T43	0	38	0	0
T55	0	22	0	0
T76	0	36	0	0
T97	0	26	0	0
T112	0	61	0	0
T126	0	18	0	0
T263	0	68	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	4852	0	0
T2	471338	37	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	27	0	0
T29	129204	0	0	0
T34	0	84	0	0
T43	0	23	0	0
T55	0	5	0	0
T76	0	25	0	0
T97	0	26	0	0
T112	0	55	0	0
T126	0	55	0	0
T263	0	53	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	4811	0	0
T2	471338	14	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	40	0	0
T29	129204	0	0	0
T34	0	65	0	0
T43	0	36	0	0
T55	0	32	0	0
T76	0	12	0	0
T97	0	72	0	0
T112	0	80	0	0
T126	0	53	0	0
T263	0	64	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	1519	0	0
T24	474402	0	0	0
T26	136028	0	0	0
T38	174428	0	0	0
T46	103962	0	0	0
T55	112169	13	0	0
T70	205112	0	0	0
T80	0	26	0	0
T105	0	25	0	0
T111	73325	0	0	0
T112	258062	0	0	0
T113	255757	0	0	0
T114	248395	0	0	0
T148	0	44	0	0
T152	0	5	0	0
T153	0	2	0	0
T154	0	46	0	0
T162	0	17	0	0
T313	0	5	0	0
T314	0	27	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	1585	0	0
T24	474402	0	0	0
T26	136028	0	0	0
T38	174428	0	0	0
T46	103962	0	0	0
T55	112169	22	0	0
T70	205112	0	0	0
T80	0	36	0	0
T105	0	24	0	0
T111	73325	0	0	0
T112	258062	0	0	0
T113	255757	0	0	0
T114	248395	0	0	0
T152	0	20	0	0
T153	0	9	0	0
T154	0	43	0	0
T162	0	15	0	0
T312	0	2	0	0
T313	0	34	0	0
T314	0	10	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	1439	0	0
T24	474402	0	0	0
T26	136028	0	0	0
T38	174428	0	0	0
T46	103962	0	0	0
T55	112169	17	0	0
T70	205112	0	0	0
T80	0	26	0	0
T105	0	6	0	0
T111	73325	0	0	0
T112	258062	0	0	0
T113	255757	0	0	0
T114	248395	0	0	0
T152	0	31	0	0
T153	0	11	0	0
T154	0	30	0	0
T162	0	33	0	0
T312	0	7	0	0
T313	0	16	0	0
T314	0	37	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	1492	0	0
T24	474402	0	0	0
T26	136028	0	0	0
T38	174428	0	0	0
T46	103962	0	0	0
T55	112169	11	0	0
T70	205112	0	0	0
T80	0	42	0	0
T105	0	4	0	0
T111	73325	0	0	0
T112	258062	0	0	0
T113	255757	0	0	0
T114	248395	0	0	0
T152	0	13	0	0
T153	0	4	0	0
T154	0	33	0	0
T162	0	15	0	0
T312	0	12	0	0
T313	0	20	0	0
T314	0	23	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	4978	0	0
T2	471338	2	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	38	0	0
T29	129204	0	0	0
T34	0	94	0	0
T43	0	35	0	0
T55	0	23	0	0
T76	0	37	0	0
T97	0	31	0	0
T112	0	85	0	0
T126	0	16	0	0
T263	0	71	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	5156	0	0
T2	471338	18	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	50	0	0
T29	129204	0	0	0
T34	0	68	0	0
T43	0	17	0	0
T55	0	14	0	0
T76	0	27	0	0
T97	0	43	0	0
T112	0	106	0	0
T126	0	37	0	0
T263	0	86	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	5052	0	0
T2	471338	44	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	33	0	0
T29	129204	0	0	0
T34	0	71	0	0
T43	0	23	0	0
T55	0	16	0	0
T76	0	42	0	0
T97	0	43	0	0
T112	0	75	0	0
T126	0	28	0	0
T263	0	66	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	5068	0	0
T2	471338	30	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	23	0	0
T29	129204	0	0	0
T34	0	55	0	0
T43	0	21	0	0
T55	0	23	0	0
T76	0	17	0	0
T97	0	34	0	0
T112	0	61	0	0
T126	0	39	0	0
T263	0	76	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	4889	0	0
T2	471338	38	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	45	0	0
T29	129204	0	0	0
T34	0	54	0	0
T43	0	38	0	0
T55	0	15	0	0
T76	0	13	0	0
T97	0	47	0	0
T112	0	70	0	0
T126	0	44	0	0
T263	0	73	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	4817	0	0
T2	471338	26	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	32	0	0
T29	129204	0	0	0
T34	0	86	0	0
T43	0	30	0	0
T55	0	12	0	0
T76	0	23	0	0
T97	0	52	0	0
T112	0	71	0	0
T126	0	50	0	0
T263	0	64	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	5068	0	0
T2	471338	27	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	43	0	0
T29	129204	0	0	0
T34	0	73	0	0
T43	0	38	0	0
T55	0	23	0	0
T76	0	26	0	0
T97	0	54	0	0
T112	0	75	0	0
T126	0	26	0	0
T263	0	57	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	4874	0	0
T2	471338	19	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	18	0	0
T29	129204	0	0	0
T34	0	80	0	0
T43	0	29	0	0
T55	0	21	0	0
T76	0	39	0	0
T97	0	34	0	0
T112	0	69	0	0
T126	0	34	0	0
T263	0	63	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	2671	0	0
T2	471338	3	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T28	0	3	0	0
T29	129204	0	0	0
T34	0	49	0	0
T43	0	8	0	0
T45	0	2	0	0
T55	0	11	0	0
T76	0	2	0	0
T112	0	17	0	0
T190	0	6	0	0
T263	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	2350	0	0
T28	894580	0	0	0
T41	271382	0	0	0
T55	0	55	0	0
T59	155475	0	0	0
T60	211422	0	0	0
T63	53936	0	0	0
T71	652649	13	0	0
T72	118369	0	0	0
T75	336525	0	0	0
T80	0	37	0	0
T105	0	42	0	0
T134	51817	0	0	0
T152	0	40	0	0
T153	0	4	0	0
T161	0	78	0	0
T162	0	21	0	0
T262	193087	0	0	0
T312	0	10	0	0
T315	0	8	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	3285	0	0
T24	474402	0	0	0
T26	136028	0	0	0
T38	174428	0	0	0
T46	103962	0	0	0
T55	112169	24	0	0
T56	0	75	0	0
T70	205112	0	0	0
T111	73325	0	0	0
T112	258062	0	0	0
T113	255757	0	0	0
T114	248395	0	0	0
T152	0	20	0	0
T161	0	10	0	0
T162	0	25	0	0
T178	0	4	0	0
T191	0	7	0	0
T192	0	4	0	0
T239	0	1	0	0
T312	0	9	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	1472	0	0
T24	474402	0	0	0
T26	136028	0	0	0
T38	174428	0	0	0
T46	103962	0	0	0
T55	112169	14	0	0
T70	205112	0	0	0
T80	0	46	0	0
T105	0	14	0	0
T111	73325	0	0	0
T112	258062	0	0	0
T113	255757	0	0	0
T114	248395	0	0	0
T152	0	21	0	0
T153	0	1	0	0
T154	0	36	0	0
T162	0	19	0	0
T312	0	3	0	0
T313	0	12	0	0
T314	0	14	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	5502	0	0
T23	233678	67	0	0
T24	474402	0	0	0
T26	136028	0	0	0
T46	103962	0	0	0
T55	112169	26	0	0
T66	0	90	0	0
T70	205112	0	0	0
T80	0	88	0	0
T105	0	10	0	0
T111	73325	0	0	0
T112	258062	0	0	0
T113	255757	0	0	0
T114	248395	0	0	0
T142	0	59	0	0
T152	0	193	0	0
T161	0	59	0	0
T162	0	103	0	0
T316	0	20	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	5967	0	0
T8	72516	0	0	0
T9	128779	0	0	0
T10	112409	0	0	0
T11	124602	0	0	0
T17	73388	53	0	0
T25	0	65	0	0
T29	129204	0	0	0
T51	50963	0	0	0
T55	0	91	0	0
T71	0	70	0	0
T93	207195	0	0	0
T94	48786	0	0	0
T95	46894	0	0	0
T102	0	29	0	0
T115	0	25	0	0
T141	0	77	0	0
T161	0	78	0	0
T185	0	74	0	0
T317	0	23	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	4662	0	0
T8	72516	0	0	0
T9	128779	0	0	0
T10	112409	0	0	0
T11	124602	0	0	0
T17	73388	77	0	0
T25	0	72	0	0
T29	129204	0	0	0
T51	50963	0	0	0
T55	0	82	0	0
T71	0	64	0	0
T93	207195	0	0	0
T94	48786	0	0	0
T95	46894	0	0	0
T102	0	41	0	0
T115	0	44	0	0
T141	0	71	0	0
T161	0	50	0	0
T185	0	53	0	0
T317	0	46	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	4895	0	0
T8	72516	0	0	0
T9	128779	0	0	0
T10	112409	0	0	0
T11	124602	0	0	0
T17	73388	68	0	0
T25	0	62	0	0
T29	129204	0	0	0
T51	50963	0	0	0
T55	0	87	0	0
T71	0	49	0	0
T93	207195	0	0	0
T94	48786	0	0	0
T95	46894	0	0	0
T102	0	21	0	0
T115	0	42	0	0
T141	0	72	0	0
T161	0	87	0	0
T185	0	69	0	0
T317	0	21	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	1695	0	0
T24	474402	0	0	0
T26	136028	0	0	0
T38	174428	0	0	0
T46	103962	0	0	0
T55	112169	20	0	0
T70	205112	0	0	0
T80	0	42	0	0
T105	0	13	0	0
T111	73325	0	0	0
T112	258062	0	0	0
T113	255757	0	0	0
T114	248395	0	0	0
T152	0	14	0	0
T153	0	4	0	0
T154	0	30	0	0
T162	0	27	0	0
T312	0	9	0	0
T313	0	10	0	0
T314	0	34	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	1612	0	0
T1	220897	11	0	0
T2	471338	0	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T55	0	23	0	0
T63	0	15	0	0
T87	0	7	0	0
T88	0	1	0	0
T89	0	11	0	0
T90	0	2	0	0
T152	0	15	0	0
T162	0	34	0	0
T318	0	1	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	1614	0	0
T1	220897	7	0	0
T2	471338	0	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T55	0	11	0	0
T63	0	7	0	0
T87	0	10	0	0
T88	0	5	0	0
T89	0	8	0	0
T90	0	12	0	0
T152	0	29	0	0
T162	0	38	0	0
T318	0	5	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	1540	0	0
T1	220897	11	0	0
T2	471338	0	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T55	0	11	0	0
T63	0	3	0	0
T87	0	14	0	0
T88	0	8	0	0
T89	0	8	0	0
T90	0	4	0	0
T102	0	4	0	0
T152	0	21	0	0
T162	0	34	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335139790	1555	0	0
T1	220897	3	0	0
T2	471338	0	0	0
T3	38859	0	0	0
T6	664447	0	0	0
T7	77976	0	0	0
T13	32711	0	0	0
T14	59272	0	0	0
T15	65573	0	0	0
T16	214953	0	0	0
T17	73388	0	0	0
T55	0	21	0	0
T84	0	7	0	0
T87	0	4	0	0
T88	0	5	0	0
T89	0	14	0	0
T90	0	6	0	0
T152	0	16	0	0
T162	0	32	0	0
T312	0	8	0	0