Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1935

1

T2

24

T4

13

T14

4

auto[1]

562

1

T2

4

T4

2

T8

7

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1844

1

T2

21

T4

7

T14

4

auto[1]

653

1

T2

7

T4

8

T8

11

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1896

1

T2

15

T4

10

T14

4

auto[1]

601

1

T2

13

T4

5

T8

7

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1892

1

T2

25

T4

13

T14

4

auto[1]

605

1

T2

3

T4

2

T8

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2253

1

T2

23

T4

15

T14

4

auto[1]

244

1

T2

5

T39

12

T235

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2248

1

T2

26

T4

15

T14

4

auto[1]

249

1

T2

2

T49

1

T81

9

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2286

1

T2

28

T4

15

T14

4

auto[1]

211

1

T49

1

T79

5

T39

6

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2239

1

T2

20

T4

15

T14

3

auto[1]

258

1

T2

8

T14

1

T49

8

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2258

1

T2

24

T4

15

T14

4

auto[1]

239

1

T2

4

T49

21

T79

5

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1974

1

T2

26

T4

2

T14

3

auto[1]

523

1

T2

2

T4

13

T14

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

752

1

T4

15

T8

6

T11

12

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

86

1

T2

3

T39

9

T239

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

72

1

T49

12

T81

5

T235

16

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T90

5

T322

18

T328

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

103

1

T2

4

T14

1

T237

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T178

3

T338

3

T339

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T2

4

T49

8

T81

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T235

2

T315

1

T331

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T226

3

T248

4

T340

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T178

3

T324

2

T341

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

24

1

T79

5

T342

2

T343

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

13

1

T39

6

T238

3

T315

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

21

1

T249

2

T340

2

T199

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T92

3

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T328

2

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

85

1

T81

2

T226

3

T237

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T2

2

T344

3

T163

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

30

1

T342

7

T340

4

T89

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T39

3

T242

2

T345

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

8

1

T329

5

T346

3

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T342

6

T199

3

T347

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

6

1

T240

1

T327

5

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

61

1

T348

8

T326

5

T349

20

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T350

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

2

1

T49

1

T338

1

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T242

2

T351

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

95

1

T49

9

T37

11

T93

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

88

1

T14

1

T249

2

T315

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

73

1

T11

6

T39

6

T103

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

135

1

T59

8

T81

2

T239

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

73

1

T4

2

T226

3

T316

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

23

1

T38

4

T330

4

T344

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T245

3

T106

2

T352

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

124

1

T2

4

T39

3

T240

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

53

1

T237

2

T253

1

T317

12

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T2

2

T4

5

T60

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T59

3

T315

3

T320

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

52

1

T36

7

T120

8

T38

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

27

1

T120

4

T343

2

T104

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

10

1

T353

1

T354

8

T355

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T8

1

T59

1

T60

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

131

1

T81

3

T235

8

T206

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

45

1

T79

5

T45

2

T103

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

68

1

T4

8

T8

5

T45

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T226

3

T340

5

T331

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T37

6

T45

6

T343

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

38

1

T81

5

T235

8

T245

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T356

1

T96

8

T324

10

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T37

1

T357

1

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T11

4

T235

2

T315

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

32

1

T2

4

T45

1

T206

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

19

1

T253

2

T178

3

T143

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T323

2

T110

2

T294

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T2

3

T11

2

T49

12

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T143

2

T204

2

T247

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T51

2

T37

2

T39

9

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T36

1

T247

1

T358

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded