Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1009

1

T28

4

T62

8

T73

13

auto[1]

1033

1

T28

16

T62

12

T73

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

500

1

T28

4

T62

5

T73

6

from_0to1

514

1

T28

3

T62

5

T73

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T28

7

T62

9

T73

15

auto[1]

1012

1

T28

13

T62

11

T73

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

988

1

T28

8

T62

13

T73

10

auto[1]

1054

1

T28

12

T62

7

T73

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T62

1

T73

1

T74

1

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T73

2

T57

2

T373

2

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T74

1

T43

1

T374

2

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T28

1

T62

1

T73

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T73

1

T74

1

T43

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T62

1

T73

1

T43

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T62

1

T74

2

T374

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T62

1

T43

1

T374

2

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T62

1

T43

2

T373

2

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T28

1

T62

1

T43

2

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T28

1

T62

1

T73

2

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T28

1

T74

1

T43

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T28

1

T73

1

T74

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T73

1

T74

1

T43

1

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T28

1

T62

2

T73

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T28

1

T43

1

T45

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1007

1

T28

11

T62

8

T73

9

auto[1]

1035

1

T28

9

T62

12

T73

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

489

1

T28

5

T62

5

T73

6

from_0to1

485

1

T28

4

T62

6

T73

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T28

13

T62

10

T73

8

auto[1]

1010

1

T28

7

T62

10

T73

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1020

1

T28

8

T62

11

T73

11

auto[1]

1022

1

T28

12

T62

9

T73

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T62

1

T43

1

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T28

2

T73

1

T74

2

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T62

1

T73

1

T373

1

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T73

1

T43

1

T374

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T62

1

T73

1

T43

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T28

1

T74

1

T43

1

auto[0]

from_0to1

auto[1]

auto[0]

53

1

T62

1

T74

1

T45

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T28

1

T73

1

T43

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T28

1

T73

1

T374

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T28

1

T73

1

T74

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T28

1

T62

1

T73

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T62

2

T43

1

T225

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T62

2

T73

1

T74

2

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T28

1

T74

1

T43

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T73

2

T374

1

T45

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T28

1

T62

2

T73

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1005

1

T28

8

T62

8

T73

8

auto[1]

1037

1

T28

12

T62

12

T73

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

479

1

T28

4

T62

4

T73

6

from_0to1

485

1

T28

3

T62

4

T73

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T28

10

T62

13

T73

13

auto[1]

989

1

T28

10

T62

7

T73

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T28

9

T62

9

T73

12

auto[1]

1021

1

T28

11

T62

11

T73

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T73

2

T74

2

T374

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T62

2

T43

1

T374

2

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T374

1

T57

1

T45

2

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T28

1

T62

1

T43

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T28

1

T74

1

T225

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T62

1

T73

2

T57

2

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T73

1

T74

1

T270

2

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T62

1

T73

1

T43

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T73

1

T74

1

T43

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T28

2

T73

2

T43

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T28

1

T62

1

T73

1

auto[1]

from_1to0

auto[1]

auto[1]

49

1

T74

1

T373

1

T45

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T62

1

T43

1

T374

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T74

1

T43

1

T374

3

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T62

1

T73

3

T74

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T28

2

T43

1

T373

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1023

1

T28

10

T62

13

T73

11

auto[1]

1019

1

T28

10

T62

7

T73

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

493

1

T28

5

T62

4

T73

5

from_0to1

490

1

T28

5

T62

4

T73

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016

1

T28

10

T62

8

T73

8

auto[1]

1026

1

T28

10

T62

12

T73

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1047

1

T28

15

T62

12

T73

10

auto[1]

995

1

T28

5

T62

8

T73

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T28

1

T62

1

T43

2

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T62

2

T43

1

T57

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T43

1

T373

1

T45

3

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T73

4

T74

1

T374

2

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T28

2

T62

1

T74

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T43

1

T374

1

T45

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T28

1

T62

2

T73

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T73

1

T74

1

T43

2

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T28

1

T62

1

T73

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T28

2

T74

1

T45

1

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T28

1

T74

1

T373

2

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T74

1

T374

1

T57

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T73

1

T74

1

T45

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T73

1

T74

1

T43

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T28

2

T43

1

T373

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T62

1

T57

1

T373

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

976

1

T28

13

T62

8

T73

8

auto[1]

1066

1

T28

7

T62

12

T73

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

490

1

T28

3

T62

4

T73

4

from_0to1

483

1

T28

3

T62

3

T73

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1007

1

T28

10

T62

8

T73

7

auto[1]

1035

1

T28

10

T62

12

T73

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1007

1

T28

3

T62

10

T73

7

auto[1]

1035

1

T28

17

T62

10

T73

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T73

1

T374

2

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T43

1

T57

3

T373

2

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T62

1

T43

1

T374

2

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T73

1

T74

2

T374

1

auto[0]

from_0to1

auto[0]

auto[0]

46

1

T74

1

T43

1

T57

2

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T28

1

T73

1

T43

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T373

1

T45

2

T225

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T28

1

T62

2

T73

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T28

1

T62

2

T73

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T62

1

T74

1

T45

2

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T28

1

T57

1

T45

2

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T28

1

T73

1

T43

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T62

1

T73

1

T374

3

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T28

1

T74

1

T45

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T74

1

T43

1

T374

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T43

2

T374

2

T57

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

994

1

T28

10

T62

13

T73

4

auto[1]

1048

1

T28

10

T62

7

T73

16

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

514

1

T28

5

T62

2

T73

6

from_0to1

513

1

T28

5

T62

3

T73

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1020

1

T28

6

T62

11

T73

10

auto[1]

1022

1

T28

14

T62

9

T73

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1039

1

T28

7

T62

13

T73

8

auto[1]

1003

1

T28

13

T62

7

T73

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T43

1

T374

1

T45

2

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T73

1

T57

1

T373

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T28

1

T62

2

T74

3

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T28

1

T73

1

T374

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T62

1

T373

1

T45

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T28

1

T374

1

T373

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T28

1

T43

1

T374

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T62

1

T74

1

T43

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T74

1

T43

1

T374

2

auto[1]

from_1to0

auto[0]

auto[1]

85

1

T73

3

T57

1

T373

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T28

2

T73

1

T43

1

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T28

1

T74

2

T45

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T62

1

T73

1

T74

3

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T28

2

T74

1

T374

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T73

3

T74

2

T374

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T28

1

T73

1

T43

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1012

1

T28

11

T62

11

T73

7

auto[1]

1030

1

T28

9

T62

9

T73

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

496

1

T28

4

T62

7

T73

6

from_0to1

500

1

T28

5

T62

6

T73

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T28

11

T62

9

T73

6

auto[1]

1012

1

T28

9

T62

11

T73

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T28

11

T62

8

T73

11

auto[1]

991

1

T28

9

T62

12

T73

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T43

2

T374

1

T45

5

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T62

1

T74

1

T57

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T28

2

T62

1

T73

2

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T62

2

T73

1

T74

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T28

2

T62

2

T43

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T73

1

T74

1

T45

4

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T62

1

T73

1

T374

2

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T28

1

T57

2

T45

2

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T62

1

T73

1

T74

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T62

1

T73

1

T374

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T28

1

T43

1

T373

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T28

1

T62

1

T73

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T28

1

T73

1

T43

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T28

1

T62

1

T74

2

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T62

1

T73

3

T374

1

auto[1]

from_0to1

auto[1]

auto[1]

45

1

T62

1

T73

1

T43

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1003

1

T28

15

T62

11

T73

4

auto[1]

1039

1

T28

5

T62

9

T73

16

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

476

1

T28

5

T62

3

T73

6

from_0to1

483

1

T28

6

T62

4

T73

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T28

11

T62

6

T73

7

auto[1]

1010

1

T28

9

T62

14

T73

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T28

11

T62

10

T73

11

auto[1]

1013

1

T28

9

T62

10

T73

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

50

1

T28

1

T73

1

T373

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T28

2

T43

1

T57

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T62

1

T74

1

T57

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T28

1

T62

1

T74

1

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T28

3

T62

1

T43

1

auto[0]

from_0to1

auto[0]

auto[1]

77

1

T28

1

T73

1

T43

1

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T374

1

T373

1

T225

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T62

1

T43

1

T374

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T73

2

T74

1

T43

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T62

1

T74

1

T57

2

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T73

2

T43

1

T374

1

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T28

1

T73

1

T43

1

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T28

1

T73

1

T45

3

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T62

1

T74

3

T374

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T28

1

T62

1

T73

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T73

3

T43

1

T57

1