Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151282	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

116530

1

T5

5

T6

4

T7

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	135621	1			T5	8		T6	3		T7	35
values[0x0]	65458	1			T5	4		T6	2		T1	6
values[0x1]	66733	1			T5	5		T6	5		T1	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	122614	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145198

1

T5

11

T6

6

T7

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1090	1			T4	2		T14	10		T35	1
valid_sources[0x01]	994	1			T6	1		T4	3		T14	1
valid_sources[0x02]	901	1			T6	1		T4	1		T14	3
valid_sources[0x03]	1141	1			T2	7		T4	3		T14	2
valid_sources[0x04]	1604	1			T2	1		T4	13		T9	1
valid_sources[0x05]	923	1			T2	21		T14	5		T70	2
valid_sources[0x06]	875	1			T4	1		T9	2		T35	3
valid_sources[0x07]	839	1			T4	4		T14	4		T9	3
valid_sources[0x08]	997	1			T14	4		T61	1		T9	1
valid_sources[0x09]	918	1			T2	1		T14	5		T51	7
valid_sources[0x0a]	1415	1			T7	1		T14	6		T50	1
valid_sources[0x0b]	1553	1			T7	1		T4	1		T14	5
valid_sources[0x0c]	936	1			T2	3		T14	1		T17	2
valid_sources[0x0d]	840	1			T2	13		T4	6		T14	4
valid_sources[0x0e]	881	1			T14	3		T50	7		T26	1
valid_sources[0x0f]	889	1			T2	11		T14	5		T15	1
valid_sources[0x10]	823	1			T4	3		T14	4		T27	2
valid_sources[0x11]	1209	1			T4	2		T50	11		T35	10
valid_sources[0x12]	814	1			T2	3		T4	1		T14	3
valid_sources[0x13]	1332	1			T4	4		T14	1		T17	1
valid_sources[0x14]	830	1			T4	9		T14	8		T15	1
valid_sources[0x15]	886	1			T4	1		T14	1		T51	4
valid_sources[0x16]	951	1			T7	1		T2	25		T4	1
valid_sources[0x17]	835	1			T4	1		T28	6		T70	1
valid_sources[0x18]	861	1			T14	1		T15	1		T17	2
valid_sources[0x19]	882	1			T14	2		T15	1		T50	3
valid_sources[0x1a]	1914	1			T2	12		T4	5		T14	2
valid_sources[0x1b]	960	1			T2	1		T4	1		T14	2
valid_sources[0x1c]	835	1			T2	5		T4	3		T14	2
valid_sources[0x1d]	818	1			T4	2		T9	1		T78	1
valid_sources[0x1e]	2072	1			T14	3		T15	1		T9	1
valid_sources[0x1f]	988	1			T2	11		T4	2		T14	1
valid_sources[0x20]	1074	1			T14	7		T26	1		T9	1
valid_sources[0x21]	1013	1			T2	3		T14	3		T50	3
valid_sources[0x22]	1372	1			T15	2		T50	3		T26	2
valid_sources[0x23]	978	1			T6	1		T2	4		T14	4
valid_sources[0x24]	742	1			T2	2		T51	2		T111	1
valid_sources[0x25]	910	1			T2	3		T4	10		T14	1
valid_sources[0x26]	821	1			T2	2		T4	3		T14	4
valid_sources[0x27]	1027	1			T4	1		T14	8		T9	2
valid_sources[0x28]	927	1			T14	1		T15	1		T17	5
valid_sources[0x29]	1063	1			T2	13		T4	1		T14	2
valid_sources[0x2a]	892	1			T2	27		T75	1		T35	1
valid_sources[0x2b]	817	1			T2	4		T14	14		T9	1
valid_sources[0x2c]	732	1			T2	4		T4	4		T14	3
valid_sources[0x2d]	863	1			T4	6		T14	2		T61	1
valid_sources[0x2e]	1245	1			T7	1		T2	1		T14	4
valid_sources[0x2f]	810	1			T4	1		T14	2		T17	2
valid_sources[0x30]	928	1			T2	3		T14	3		T28	13
valid_sources[0x31]	1067	1			T6	2		T14	4		T50	1
valid_sources[0x32]	879	1			T6	1		T4	1		T14	4
valid_sources[0x33]	852	1			T4	2		T17	1		T50	1
valid_sources[0x34]	920	1			T4	2		T14	1		T15	1
valid_sources[0x35]	1056	1			T9	1		T78	5		T60	3
valid_sources[0x36]	2075	1			T2	2		T14	3		T10	3
valid_sources[0x37]	940	1			T2	18		T4	1		T14	6
valid_sources[0x38]	882	1			T2	13		T4	4		T14	1
valid_sources[0x39]	878	1			T6	1		T4	3		T14	6
valid_sources[0x3a]	1694	1			T6	1		T14	5		T17	1
valid_sources[0x3b]	1003	1			T7	1		T4	3		T14	3
valid_sources[0x3c]	874	1			T2	8		T14	2		T26	1
valid_sources[0x3d]	849	1			T4	7		T14	6		T35	4
valid_sources[0x3e]	885	1			T2	2		T4	1		T14	5
valid_sources[0x3f]	1058	1			T4	4		T14	1		T50	9
valid_sources[0x40]	1106	1			T2	5		T4	4		T14	8
valid_sources[0x41]	1005	1			T2	6		T14	1		T9	1
valid_sources[0x42]	925	1			T14	7		T9	1		T35	6
valid_sources[0x43]	764	1			T4	1		T14	2		T28	4
valid_sources[0x44]	1103	1			T7	2		T4	4		T14	11
valid_sources[0x45]	2197	1			T4	4		T14	5		T26	1
valid_sources[0x46]	911	1			T2	9		T14	4		T17	1
valid_sources[0x47]	947	1			T2	11		T14	1		T15	1
valid_sources[0x48]	1103	1			T7	1		T2	2		T14	1
valid_sources[0x49]	883	1			T4	2		T14	5		T50	28
valid_sources[0x4a]	911	1			T2	12		T14	2		T9	1
valid_sources[0x4b]	856	1			T14	4		T50	1		T51	1
valid_sources[0x4c]	929	1			T4	6		T14	1		T9	2
valid_sources[0x4d]	880	1			T4	4		T17	1		T9	1
valid_sources[0x4e]	939	1			T14	5		T50	1		T78	1
valid_sources[0x4f]	910	1			T2	10		T4	4		T14	6
valid_sources[0x50]	831	1			T4	5		T14	6		T50	5
valid_sources[0x51]	1290	1			T2	13		T4	6		T14	2
valid_sources[0x52]	831	1			T111	1		T44	2		T78	1
valid_sources[0x53]	1654	1			T4	1		T14	3		T9	1
valid_sources[0x54]	781	1			T14	6		T9	1		T13	4
valid_sources[0x55]	954	1			T4	4		T14	10		T26	1
valid_sources[0x56]	1124	1			T2	18		T4	1		T14	1
valid_sources[0x57]	916	1			T4	3		T14	3		T15	1
valid_sources[0x58]	822	1			T50	1		T35	1		T51	8
valid_sources[0x59]	970	1			T2	7		T4	4		T14	3
valid_sources[0x5a]	1253	1			T14	6		T9	1		T35	6
valid_sources[0x5b]	837	1			T2	18		T4	11		T14	2
valid_sources[0x5c]	1080	1			T2	17		T4	6		T14	2
valid_sources[0x5d]	904	1			T4	1		T50	3		T51	2
valid_sources[0x5e]	814	1			T4	8		T14	3		T15	1
valid_sources[0x5f]	911	1			T14	9		T50	1		T78	4
valid_sources[0x60]	1047	1			T2	42		T4	8		T14	8
valid_sources[0x61]	971	1			T14	5		T70	1		T35	3
valid_sources[0x62]	1197	1			T2	6		T4	2		T14	3
valid_sources[0x63]	904	1			T4	1		T14	4		T15	1
valid_sources[0x64]	936	1			T2	6		T14	5		T26	1
valid_sources[0x65]	926	1			T7	1		T4	1		T14	2
valid_sources[0x66]	956	1			T2	3		T4	1		T14	1
valid_sources[0x67]	993	1			T7	1		T4	6		T14	1
valid_sources[0x68]	831	1			T2	3		T4	5		T14	2
valid_sources[0x69]	858	1			T4	3		T14	5		T15	1
valid_sources[0x6a]	776	1			T4	2		T14	2		T26	1
valid_sources[0x6b]	1517	1			T7	2		T2	4		T14	3
valid_sources[0x6c]	1056	1			T4	1		T14	4		T35	4
valid_sources[0x6d]	1130	1			T7	1		T4	5		T14	7
valid_sources[0x6e]	906	1			T14	5		T78	4		T60	3
valid_sources[0x6f]	846	1			T7	1		T2	5		T4	2
valid_sources[0x70]	1050	1			T4	3		T14	1		T50	2
valid_sources[0x71]	1250	1			T4	2		T14	1		T70	2
valid_sources[0x72]	1098	1			T14	1		T26	1		T9	1
valid_sources[0x73]	912	1			T2	15		T4	3		T14	2
valid_sources[0x74]	1314	1			T2	11		T14	1		T9	1
valid_sources[0x75]	928	1			T2	4		T14	4		T9	1
valid_sources[0x76]	1430	1			T4	2		T14	4		T15	1
valid_sources[0x77]	859	1			T7	1		T14	8		T17	1
valid_sources[0x78]	1526	1			T4	4		T26	2		T27	1
valid_sources[0x79]	739	1			T14	1		T51	12		T78	3
valid_sources[0x7a]	936	1			T2	5		T4	8		T14	7
valid_sources[0x7b]	1650	1			T4	3		T14	5		T26	1
valid_sources[0x7c]	976	1			T14	2		T15	1		T35	4
valid_sources[0x7d]	1954	1			T14	4		T15	1		T29	1
valid_sources[0x7e]	943	1			T7	1		T4	1		T13	2
valid_sources[0x7f]	2231	1			T14	1		T50	5		T9	1
valid_sources[0x80]	1146	1			T2	4		T4	3		T14	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61884

1

T5

3

T6

2

T7

17

values[0x0]

all_enables

biggest_size

31887

1

T5

2

T1

3

T2

137

values[0x1]

all_enables

biggest_size

22759

1

T6

2

T2

74

T4

36