Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T7,T1
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T1
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T30,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T5,T30,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T30,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T30,T31
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T30,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T30,T31
0	1	Covered	T57,T107,T108
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T30,T31
0	1	Covered	T5,T30,T31
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T30,T31
1	-	Covered	T5,T30,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T30,T31
DetectSt	168	Covered	T5,T30,T31
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T5,T30,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T30,T31
DebounceSt->IdleSt	163	Covered	T31,T52,T53
DetectSt->IdleSt	186	Covered	T57,T107,T108
DetectSt->StableSt	191	Covered	T5,T30,T31
IdleSt->DebounceSt	148	Covered	T5,T30,T31
StableSt->IdleSt	206	Covered	T5,T30,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T30,T31
0	1	Covered	T5,T30,T31
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T30,T31
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T30,T31
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T30,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T52,T53
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T30,T31
DetectSt	-	-	-	-	1	-	-	Covered	T57,T107,T108
DetectSt	-	-	-	-	0	1	-	Covered	T5,T30,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T30,T31
StableSt	-	-	-	-	-	-	0	Covered	T5,T30,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	292	0	0
CntIncr_A	9133666	176827	0	0
CntNoWrap_A	9133666	8487147	0	0
DetectStDropOut_A	9133666	3	0	0
DetectedOut_A	9133666	866	0	0
DetectedPulseOut_A	9133666	128	0	0
DisabledIdleSt_A	9133666	8303581	0	0
DisabledNoDetection_A	9133666	8305863	0	0
EnterDebounceSt_A	9133666	168	0	0
EnterDetectSt_A	9133666	131	0	0
EnterStableSt_A	9133666	128	0	0
PulseIsPulse_A	9133666	128	0	0
StayInStableSt	9133666	738	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9133666	6893	0	0
gen_low_level_sva.LowLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	128	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	292	0	0
T1	564982	0	0	0
T2	21127	0	0	0
T3	825	0	0	0
T4	25465	0	0	0
T5	738	2	0	0
T6	435	0	0	0
T7	437	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T30	0	4	0	0
T31	0	4	0	0
T43	0	6	0	0
T52	0	3	0	0
T53	0	5	0	0
T54	0	2	0	0
T55	0	6	0	0
T56	0	4	0	0
T57	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	176827	0	0
T1	564982	0	0	0
T2	21127	0	0	0
T3	825	0	0	0
T4	25465	0	0	0
T5	738	48	0	0
T6	435	0	0	0
T7	437	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T30	0	101	0	0
T31	0	129	0	0
T43	0	42	0	0
T52	0	165	0	0
T53	0	172	0	0
T54	0	7854	0	0
T55	0	262	0	0
T56	0	147	0	0
T57	0	508	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8487147	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	335	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	3	0	0
T57	10924	1	0	0
T82	1782	0	0	0
T107	0	1	0	0
T108	0	1	0	0
T112	4404	0	0	0
T113	66142	0	0	0
T114	824	0	0	0
T115	422	0	0	0
T116	162493	0	0	0
T117	796	0	0	0
T118	436	0	0	0
T119	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	866	0	0
T1	564982	0	0	0
T2	21127	0	0	0
T3	825	0	0	0
T4	25465	0	0	0
T5	738	5	0	0
T6	435	0	0	0
T7	437	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T30	0	16	0	0
T31	0	2	0	0
T43	0	11	0	0
T52	0	12	0	0
T53	0	14	0	0
T54	0	6	0	0
T55	0	27	0	0
T56	0	20	0	0
T57	0	51	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	128	0	0
T1	564982	0	0	0
T2	21127	0	0	0
T3	825	0	0	0
T4	25465	0	0	0
T5	738	1	0	0
T6	435	0	0	0
T7	437	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T43	0	3	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	3	0	0
T56	0	2	0	0
T57	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8303581	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	236	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8305863	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	237	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	168	0	0
T1	564982	0	0	0
T2	21127	0	0	0
T3	825	0	0	0
T4	25465	0	0	0
T5	738	1	0	0
T6	435	0	0	0
T7	437	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T30	0	2	0	0
T31	0	3	0	0
T43	0	3	0	0
T52	0	2	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	3	0	0
T56	0	2	0	0
T57	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	131	0	0
T1	564982	0	0	0
T2	21127	0	0	0
T3	825	0	0	0
T4	25465	0	0	0
T5	738	1	0	0
T6	435	0	0	0
T7	437	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T43	0	3	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	3	0	0
T56	0	2	0	0
T57	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	128	0	0
T1	564982	0	0	0
T2	21127	0	0	0
T3	825	0	0	0
T4	25465	0	0	0
T5	738	1	0	0
T6	435	0	0	0
T7	437	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T43	0	3	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	3	0	0
T56	0	2	0	0
T57	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	128	0	0
T1	564982	0	0	0
T2	21127	0	0	0
T3	825	0	0	0
T4	25465	0	0	0
T5	738	1	0	0
T6	435	0	0	0
T7	437	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T43	0	3	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	3	0	0
T56	0	2	0	0
T57	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	738	0	0
T1	564982	0	0	0
T2	21127	0	0	0
T3	825	0	0	0
T4	25465	0	0	0
T5	738	4	0	0
T6	435	0	0	0
T7	437	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T30	0	14	0	0
T31	0	1	0	0
T43	0	8	0	0
T52	0	11	0	0
T53	0	12	0	0
T54	0	5	0	0
T55	0	24	0	0
T56	0	18	0	0
T57	0	45	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	6893	0	0
T1	564982	7	0	0
T2	21127	22	0	0
T3	825	4	0	0
T4	25465	16	0	0
T5	738	3	0	0
T6	435	0	0	0
T7	437	5	0	0
T14	8467	31	0	0
T15	494	9	0	0
T16	5016	29	0	0
T17	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	128	0	0
T1	564982	0	0	0
T2	21127	0	0	0
T3	825	0	0	0
T4	25465	0	0	0
T5	738	1	0	0
T6	435	0	0	0
T7	437	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T43	0	3	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	3	0	0
T56	0	2	0	0
T57	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T7,T1
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T1
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T3,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T3,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T3,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T25
1	0	Covered	T5,T7,T1
1	1	Covered	T1,T3,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T25
0	1	Covered	T96,T97,T98
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T25
0	1	Unreachable
1	0	Covered	T1,T3,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T25
DetectSt	168	Covered	T1,T3,T25
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T3,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T25
DebounceSt->IdleSt	163	Covered	T64,T82,T122
DetectSt->IdleSt	186	Covered	T96,T97,T98
DetectSt->StableSt	191	Covered	T1,T3,T25
IdleSt->DebounceSt	148	Covered	T1,T3,T25
StableSt->IdleSt	206	Covered	T1,T3,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T25
0	1	Covered	T1,T3,T25
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T25
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T25
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T64,T82,T122
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T25
DetectSt	-	-	-	-	1	-	-	Covered	T96,T97,T98
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T25
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	172	0	0
CntIncr_A	9133666	446165	0	0
CntNoWrap_A	9133666	8487267	0	0
DetectStDropOut_A	9133666	13	0	0
DetectedOut_A	9133666	122256	0	0
DetectedPulseOut_A	9133666	53	0	0
DisabledIdleSt_A	9133666	6304997	0	0
DisabledNoDetection_A	9133666	6307337	0	0
EnterDebounceSt_A	9133666	108	0	0
EnterDetectSt_A	9133666	66	0	0
EnterStableSt_A	9133666	53	0	0
PulseIsPulse_A	9133666	53	0	0
StayInStableSt	9133666	122203	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9133666	6893	0	0
gen_low_level_sva.LowLevelEvent_A	9133666	8489780	0	0
gen_sticky_sva.StableStDropOut_A	9133666	1294829	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	172	0	0
T1	564982	2	0	0
T2	21127	0	0	0
T3	825	2	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	2	0	0
T43	0	2	0	0
T64	0	9	0	0
T82	0	3	0	0
T83	0	2	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	446165	0	0
T1	564982	99	0	0
T2	21127	0	0	0
T3	825	21	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	62	0	0
T43	0	93	0	0
T64	0	873	0	0
T82	0	300	0	0
T83	0	52	0	0
T84	0	95	0	0
T85	0	73	0	0
T86	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8487267	0	0
T1	564982	564579	0	0
T2	21127	20688	0	0
T3	825	422	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	13	0	0
T96	27666	2	0	0
T97	0	1	0	0
T98	0	1	0	0
T105	30379	0	0	0
T106	11392	0	0	0
T126	0	1	0	0
T127	0	5	0	0
T128	0	3	0	0
T129	503	0	0	0
T130	554	0	0	0
T131	502	0	0	0
T132	502	0	0	0
T133	492	0	0	0
T134	33114	0	0	0
T135	496	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	122256	0	0
T1	564982	874	0	0
T2	21127	0	0	0
T3	825	52	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	497	0	0
T43	0	460	0	0
T83	0	18	0	0
T84	0	401	0	0
T85	0	198	0	0
T86	0	198	0	0
T93	0	176	0	0
T121	0	209	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	53	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	1	0	0
T43	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0
T121	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	6304997	0	0
T1	564982	161322	0	0
T2	21127	20688	0	0
T3	825	219	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	6307337	0	0
T1	564982	161323	0	0
T2	21127	20694	0	0
T3	825	220	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	108	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	1	0	0
T43	0	1	0	0
T64	0	9	0	0
T82	0	3	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	66	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	1	0	0
T43	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0
T121	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	53	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	1	0	0
T43	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0
T121	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	53	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	1	0	0
T43	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0
T121	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	122203	0	0
T1	564982	873	0	0
T2	21127	0	0	0
T3	825	51	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	496	0	0
T43	0	459	0	0
T83	0	17	0	0
T84	0	400	0	0
T85	0	197	0	0
T86	0	197	0	0
T93	0	175	0	0
T121	0	207	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	6893	0	0
T1	564982	7	0	0
T2	21127	22	0	0
T3	825	4	0	0
T4	25465	16	0	0
T5	738	3	0	0
T6	435	0	0	0
T7	437	5	0	0
T14	8467	31	0	0
T15	494	9	0	0
T16	5016	29	0	0
T17	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	1294829	0	0
T1	564982	402277	0	0
T2	21127	0	0	0
T3	825	111	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	96	0	0
T43	0	40	0	0
T83	0	50	0	0
T84	0	43938	0	0
T85	0	103	0	0
T86	0	505	0	0
T93	0	168	0	0
T121	0	835	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T7,T1,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T7,T1,T3
1	1	Covered	T7,T1,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T3,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T3,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T3,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T25
1	0	Covered	T7,T1,T3
1	1	Covered	T1,T3,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T64
0	1	Covered	T25,T64,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T64
0	1	Unreachable
1	0	Covered	T1,T3,T64

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T25
DetectSt	168	Covered	T1,T3,T25
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T3,T64

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T25
DebounceSt->IdleSt	163	Covered	T25,T64,T85
DetectSt->IdleSt	186	Covered	T25,T64,T95
DetectSt->StableSt	191	Covered	T1,T3,T64
IdleSt->DebounceSt	148	Covered	T1,T3,T25
StableSt->IdleSt	206	Covered	T1,T3,T64

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T25
0	1	Covered	T1,T3,T25
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T25
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T25
IdleSt	0	-	-	-	-	-	-	Covered	T7,T1,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T25,T64,T85
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T25
DetectSt	-	-	-	-	1	-	-	Covered	T25,T64,T95
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T64
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T64
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T64
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	170	0	0
CntIncr_A	9133666	208587	0	0
CntNoWrap_A	9133666	8487269	0	0
DetectStDropOut_A	9133666	15	0	0
DetectedOut_A	9133666	850249	0	0
DetectedPulseOut_A	9133666	54	0	0
DisabledIdleSt_A	9133666	6304997	0	0
DisabledNoDetection_A	9133666	6307337	0	0
EnterDebounceSt_A	9133666	103	0	0
EnterDetectSt_A	9133666	69	0	0
EnterStableSt_A	9133666	54	0	0
PulseIsPulse_A	9133666	54	0	0
StayInStableSt	9133666	850195	0	0
gen_high_level_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_sticky_sva.StableStDropOut_A	9133666	1082276	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	170	0	0
T1	564982	2	0	0
T2	21127	0	0	0
T3	825	2	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	9	0	0
T43	0	2	0	0
T64	0	12	0	0
T82	0	2	0	0
T83	0	2	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	208587	0	0
T1	564982	90	0	0
T2	21127	0	0	0
T3	825	27	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	170	0	0
T43	0	24	0	0
T64	0	357	0	0
T82	0	10	0	0
T83	0	56	0	0
T84	0	15	0	0
T85	0	158	0	0
T86	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8487269	0	0
T1	564982	564579	0	0
T2	21127	20688	0	0
T3	825	422	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	15	0	0
T25	1119	4	0	0
T31	652	0	0	0
T59	26940	0	0	0
T60	20896	0	0	0
T64	0	4	0	0
T67	497	0	0	0
T71	522	0	0	0
T95	0	2	0	0
T136	0	4	0	0
T137	0	1	0	0
T138	450	0	0	0
T139	405	0	0	0
T140	1013	0	0	0
T141	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	850249	0	0
T1	564982	674	0	0
T2	21127	0	0	0
T3	825	64	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T43	0	67	0	0
T64	0	103	0	0
T82	0	41	0	0
T83	0	40	0	0
T84	0	94	0	0
T86	0	310	0	0
T123	0	433	0	0
T124	0	145	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	54	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T43	0	1	0	0
T64	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T86	0	1	0	0
T123	0	1	0	0
T124	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	6304997	0	0
T1	564982	161322	0	0
T2	21127	20688	0	0
T3	825	219	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	6307337	0	0
T1	564982	161323	0	0
T2	21127	20694	0	0
T3	825	220	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	103	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	5	0	0
T43	0	1	0	0
T64	0	7	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T86	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	69	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	4	0	0
T43	0	1	0	0
T64	0	5	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T86	0	1	0	0
T123	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	54	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T43	0	1	0	0
T64	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T86	0	1	0	0
T123	0	1	0	0
T124	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	54	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T43	0	1	0	0
T64	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T86	0	1	0	0
T123	0	1	0	0
T124	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	850195	0	0
T1	564982	673	0	0
T2	21127	0	0	0
T3	825	63	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T43	0	66	0	0
T64	0	102	0	0
T82	0	40	0	0
T83	0	39	0	0
T84	0	93	0	0
T86	0	309	0	0
T123	0	432	0	0
T124	0	143	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	1082276	0	0
T1	564982	402476	0	0
T2	21127	0	0	0
T3	825	98	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T43	0	506	0	0
T64	0	501	0	0
T82	0	297	0	0
T83	0	32	0	0
T84	0	44327	0	0
T86	0	385	0	0
T123	0	98	0	0
T124	0	1015	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T7,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T3,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T3,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T3,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T25
1	0	Covered	T7,T1,T2
1	1	Covered	T1,T3,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T25
0	1	Covered	T25,T43,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T25
0	1	Unreachable
1	0	Covered	T1,T3,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T25
DetectSt	168	Covered	T1,T3,T25
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T3,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T25
DebounceSt->IdleSt	163	Covered	T25,T84,T85
DetectSt->IdleSt	186	Covered	T25,T43,T93
DetectSt->StableSt	191	Covered	T1,T3,T25
IdleSt->DebounceSt	148	Covered	T1,T3,T25
StableSt->IdleSt	206	Covered	T1,T3,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T25
0	1	Covered	T1,T3,T25
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T25
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T25
IdleSt	0	-	-	-	-	-	-	Covered	T7,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T25,T84,T85
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T25
DetectSt	-	-	-	-	1	-	-	Covered	T25,T43,T93
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T25
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	187	0	0
CntIncr_A	9133666	201773	0	0
CntNoWrap_A	9133666	8487252	0	0
DetectStDropOut_A	9133666	14	0	0
DetectedOut_A	9133666	432738	0	0
DetectedPulseOut_A	9133666	41	0	0
DisabledIdleSt_A	9133666	6304997	0	0
DisabledNoDetection_A	9133666	6307337	0	0
EnterDebounceSt_A	9133666	134	0	0
EnterDetectSt_A	9133666	55	0	0
EnterStableSt_A	9133666	41	0	0
PulseIsPulse_A	9133666	41	0	0
StayInStableSt	9133666	432697	0	0
gen_high_event_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_high_level_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_sticky_sva.StableStDropOut_A	9133666	508783	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	187	0	0
T1	564982	2	0	0
T2	21127	0	0	0
T3	825	2	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	5	0	0
T43	0	6	0	0
T64	0	6	0	0
T82	0	2	0	0
T83	0	2	0	0
T84	0	4	0	0
T85	0	2	0	0
T86	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	201773	0	0
T1	564982	64319	0	0
T2	21127	0	0	0
T3	825	50	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	87	0	0
T43	0	201	0	0
T64	0	246	0	0
T82	0	28	0	0
T83	0	43	0	0
T84	0	44408	0	0
T85	0	58	0	0
T86	0	384	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8487252	0	0
T1	564982	564579	0	0
T2	21127	20688	0	0
T3	825	422	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	14	0	0
T25	1119	1	0	0
T31	652	0	0	0
T43	0	3	0	0
T59	26940	0	0	0
T60	20896	0	0	0
T67	497	0	0	0
T71	522	0	0	0
T93	0	1	0	0
T125	0	1	0	0
T138	450	0	0	0
T139	405	0	0	0
T140	1013	0	0	0
T141	404	0	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	432738	0	0
T1	564982	338875	0	0
T2	21127	0	0	0
T3	825	112	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	63	0	0
T64	0	744	0	0
T82	0	136	0	0
T83	0	10	0	0
T93	0	64	0	0
T122	0	69	0	0
T123	0	192	0	0
T125	0	34	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	41	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	1	0	0
T64	0	3	0	0
T82	0	1	0	0
T83	0	1	0	0
T93	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T125	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	6304997	0	0
T1	564982	161322	0	0
T2	21127	20688	0	0
T3	825	219	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	6307337	0	0
T1	564982	161323	0	0
T2	21127	20694	0	0
T3	825	220	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	134	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	3	0	0
T43	0	3	0	0
T64	0	3	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	4	0	0
T85	0	2	0	0
T86	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	55	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	2	0	0
T43	0	3	0	0
T64	0	3	0	0
T82	0	1	0	0
T83	0	1	0	0
T93	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	41	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	1	0	0
T64	0	3	0	0
T82	0	1	0	0
T83	0	1	0	0
T93	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T125	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	41	0	0
T1	564982	1	0	0
T2	21127	0	0	0
T3	825	1	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	1	0	0
T64	0	3	0	0
T82	0	1	0	0
T83	0	1	0	0
T93	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T125	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	432697	0	0
T1	564982	338874	0	0
T2	21127	0	0	0
T3	825	111	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	62	0	0
T64	0	741	0	0
T82	0	135	0	0
T83	0	9	0	0
T93	0	63	0	0
T122	0	68	0	0
T123	0	191	0	0
T125	0	33	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	508783	0	0
T1	564982	59	0	0
T2	21127	0	0	0
T3	825	36	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T25	0	321	0	0
T64	0	997	0	0
T82	0	194	0	0
T83	0	82	0	0
T93	0	144	0	0
T122	0	132	0	0
T123	0	376	0	0
T125	0	183	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T35,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T10,T35,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T35,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T35,T41
1	0	Covered	T5,T6,T7
1	1	Covered	T10,T35,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T35,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T35,T43
0	1	Covered	T10,T35,T57
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T35,T43
1	-	Covered	T10,T35,T57

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T35,T43
DetectSt	168	Covered	T10,T35,T43
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T10,T35,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T35,T43
DebounceSt->IdleSt	163	Covered	T93,T87,T146
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T35,T43
IdleSt->DebounceSt	148	Covered	T10,T35,T43
StableSt->IdleSt	206	Covered	T10,T35,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T35,T43
0	1	Covered	T10,T35,T43
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T35,T43
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T35,T43
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T35,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T147,T148
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T35,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T35,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T35,T57
StableSt	-	-	-	-	-	-	0	Covered	T10,T35,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	82	0	0
CntIncr_A	9133666	55279	0	0
CntNoWrap_A	9133666	8487357	0	0
DetectStDropOut_A	9133666	0	0	0
DetectedOut_A	9133666	7172	0	0
DetectedPulseOut_A	9133666	39	0	0
DisabledIdleSt_A	9133666	8293370	0	0
DisabledNoDetection_A	9133666	8295657	0	0
EnterDebounceSt_A	9133666	45	0	0
EnterDetectSt_A	9133666	39	0	0
EnterStableSt_A	9133666	39	0	0
PulseIsPulse_A	9133666	39	0	0
StayInStableSt	9133666	7114	0	0
gen_high_level_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	82	0	0
T10	898	2	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	2	0	0
T43	0	2	0	0
T45	0	4	0	0
T46	0	2	0	0
T57	0	2	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	2	0	0
T149	0	4	0	0
T150	0	2	0	0
T151	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	55279	0	0
T10	898	84	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	59	0	0
T43	0	39	0	0
T45	0	150	0	0
T46	0	28	0	0
T57	0	70	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	52865	0	0
T149	0	200	0	0
T150	0	65	0	0
T151	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8487357	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	7172	0	0
T10	898	43	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	39	0	0
T43	0	37	0	0
T45	0	98	0	0
T46	0	62	0	0
T57	0	42	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	4755	0	0
T149	0	85	0	0
T150	0	10	0	0
T151	0	133	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	39	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8293370	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8295657	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	45	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	39	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	39	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	39	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	7114	0	0
T10	898	42	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	38	0	0
T43	0	35	0	0
T45	0	96	0	0
T46	0	60	0	0
T57	0	41	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	4754	0	0
T149	0	82	0	0
T150	0	9	0	0
T151	0	131	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	20	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	1	0	0
T45	0	2	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T96	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T12,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T10,T12,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T12,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T12
1	0	Covered	T7,T2,T4
1	1	Covered	T10,T12,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T44
0	1	Covered	T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T44
0	1	Covered	T10,T44,T47
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T12,T44
1	-	Covered	T10,T44,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T12,T44
DetectSt	168	Covered	T10,T12,T44
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T10,T12,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T12,T44
DebounceSt->IdleSt	163	Covered	T63,T43,T155
DetectSt->IdleSt	186	Covered	T154
DetectSt->StableSt	191	Covered	T10,T12,T44
IdleSt->DebounceSt	148	Covered	T10,T12,T44
StableSt->IdleSt	206	Covered	T10,T44,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T12,T44
0	1	Covered	T10,T12,T44
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T44
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T12,T44
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T12,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T155,T96
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T12,T44
DetectSt	-	-	-	-	1	-	-	Covered	T154
DetectSt	-	-	-	-	0	1	-	Covered	T10,T12,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T44,T47
StableSt	-	-	-	-	-	-	0	Covered	T10,T12,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	158	0	0
CntIncr_A	9133666	263791	0	0
CntNoWrap_A	9133666	8487281	0	0
DetectStDropOut_A	9133666	1	0	0
DetectedOut_A	9133666	37933	0	0
DetectedPulseOut_A	9133666	75	0	0
DisabledIdleSt_A	9133666	7811430	0	0
DisabledNoDetection_A	9133666	7813707	0	0
EnterDebounceSt_A	9133666	84	0	0
EnterDetectSt_A	9133666	76	0	0
EnterStableSt_A	9133666	75	0	0
PulseIsPulse_A	9133666	75	0	0
StayInStableSt	9133666	37828	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9133666	2599	0	0
gen_low_level_sva.LowLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	45	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	158	0	0
T10	898	4	0	0
T11	22238	0	0	0
T12	1025	2	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	6	0	0
T47	0	2	0	0
T57	0	4	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T94	0	2	0	0
T156	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	263791	0	0
T10	898	168	0	0
T11	22238	0	0	0
T12	1025	60	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	35	0	0
T43	0	39	0	0
T44	0	64	0	0
T45	0	287	0	0
T47	0	49	0	0
T57	0	140	0	0
T58	691	0	0	0
T63	0	351	0	0
T70	523	0	0	0
T77	423	0	0	0
T94	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8487281	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	1	0	0
T147	2419	0	0	0
T154	5621	1	0	0
T157	618	0	0	0
T158	5591	0	0	0
T159	6218	0	0	0
T160	497	0	0	0
T161	11610	0	0	0
T162	503	0	0	0
T163	17887	0	0	0
T164	549	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	37933	0	0
T10	898	191	0	0
T11	22238	0	0	0
T12	1025	142	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	43	0	0
T44	0	342	0	0
T45	0	326	0	0
T47	0	18	0	0
T57	0	57	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T94	0	39	0	0
T151	0	8	0	0
T156	0	1932	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	75	0	0
T10	898	2	0	0
T11	22238	0	0	0
T12	1025	1	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T47	0	1	0	0
T57	0	2	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T94	0	1	0	0
T151	0	1	0	0
T156	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	7811430	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	7813707	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	84	0	0
T10	898	2	0	0
T11	22238	0	0	0
T12	1025	1	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T47	0	1	0	0
T57	0	2	0	0
T58	691	0	0	0
T63	0	1	0	0
T70	523	0	0	0
T77	423	0	0	0
T94	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	76	0	0
T10	898	2	0	0
T11	22238	0	0	0
T12	1025	1	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T47	0	1	0	0
T57	0	2	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T94	0	1	0	0
T151	0	1	0	0
T156	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	75	0	0
T10	898	2	0	0
T11	22238	0	0	0
T12	1025	1	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T47	0	1	0	0
T57	0	2	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T94	0	1	0	0
T151	0	1	0	0
T156	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	75	0	0
T10	898	2	0	0
T11	22238	0	0	0
T12	1025	1	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T47	0	1	0	0
T57	0	2	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T94	0	1	0	0
T151	0	1	0	0
T156	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	37828	0	0
T10	898	188	0	0
T11	22238	0	0	0
T12	1025	140	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	41	0	0
T44	0	341	0	0
T45	0	321	0	0
T47	0	17	0	0
T57	0	54	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T94	0	37	0	0
T151	0	7	0	0
T156	0	1929	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	2599	0	0
T1	564982	0	0	0
T2	21127	0	0	0
T3	825	0	0	0
T4	25465	0	0	0
T7	437	4	0	0
T9	0	11	0	0
T10	0	2	0	0
T14	8467	0	0	0
T15	494	4	0	0
T16	5016	0	0	0
T17	457	7	0	0
T18	878	0	0	0
T26	0	4	0	0
T27	0	4	0	0
T28	0	7	0	0
T29	0	6	0	0
T76	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	45	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T151	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0