Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 46 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
| Total | Covered | Percent |
Conditions | 21 | 19 | 90.48 |
Logical | 21 | 19 | 90.48 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T10,T13,T44 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T5,T6,T7 |
VC_COV_UNR |
1 | Covered | T10,T13,T44 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T10,T13,T44 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9,T10,T13 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T10,T13,T44 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T10,T13,T44 |
0 | 1 | Covered | T167,T168 |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T10,T13,T44 |
0 | 1 | Covered | T44,T42,T57 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T10,T13,T44 |
1 | - | Covered | T44,T42,T57 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T10,T13,T44 |
DetectSt |
168 |
Covered |
T10,T13,T44 |
IdleSt |
163 |
Covered |
T5,T6,T7 |
StableSt |
191 |
Covered |
T10,T13,T44 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T10,T13,T44 |
DebounceSt->IdleSt |
163 |
Covered |
T87,T169,T88 |
DetectSt->IdleSt |
186 |
Covered |
T167,T168 |
DetectSt->StableSt |
191 |
Covered |
T10,T13,T44 |
IdleSt->DebounceSt |
148 |
Covered |
T10,T13,T44 |
StableSt->IdleSt |
206 |
Covered |
T44,T43,T42 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
| Line No. | Total | Covered | Percent |
Branches |
|
20 |
20 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
10 |
10 |
100.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T10,T13,T44 |
|
0 |
1 |
Covered |
T10,T13,T44 |
|
0 |
0 |
Excluded |
T5,T6,T7 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T10,T13,T44 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T10,T13,T44 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T5,T6,T7 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T87,T88 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T10,T13,T44 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T169 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T10,T13,T44 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T167,T168 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T10,T13,T44 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Excluded |
|
VC_COV_UNR |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T44,T42,T57 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T10,T13,T44 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
75 |
0 |
0 |
T10 |
898 |
2 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
2 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T42 |
0 |
4 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T44 |
0 |
4 |
0 |
0 |
T45 |
0 |
4 |
0 |
0 |
T57 |
0 |
2 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T156 |
0 |
2 |
0 |
0 |
T170 |
0 |
4 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
154857 |
0 |
0 |
T10 |
898 |
84 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
855 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T42 |
0 |
146 |
0 |
0 |
T43 |
0 |
39 |
0 |
0 |
T44 |
0 |
128 |
0 |
0 |
T45 |
0 |
110 |
0 |
0 |
T57 |
0 |
70 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T150 |
0 |
130 |
0 |
0 |
T156 |
0 |
58822 |
0 |
0 |
T170 |
0 |
86 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8487364 |
0 |
0 |
T1 |
564982 |
564581 |
0 |
0 |
T2 |
21127 |
20688 |
0 |
0 |
T3 |
825 |
424 |
0 |
0 |
T4 |
25465 |
23796 |
0 |
0 |
T5 |
738 |
337 |
0 |
0 |
T6 |
435 |
34 |
0 |
0 |
T7 |
437 |
36 |
0 |
0 |
T14 |
8467 |
8058 |
0 |
0 |
T15 |
494 |
93 |
0 |
0 |
T16 |
5016 |
4615 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
2 |
0 |
0 |
T167 |
4692 |
1 |
0 |
0 |
T168 |
0 |
1 |
0 |
0 |
T171 |
2145 |
0 |
0 |
0 |
T172 |
423 |
0 |
0 |
0 |
T173 |
452 |
0 |
0 |
0 |
T174 |
2832 |
0 |
0 |
0 |
T175 |
415 |
0 |
0 |
0 |
T176 |
5276 |
0 |
0 |
0 |
T177 |
407 |
0 |
0 |
0 |
T178 |
16850 |
0 |
0 |
0 |
T179 |
4420 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
122981 |
0 |
0 |
T10 |
898 |
132 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
44 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T42 |
0 |
189 |
0 |
0 |
T43 |
0 |
37 |
0 |
0 |
T44 |
0 |
177 |
0 |
0 |
T45 |
0 |
95 |
0 |
0 |
T57 |
0 |
46 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T150 |
0 |
155 |
0 |
0 |
T156 |
0 |
65081 |
0 |
0 |
T170 |
0 |
190 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
34 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T42 |
0 |
2 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
0 |
2 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T170 |
0 |
2 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
7645070 |
0 |
0 |
T1 |
564982 |
564581 |
0 |
0 |
T2 |
21127 |
20688 |
0 |
0 |
T3 |
825 |
424 |
0 |
0 |
T4 |
25465 |
23796 |
0 |
0 |
T5 |
738 |
337 |
0 |
0 |
T6 |
435 |
34 |
0 |
0 |
T7 |
437 |
36 |
0 |
0 |
T14 |
8467 |
8058 |
0 |
0 |
T15 |
494 |
93 |
0 |
0 |
T16 |
5016 |
4615 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
7647359 |
0 |
0 |
T1 |
564982 |
564582 |
0 |
0 |
T2 |
21127 |
20694 |
0 |
0 |
T3 |
825 |
425 |
0 |
0 |
T4 |
25465 |
23808 |
0 |
0 |
T5 |
738 |
338 |
0 |
0 |
T6 |
435 |
35 |
0 |
0 |
T7 |
437 |
37 |
0 |
0 |
T14 |
8467 |
8060 |
0 |
0 |
T15 |
494 |
94 |
0 |
0 |
T16 |
5016 |
4616 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
39 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T42 |
0 |
2 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
0 |
2 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T170 |
0 |
2 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
36 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T42 |
0 |
2 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
0 |
2 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T170 |
0 |
2 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
34 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T42 |
0 |
2 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
0 |
2 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T170 |
0 |
2 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
34 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T42 |
0 |
2 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
0 |
2 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T170 |
0 |
2 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
122931 |
0 |
0 |
T10 |
898 |
130 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
42 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T42 |
0 |
186 |
0 |
0 |
T43 |
0 |
35 |
0 |
0 |
T44 |
0 |
175 |
0 |
0 |
T45 |
0 |
92 |
0 |
0 |
T57 |
0 |
45 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T150 |
0 |
152 |
0 |
0 |
T156 |
0 |
65080 |
0 |
0 |
T170 |
0 |
187 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8489780 |
0 |
0 |
T1 |
564982 |
564582 |
0 |
0 |
T2 |
21127 |
20694 |
0 |
0 |
T3 |
825 |
425 |
0 |
0 |
T4 |
25465 |
23808 |
0 |
0 |
T5 |
738 |
338 |
0 |
0 |
T6 |
435 |
35 |
0 |
0 |
T7 |
437 |
37 |
0 |
0 |
T14 |
8467 |
8060 |
0 |
0 |
T15 |
494 |
94 |
0 |
0 |
T16 |
5016 |
4616 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
18 |
0 |
0 |
T25 |
1119 |
0 |
0 |
0 |
T30 |
676 |
0 |
0 |
0 |
T36 |
20520 |
0 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T44 |
994 |
2 |
0 |
0 |
T45 |
0 |
1 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T59 |
26940 |
0 |
0 |
0 |
T62 |
2265 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T78 |
6020 |
0 |
0 |
0 |
T138 |
450 |
0 |
0 |
0 |
T143 |
0 |
1 |
0 |
0 |
T150 |
0 |
1 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T170 |
0 |
1 |
0 |
0 |
T180 |
0 |
1 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 46 | 100.00 |
CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
58 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
| Total | Covered | Percent |
Conditions | 21 | 19 | 90.48 |
Logical | 21 | 19 | 90.48 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T9,T10,T44 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T5,T6,T7 |
VC_COV_UNR |
1 | Covered | T9,T10,T44 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T9,T10,T44 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9,T10,T44 |
1 | 0 | Covered | T7,T2,T4 |
1 | 1 | Covered | T9,T10,T44 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T9,T10,T44 |
0 | 1 | Covered | T182 |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T9,T10,T44 |
0 | 1 | Covered | T10,T44,T114 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T9,T10,T44 |
1 | - | Covered | T10,T44,T114 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T9,T10,T44 |
DetectSt |
168 |
Covered |
T9,T10,T44 |
IdleSt |
163 |
Covered |
T5,T6,T7 |
StableSt |
191 |
Covered |
T9,T10,T44 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T9,T10,T44 |
DebounceSt->IdleSt |
163 |
Covered |
T166,T155,T87 |
DetectSt->IdleSt |
186 |
Covered |
T182 |
DetectSt->StableSt |
191 |
Covered |
T9,T10,T44 |
IdleSt->DebounceSt |
148 |
Covered |
T9,T10,T44 |
StableSt->IdleSt |
206 |
Covered |
T9,T10,T44 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
| Line No. | Total | Covered | Percent |
Branches |
|
20 |
20 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
10 |
10 |
100.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T9,T10,T44 |
|
0 |
1 |
Covered |
T9,T10,T44 |
|
0 |
0 |
Excluded |
T5,T6,T7 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T10,T44 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T9,T10,T44 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T5,T6,T7 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T87,T88 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T9,T10,T44 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T166,T155 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T9,T10,T44 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T182 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T9,T10,T44 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Excluded |
|
VC_COV_UNR |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T10,T44,T114 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T9,T10,T44 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
122 |
0 |
0 |
T9 |
2955 |
2 |
0 |
0 |
T10 |
898 |
2 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T41 |
0 |
2 |
0 |
0 |
T44 |
0 |
6 |
0 |
0 |
T45 |
0 |
4 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T93 |
0 |
2 |
0 |
0 |
T114 |
0 |
2 |
0 |
0 |
T166 |
0 |
3 |
0 |
0 |
T183 |
0 |
2 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
45729 |
0 |
0 |
T9 |
2955 |
25 |
0 |
0 |
T10 |
898 |
84 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T41 |
0 |
35 |
0 |
0 |
T44 |
0 |
192 |
0 |
0 |
T45 |
0 |
192 |
0 |
0 |
T46 |
0 |
28 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T93 |
0 |
42362 |
0 |
0 |
T114 |
0 |
67 |
0 |
0 |
T166 |
0 |
88 |
0 |
0 |
T183 |
0 |
61 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8487317 |
0 |
0 |
T1 |
564982 |
564581 |
0 |
0 |
T2 |
21127 |
20688 |
0 |
0 |
T3 |
825 |
424 |
0 |
0 |
T4 |
25465 |
23796 |
0 |
0 |
T5 |
738 |
337 |
0 |
0 |
T6 |
435 |
34 |
0 |
0 |
T7 |
437 |
36 |
0 |
0 |
T14 |
8467 |
8058 |
0 |
0 |
T15 |
494 |
93 |
0 |
0 |
T16 |
5016 |
4615 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
1 |
0 |
0 |
T182 |
799 |
1 |
0 |
0 |
T184 |
502 |
0 |
0 |
0 |
T185 |
777 |
0 |
0 |
0 |
T186 |
525 |
0 |
0 |
0 |
T187 |
526 |
0 |
0 |
0 |
T188 |
498 |
0 |
0 |
0 |
T189 |
504 |
0 |
0 |
0 |
T190 |
443 |
0 |
0 |
0 |
T191 |
523 |
0 |
0 |
0 |
T192 |
855 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
104166 |
0 |
0 |
T9 |
2955 |
70 |
0 |
0 |
T10 |
898 |
188 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T41 |
0 |
81 |
0 |
0 |
T44 |
0 |
84 |
0 |
0 |
T45 |
0 |
405 |
0 |
0 |
T46 |
0 |
49 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T93 |
0 |
100071 |
0 |
0 |
T114 |
0 |
148 |
0 |
0 |
T166 |
0 |
60 |
0 |
0 |
T183 |
0 |
15 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
58 |
0 |
0 |
T9 |
2955 |
1 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T93 |
0 |
1 |
0 |
0 |
T114 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T183 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8302589 |
0 |
0 |
T1 |
564982 |
564581 |
0 |
0 |
T2 |
21127 |
20688 |
0 |
0 |
T3 |
825 |
424 |
0 |
0 |
T4 |
25465 |
23796 |
0 |
0 |
T5 |
738 |
337 |
0 |
0 |
T6 |
435 |
34 |
0 |
0 |
T7 |
437 |
36 |
0 |
0 |
T14 |
8467 |
8058 |
0 |
0 |
T15 |
494 |
93 |
0 |
0 |
T16 |
5016 |
4615 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8304876 |
0 |
0 |
T1 |
564982 |
564582 |
0 |
0 |
T2 |
21127 |
20694 |
0 |
0 |
T3 |
825 |
425 |
0 |
0 |
T4 |
25465 |
23808 |
0 |
0 |
T5 |
738 |
338 |
0 |
0 |
T6 |
435 |
35 |
0 |
0 |
T7 |
437 |
37 |
0 |
0 |
T14 |
8467 |
8060 |
0 |
0 |
T15 |
494 |
94 |
0 |
0 |
T16 |
5016 |
4616 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
63 |
0 |
0 |
T9 |
2955 |
1 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T93 |
0 |
1 |
0 |
0 |
T114 |
0 |
1 |
0 |
0 |
T166 |
0 |
2 |
0 |
0 |
T183 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
59 |
0 |
0 |
T9 |
2955 |
1 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T93 |
0 |
1 |
0 |
0 |
T114 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T183 |
0 |
1 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
58 |
0 |
0 |
T9 |
2955 |
1 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T93 |
0 |
1 |
0 |
0 |
T114 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T183 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
58 |
0 |
0 |
T9 |
2955 |
1 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T93 |
0 |
1 |
0 |
0 |
T114 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T183 |
0 |
1 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
104076 |
0 |
0 |
T9 |
2955 |
68 |
0 |
0 |
T10 |
898 |
187 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T41 |
0 |
79 |
0 |
0 |
T44 |
0 |
80 |
0 |
0 |
T45 |
0 |
402 |
0 |
0 |
T46 |
0 |
47 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T93 |
0 |
100069 |
0 |
0 |
T114 |
0 |
147 |
0 |
0 |
T166 |
0 |
58 |
0 |
0 |
T183 |
0 |
14 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
2935 |
0 |
0 |
T1 |
564982 |
0 |
0 |
0 |
T2 |
21127 |
0 |
0 |
0 |
T3 |
825 |
0 |
0 |
0 |
T4 |
25465 |
5 |
0 |
0 |
T7 |
437 |
6 |
0 |
0 |
T9 |
0 |
10 |
0 |
0 |
T14 |
8467 |
0 |
0 |
0 |
T15 |
494 |
5 |
0 |
0 |
T16 |
5016 |
0 |
0 |
0 |
T17 |
457 |
5 |
0 |
0 |
T18 |
878 |
3 |
0 |
0 |
T26 |
0 |
3 |
0 |
0 |
T28 |
0 |
6 |
0 |
0 |
T61 |
0 |
3 |
0 |
0 |
T76 |
0 |
3 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8489780 |
0 |
0 |
T1 |
564982 |
564582 |
0 |
0 |
T2 |
21127 |
20694 |
0 |
0 |
T3 |
825 |
425 |
0 |
0 |
T4 |
25465 |
23808 |
0 |
0 |
T5 |
738 |
338 |
0 |
0 |
T6 |
435 |
35 |
0 |
0 |
T7 |
437 |
37 |
0 |
0 |
T14 |
8467 |
8060 |
0 |
0 |
T15 |
494 |
94 |
0 |
0 |
T16 |
5016 |
4616 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
26 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
0 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T44 |
0 |
2 |
0 |
0 |
T45 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T96 |
0 |
1 |
0 |
0 |
T114 |
0 |
1 |
0 |
0 |
T143 |
0 |
1 |
0 |
0 |
T168 |
0 |
1 |
0 |
0 |
T183 |
0 |
1 |
0 |
0 |
T193 |
0 |
1 |
0 |
0 |
T194 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 46 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
| Total | Covered | Percent |
Conditions | 21 | 19 | 90.48 |
Logical | 21 | 19 | 90.48 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T7,T1,T2 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T7,T1,T2 |
1 | 1 | Covered | T7,T1,T2 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T9,T10,T12 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T5,T6,T7 |
VC_COV_UNR |
1 | Covered | T9,T10,T12 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T9,T10,T12 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9,T10,T12 |
1 | 0 | Covered | T7,T1,T2 |
1 | 1 | Covered | T9,T10,T12 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T9,T10,T12 |
0 | 1 | Covered | T195 |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T9,T10,T12 |
0 | 1 | Covered | T12,T35,T44 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T9,T10,T12 |
1 | - | Covered | T12,T35,T44 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T9,T10,T12 |
DetectSt |
168 |
Covered |
T9,T10,T12 |
IdleSt |
163 |
Covered |
T5,T6,T7 |
StableSt |
191 |
Covered |
T9,T10,T12 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T9,T10,T12 |
DebounceSt->IdleSt |
163 |
Covered |
T43,T46,T87 |
DetectSt->IdleSt |
186 |
Covered |
T195 |
DetectSt->StableSt |
191 |
Covered |
T9,T10,T12 |
IdleSt->DebounceSt |
148 |
Covered |
T9,T10,T12 |
StableSt->IdleSt |
206 |
Covered |
T9,T12,T35 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
| Line No. | Total | Covered | Percent |
Branches |
|
20 |
20 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
10 |
10 |
100.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T9,T10,T12 |
|
0 |
1 |
Covered |
T9,T10,T12 |
|
0 |
0 |
Excluded |
T5,T6,T7 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T10,T12 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T9,T10,T12 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T7,T1,T2 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T87,T88 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T9,T10,T12 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T43,T46,T196 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T9,T10,T12 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T195 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T9,T10,T12 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Excluded |
|
VC_COV_UNR |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T12,T35,T44 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T9,T10,T12 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
159 |
0 |
0 |
T9 |
2955 |
2 |
0 |
0 |
T10 |
898 |
2 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
2 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
0 |
6 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T47 |
0 |
2 |
0 |
0 |
T57 |
0 |
2 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T114 |
0 |
4 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
203946 |
0 |
0 |
T9 |
2955 |
25 |
0 |
0 |
T10 |
898 |
84 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
60 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
0 |
118 |
0 |
0 |
T43 |
0 |
32 |
0 |
0 |
T44 |
0 |
192 |
0 |
0 |
T45 |
0 |
95 |
0 |
0 |
T47 |
0 |
49 |
0 |
0 |
T57 |
0 |
70 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T114 |
0 |
134 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8487280 |
0 |
0 |
T1 |
564982 |
564581 |
0 |
0 |
T2 |
21127 |
20688 |
0 |
0 |
T3 |
825 |
424 |
0 |
0 |
T4 |
25465 |
23796 |
0 |
0 |
T5 |
738 |
337 |
0 |
0 |
T6 |
435 |
34 |
0 |
0 |
T7 |
437 |
36 |
0 |
0 |
T14 |
8467 |
8058 |
0 |
0 |
T15 |
494 |
93 |
0 |
0 |
T16 |
5016 |
4615 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
1 |
0 |
0 |
T195 |
2657 |
1 |
0 |
0 |
T197 |
5219 |
0 |
0 |
0 |
T198 |
506 |
0 |
0 |
0 |
T199 |
13559 |
0 |
0 |
0 |
T200 |
722 |
0 |
0 |
0 |
T201 |
402 |
0 |
0 |
0 |
T202 |
423 |
0 |
0 |
0 |
T203 |
491 |
0 |
0 |
0 |
T204 |
54730 |
0 |
0 |
0 |
T205 |
442 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
135374 |
0 |
0 |
T9 |
2955 |
43 |
0 |
0 |
T10 |
898 |
47 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
249 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
0 |
59 |
0 |
0 |
T44 |
0 |
191 |
0 |
0 |
T45 |
0 |
204 |
0 |
0 |
T47 |
0 |
190 |
0 |
0 |
T57 |
0 |
166 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T114 |
0 |
171 |
0 |
0 |
T170 |
0 |
145 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
76 |
0 |
0 |
T9 |
2955 |
1 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
1 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T114 |
0 |
2 |
0 |
0 |
T170 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
7820062 |
0 |
0 |
T1 |
564982 |
564581 |
0 |
0 |
T2 |
21127 |
20688 |
0 |
0 |
T3 |
825 |
424 |
0 |
0 |
T4 |
25465 |
23796 |
0 |
0 |
T5 |
738 |
337 |
0 |
0 |
T6 |
435 |
34 |
0 |
0 |
T7 |
437 |
36 |
0 |
0 |
T14 |
8467 |
8058 |
0 |
0 |
T15 |
494 |
93 |
0 |
0 |
T16 |
5016 |
4615 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
7822341 |
0 |
0 |
T1 |
564982 |
564582 |
0 |
0 |
T2 |
21127 |
20694 |
0 |
0 |
T3 |
825 |
425 |
0 |
0 |
T4 |
25465 |
23808 |
0 |
0 |
T5 |
738 |
338 |
0 |
0 |
T6 |
435 |
35 |
0 |
0 |
T7 |
437 |
37 |
0 |
0 |
T14 |
8467 |
8060 |
0 |
0 |
T15 |
494 |
94 |
0 |
0 |
T16 |
5016 |
4616 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
83 |
0 |
0 |
T9 |
2955 |
1 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
1 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T114 |
0 |
2 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
77 |
0 |
0 |
T9 |
2955 |
1 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
1 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T114 |
0 |
2 |
0 |
0 |
T170 |
0 |
1 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
76 |
0 |
0 |
T9 |
2955 |
1 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
1 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T114 |
0 |
2 |
0 |
0 |
T170 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
76 |
0 |
0 |
T9 |
2955 |
1 |
0 |
0 |
T10 |
898 |
1 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
1 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T114 |
0 |
2 |
0 |
0 |
T170 |
0 |
1 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
135264 |
0 |
0 |
T9 |
2955 |
41 |
0 |
0 |
T10 |
898 |
45 |
0 |
0 |
T11 |
22238 |
0 |
0 |
0 |
T12 |
1025 |
248 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T27 |
1322 |
0 |
0 |
0 |
T29 |
525 |
0 |
0 |
0 |
T35 |
0 |
56 |
0 |
0 |
T44 |
0 |
187 |
0 |
0 |
T45 |
0 |
203 |
0 |
0 |
T47 |
0 |
188 |
0 |
0 |
T57 |
0 |
164 |
0 |
0 |
T58 |
691 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T114 |
0 |
168 |
0 |
0 |
T170 |
0 |
144 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8489780 |
0 |
0 |
T1 |
564982 |
564582 |
0 |
0 |
T2 |
21127 |
20694 |
0 |
0 |
T3 |
825 |
425 |
0 |
0 |
T4 |
25465 |
23808 |
0 |
0 |
T5 |
738 |
338 |
0 |
0 |
T6 |
435 |
35 |
0 |
0 |
T7 |
437 |
37 |
0 |
0 |
T14 |
8467 |
8060 |
0 |
0 |
T15 |
494 |
94 |
0 |
0 |
T16 |
5016 |
4616 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
42 |
0 |
0 |
T12 |
1025 |
1 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T35 |
4876 |
1 |
0 |
0 |
T40 |
1001 |
0 |
0 |
0 |
T44 |
994 |
2 |
0 |
0 |
T45 |
0 |
1 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T114 |
0 |
1 |
0 |
0 |
T150 |
0 |
1 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T170 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 44 | 95.65 |
CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 30 | 93.75 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
58 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
0 |
1 |
187 |
0 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
| Total | Covered | Percent |
Conditions | 21 | 18 | 85.71 |
Logical | 21 | 18 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
-1- | Status | Tests |
0 | Covered | T7,T1,T2 |
1 | Covered | T5,T6,T7 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T13,T35,T40 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T5,T6,T7 |
VC_COV_UNR |
1 | Covered | T13,T35,T40 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T13,T35,T40 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9,T13,T35 |
1 | 0 | Covered | T7,T1,T2 |
1 | 1 | Covered | T13,T35,T40 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T13,T35,T40 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T13,T35,T40 |
0 | 1 | Covered | T13,T35,T40 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T13,T35,T40 |
1 | - | Covered | T13,T35,T40 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
5 |
83.33 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T13,T35,T40 |
DetectSt |
168 |
Covered |
T13,T35,T40 |
IdleSt |
163 |
Covered |
T5,T6,T7 |
StableSt |
191 |
Covered |
T13,T35,T40 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T13,T35,T40 |
DebounceSt->IdleSt |
163 |
Covered |
T43,T167,T87 |
DetectSt->IdleSt |
186 |
Not Covered |
|
DetectSt->StableSt |
191 |
Covered |
T13,T35,T40 |
IdleSt->DebounceSt |
148 |
Covered |
T13,T35,T40 |
StableSt->IdleSt |
206 |
Covered |
T13,T35,T40 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
| Line No. | Total | Covered | Percent |
Branches |
|
20 |
19 |
95.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
10 |
9 |
90.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T13,T35,T40 |
|
0 |
1 |
Covered |
T13,T35,T40 |
|
0 |
0 |
Excluded |
T5,T6,T7 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T13,T35,T40 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T13,T35,T40 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T5,T6,T7 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T87,T88 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T13,T35,T40 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T43,T167,T146 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T13,T35,T40 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Not Covered |
|
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T13,T35,T40 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Excluded |
|
VC_COV_UNR |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T13,T35,T40 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T13,T35,T40 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
59 |
0 |
0 |
T13 |
3601 |
2 |
0 |
0 |
T35 |
4876 |
2 |
0 |
0 |
T40 |
1001 |
4 |
0 |
0 |
T43 |
0 |
3 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T46 |
0 |
6 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T114 |
0 |
2 |
0 |
0 |
T149 |
0 |
2 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
T156 |
0 |
2 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T206 |
0 |
2 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
108585 |
0 |
0 |
T13 |
3601 |
855 |
0 |
0 |
T35 |
4876 |
59 |
0 |
0 |
T40 |
1001 |
148 |
0 |
0 |
T43 |
0 |
71 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T46 |
0 |
84 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T114 |
0 |
67 |
0 |
0 |
T149 |
0 |
100 |
0 |
0 |
T151 |
0 |
42 |
0 |
0 |
T156 |
0 |
58822 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T206 |
0 |
42 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8487380 |
0 |
0 |
T1 |
564982 |
564581 |
0 |
0 |
T2 |
21127 |
20688 |
0 |
0 |
T3 |
825 |
424 |
0 |
0 |
T4 |
25465 |
23796 |
0 |
0 |
T5 |
738 |
337 |
0 |
0 |
T6 |
435 |
34 |
0 |
0 |
T7 |
437 |
36 |
0 |
0 |
T14 |
8467 |
8058 |
0 |
0 |
T15 |
494 |
93 |
0 |
0 |
T16 |
5016 |
4615 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
122368 |
0 |
0 |
T13 |
3601 |
40 |
0 |
0 |
T35 |
4876 |
40 |
0 |
0 |
T40 |
1001 |
177 |
0 |
0 |
T43 |
0 |
41 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T46 |
0 |
137 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T114 |
0 |
40 |
0 |
0 |
T149 |
0 |
143 |
0 |
0 |
T151 |
0 |
18 |
0 |
0 |
T156 |
0 |
65079 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T206 |
0 |
104 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
27 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T35 |
4876 |
1 |
0 |
0 |
T40 |
1001 |
2 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T114 |
0 |
1 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T206 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8016058 |
0 |
0 |
T1 |
564982 |
564581 |
0 |
0 |
T2 |
21127 |
20688 |
0 |
0 |
T3 |
825 |
424 |
0 |
0 |
T4 |
25465 |
23796 |
0 |
0 |
T5 |
738 |
337 |
0 |
0 |
T6 |
435 |
34 |
0 |
0 |
T7 |
437 |
36 |
0 |
0 |
T14 |
8467 |
8058 |
0 |
0 |
T15 |
494 |
93 |
0 |
0 |
T16 |
5016 |
4615 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8018358 |
0 |
0 |
T1 |
564982 |
564582 |
0 |
0 |
T2 |
21127 |
20694 |
0 |
0 |
T3 |
825 |
425 |
0 |
0 |
T4 |
25465 |
23808 |
0 |
0 |
T5 |
738 |
338 |
0 |
0 |
T6 |
435 |
35 |
0 |
0 |
T7 |
437 |
37 |
0 |
0 |
T14 |
8467 |
8060 |
0 |
0 |
T15 |
494 |
94 |
0 |
0 |
T16 |
5016 |
4616 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
32 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T35 |
4876 |
1 |
0 |
0 |
T40 |
1001 |
2 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T114 |
0 |
1 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T206 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
27 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T35 |
4876 |
1 |
0 |
0 |
T40 |
1001 |
2 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T114 |
0 |
1 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T206 |
0 |
1 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
27 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T35 |
4876 |
1 |
0 |
0 |
T40 |
1001 |
2 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T114 |
0 |
1 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T206 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
27 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T35 |
4876 |
1 |
0 |
0 |
T40 |
1001 |
2 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T114 |
0 |
1 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T206 |
0 |
1 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
122330 |
0 |
0 |
T13 |
3601 |
39 |
0 |
0 |
T35 |
4876 |
39 |
0 |
0 |
T40 |
1001 |
174 |
0 |
0 |
T43 |
0 |
39 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T46 |
0 |
133 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T114 |
0 |
39 |
0 |
0 |
T149 |
0 |
141 |
0 |
0 |
T151 |
0 |
16 |
0 |
0 |
T156 |
0 |
65077 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T206 |
0 |
103 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
6495 |
0 |
0 |
T1 |
564982 |
7 |
0 |
0 |
T2 |
21127 |
25 |
0 |
0 |
T3 |
825 |
4 |
0 |
0 |
T4 |
25465 |
8 |
0 |
0 |
T7 |
437 |
5 |
0 |
0 |
T8 |
0 |
16 |
0 |
0 |
T14 |
8467 |
25 |
0 |
0 |
T15 |
494 |
8 |
0 |
0 |
T16 |
5016 |
21 |
0 |
0 |
T17 |
457 |
7 |
0 |
0 |
T18 |
878 |
0 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8489780 |
0 |
0 |
T1 |
564982 |
564582 |
0 |
0 |
T2 |
21127 |
20694 |
0 |
0 |
T3 |
825 |
425 |
0 |
0 |
T4 |
25465 |
23808 |
0 |
0 |
T5 |
738 |
338 |
0 |
0 |
T6 |
435 |
35 |
0 |
0 |
T7 |
437 |
37 |
0 |
0 |
T14 |
8467 |
8060 |
0 |
0 |
T15 |
494 |
94 |
0 |
0 |
T16 |
5016 |
4616 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
16 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T35 |
4876 |
1 |
0 |
0 |
T40 |
1001 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T114 |
0 |
1 |
0 |
0 |
T143 |
0 |
2 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T195 |
0 |
1 |
0 |
0 |
T206 |
0 |
1 |
0 |
0 |
T207 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 46 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
| Total | Covered | Percent |
Conditions | 21 | 19 | 90.48 |
Logical | 21 | 19 | 90.48 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T7,T2 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T6,T7,T2 |
1 | 1 | Covered | T6,T7,T2 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T13,T40,T43 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T5,T6,T7 |
VC_COV_UNR |
1 | Covered | T13,T40,T43 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T13,T40,T43 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T10,T13,T40 |
1 | 0 | Covered | T6,T7,T2 |
1 | 1 | Covered | T13,T40,T43 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T13,T40,T43 |
0 | 1 | Covered | T143,T208 |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T13,T40,T43 |
0 | 1 | Covered | T13,T40,T45 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T13,T40,T43 |
1 | - | Covered | T13,T40,T45 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T13,T40,T43 |
DetectSt |
168 |
Covered |
T13,T40,T43 |
IdleSt |
163 |
Covered |
T5,T6,T7 |
StableSt |
191 |
Covered |
T13,T40,T43 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T13,T40,T43 |
DebounceSt->IdleSt |
163 |
Covered |
T96,T188,T87 |
DetectSt->IdleSt |
186 |
Covered |
T143,T208 |
DetectSt->StableSt |
191 |
Covered |
T13,T40,T43 |
IdleSt->DebounceSt |
148 |
Covered |
T13,T40,T43 |
StableSt->IdleSt |
206 |
Covered |
T13,T40,T43 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
| Line No. | Total | Covered | Percent |
Branches |
|
20 |
20 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
10 |
10 |
100.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T13,T40,T43 |
|
0 |
1 |
Covered |
T13,T40,T43 |
|
0 |
0 |
Excluded |
T5,T6,T7 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T13,T40,T43 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T13,T40,T43 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T6,T7,T2 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T87,T88 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T13,T40,T43 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T96,T188 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T13,T40,T43 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T143,T208 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T13,T40,T43 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Excluded |
|
VC_COV_UNR |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T13,T40,T45 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T13,T40,T43 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
114 |
0 |
0 |
T13 |
3601 |
2 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T40 |
1001 |
6 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
8 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T94 |
0 |
2 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T156 |
0 |
2 |
0 |
0 |
T165 |
0 |
2 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T209 |
0 |
2 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
62444 |
0 |
0 |
T13 |
3601 |
855 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T40 |
1001 |
222 |
0 |
0 |
T43 |
0 |
32 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
244 |
0 |
0 |
T46 |
0 |
28 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T94 |
0 |
96 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T151 |
0 |
21 |
0 |
0 |
T156 |
0 |
58822 |
0 |
0 |
T165 |
0 |
12 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T209 |
0 |
84 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8487325 |
0 |
0 |
T1 |
564982 |
564581 |
0 |
0 |
T2 |
21127 |
20688 |
0 |
0 |
T3 |
825 |
424 |
0 |
0 |
T4 |
25465 |
23796 |
0 |
0 |
T5 |
738 |
337 |
0 |
0 |
T6 |
435 |
34 |
0 |
0 |
T7 |
437 |
36 |
0 |
0 |
T14 |
8467 |
8058 |
0 |
0 |
T15 |
494 |
93 |
0 |
0 |
T16 |
5016 |
4615 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
2 |
0 |
0 |
T143 |
198163 |
1 |
0 |
0 |
T195 |
2657 |
0 |
0 |
0 |
T197 |
5219 |
0 |
0 |
0 |
T198 |
506 |
0 |
0 |
0 |
T199 |
13559 |
0 |
0 |
0 |
T200 |
722 |
0 |
0 |
0 |
T201 |
402 |
0 |
0 |
0 |
T208 |
0 |
1 |
0 |
0 |
T210 |
407 |
0 |
0 |
0 |
T211 |
522 |
0 |
0 |
0 |
T212 |
704964 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
66407 |
0 |
0 |
T13 |
3601 |
424 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T40 |
1001 |
200 |
0 |
0 |
T43 |
0 |
73 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
759 |
0 |
0 |
T46 |
0 |
177 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T94 |
0 |
136 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T151 |
0 |
135 |
0 |
0 |
T156 |
0 |
60757 |
0 |
0 |
T165 |
0 |
60 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T209 |
0 |
46 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
53 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T40 |
1001 |
3 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
4 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T94 |
0 |
1 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T165 |
0 |
1 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T209 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8225226 |
0 |
0 |
T1 |
564982 |
564581 |
0 |
0 |
T2 |
21127 |
20688 |
0 |
0 |
T3 |
825 |
424 |
0 |
0 |
T4 |
25465 |
23796 |
0 |
0 |
T5 |
738 |
337 |
0 |
0 |
T6 |
435 |
34 |
0 |
0 |
T7 |
437 |
36 |
0 |
0 |
T14 |
8467 |
8058 |
0 |
0 |
T15 |
494 |
93 |
0 |
0 |
T16 |
5016 |
4615 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8227517 |
0 |
0 |
T1 |
564982 |
564582 |
0 |
0 |
T2 |
21127 |
20694 |
0 |
0 |
T3 |
825 |
425 |
0 |
0 |
T4 |
25465 |
23808 |
0 |
0 |
T5 |
738 |
338 |
0 |
0 |
T6 |
435 |
35 |
0 |
0 |
T7 |
437 |
37 |
0 |
0 |
T14 |
8467 |
8060 |
0 |
0 |
T15 |
494 |
94 |
0 |
0 |
T16 |
5016 |
4616 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
59 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T40 |
1001 |
3 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
4 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T94 |
0 |
1 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T165 |
0 |
1 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T209 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
55 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T40 |
1001 |
3 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
4 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T94 |
0 |
1 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T165 |
0 |
1 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T209 |
0 |
1 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
53 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T40 |
1001 |
3 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
4 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T94 |
0 |
1 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T165 |
0 |
1 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T209 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
53 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T40 |
1001 |
3 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
4 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T94 |
0 |
1 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T165 |
0 |
1 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T209 |
0 |
1 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
66334 |
0 |
0 |
T13 |
3601 |
423 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T40 |
1001 |
196 |
0 |
0 |
T43 |
0 |
71 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
753 |
0 |
0 |
T46 |
0 |
176 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T94 |
0 |
134 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T151 |
0 |
134 |
0 |
0 |
T156 |
0 |
60756 |
0 |
0 |
T165 |
0 |
59 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T209 |
0 |
44 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8489780 |
0 |
0 |
T1 |
564982 |
564582 |
0 |
0 |
T2 |
21127 |
20694 |
0 |
0 |
T3 |
825 |
425 |
0 |
0 |
T4 |
25465 |
23808 |
0 |
0 |
T5 |
738 |
338 |
0 |
0 |
T6 |
435 |
35 |
0 |
0 |
T7 |
437 |
37 |
0 |
0 |
T14 |
8467 |
8060 |
0 |
0 |
T15 |
494 |
94 |
0 |
0 |
T16 |
5016 |
4616 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
33 |
0 |
0 |
T13 |
3601 |
1 |
0 |
0 |
T35 |
4876 |
0 |
0 |
0 |
T40 |
1001 |
2 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T165 |
0 |
1 |
0 |
0 |
T167 |
0 |
1 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T206 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 45 | 97.83 |
CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 31 | 96.88 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
58 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
0 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
| Total | Covered | Percent |
Conditions | 21 | 19 | 90.48 |
Logical | 21 | 19 | 90.48 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
-1- | Status | Tests |
0 | Covered | T6,T7,T2 |
1 | Covered | T5,T6,T7 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T2 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T12,T35,T40 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T5,T6,T7 |
VC_COV_UNR |
1 | Covered | T12,T35,T40 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T12,T35,T40 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9,T10,T12 |
1 | 0 | Covered | T6,T7,T2 |
1 | 1 | Covered | T12,T35,T40 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T12,T35,T40 |
0 | 1 | Covered | T40 |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T12,T35,T40 |
0 | 1 | Covered | T40,T47,T45 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T12,T35,T40 |
1 | - | Covered | T40,T47,T45 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T12,T35,T40 |
DetectSt |
168 |
Covered |
T12,T35,T40 |
IdleSt |
163 |
Covered |
T5,T6,T7 |
StableSt |
191 |
Covered |
T12,T35,T40 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T12,T35,T40 |
DebounceSt->IdleSt |
163 |
Covered |
T93,T87,T88 |
DetectSt->IdleSt |
186 |
Covered |
T40 |
DetectSt->StableSt |
191 |
Covered |
T12,T35,T40 |
IdleSt->DebounceSt |
148 |
Covered |
T12,T35,T40 |
StableSt->IdleSt |
206 |
Covered |
T35,T40,T47 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
| Line No. | Total | Covered | Percent |
Branches |
|
20 |
19 |
95.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
10 |
9 |
90.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T12,T35,T40 |
|
0 |
1 |
Covered |
T12,T35,T40 |
|
0 |
0 |
Excluded |
T5,T6,T7 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T12,T35,T40 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T12,T35,T40 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T5,T6,T7 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T87,T88 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T12,T35,T40 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Not Covered |
|
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T12,T35,T40 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T40 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T12,T35,T40 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Excluded |
|
VC_COV_UNR |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T40,T47,T45 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T12,T35,T40 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
78 |
0 |
0 |
T12 |
1025 |
2 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T35 |
4876 |
2 |
0 |
0 |
T40 |
1001 |
4 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
4 |
0 |
0 |
T47 |
0 |
2 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T143 |
0 |
6 |
0 |
0 |
T152 |
0 |
4 |
0 |
0 |
T165 |
0 |
2 |
0 |
0 |
T168 |
0 |
2 |
0 |
0 |
T180 |
0 |
2 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
58267 |
0 |
0 |
T12 |
1025 |
60 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T35 |
4876 |
59 |
0 |
0 |
T40 |
1001 |
148 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
150 |
0 |
0 |
T47 |
0 |
49 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T93 |
0 |
10502 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T143 |
0 |
122 |
0 |
0 |
T152 |
0 |
162 |
0 |
0 |
T165 |
0 |
12 |
0 |
0 |
T168 |
0 |
62 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8487361 |
0 |
0 |
T1 |
564982 |
564581 |
0 |
0 |
T2 |
21127 |
20688 |
0 |
0 |
T3 |
825 |
424 |
0 |
0 |
T4 |
25465 |
23796 |
0 |
0 |
T5 |
738 |
337 |
0 |
0 |
T6 |
435 |
34 |
0 |
0 |
T7 |
437 |
36 |
0 |
0 |
T14 |
8467 |
8058 |
0 |
0 |
T15 |
494 |
93 |
0 |
0 |
T16 |
5016 |
4615 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
1 |
0 |
0 |
T25 |
1119 |
0 |
0 |
0 |
T30 |
676 |
0 |
0 |
0 |
T36 |
20520 |
0 |
0 |
0 |
T40 |
1001 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T62 |
2265 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T78 |
6020 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
48701 |
0 |
0 |
T12 |
1025 |
39 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T35 |
4876 |
40 |
0 |
0 |
T40 |
1001 |
18 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
90 |
0 |
0 |
T47 |
0 |
90 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T143 |
0 |
296 |
0 |
0 |
T152 |
0 |
83 |
0 |
0 |
T165 |
0 |
53 |
0 |
0 |
T168 |
0 |
68 |
0 |
0 |
T180 |
0 |
45790 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
37 |
0 |
0 |
T12 |
1025 |
1 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T35 |
4876 |
1 |
0 |
0 |
T40 |
1001 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T143 |
0 |
3 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T165 |
0 |
1 |
0 |
0 |
T168 |
0 |
1 |
0 |
0 |
T180 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8102638 |
0 |
0 |
T1 |
564982 |
564581 |
0 |
0 |
T2 |
21127 |
20688 |
0 |
0 |
T3 |
825 |
424 |
0 |
0 |
T4 |
25465 |
23796 |
0 |
0 |
T5 |
738 |
337 |
0 |
0 |
T6 |
435 |
34 |
0 |
0 |
T7 |
437 |
36 |
0 |
0 |
T14 |
8467 |
8058 |
0 |
0 |
T15 |
494 |
93 |
0 |
0 |
T16 |
5016 |
4615 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8104924 |
0 |
0 |
T1 |
564982 |
564582 |
0 |
0 |
T2 |
21127 |
20694 |
0 |
0 |
T3 |
825 |
425 |
0 |
0 |
T4 |
25465 |
23808 |
0 |
0 |
T5 |
738 |
338 |
0 |
0 |
T6 |
435 |
35 |
0 |
0 |
T7 |
437 |
37 |
0 |
0 |
T14 |
8467 |
8060 |
0 |
0 |
T15 |
494 |
94 |
0 |
0 |
T16 |
5016 |
4616 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
41 |
0 |
0 |
T12 |
1025 |
1 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T35 |
4876 |
1 |
0 |
0 |
T40 |
1001 |
2 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T93 |
0 |
1 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T143 |
0 |
3 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T165 |
0 |
1 |
0 |
0 |
T168 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
38 |
0 |
0 |
T12 |
1025 |
1 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T35 |
4876 |
1 |
0 |
0 |
T40 |
1001 |
2 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T143 |
0 |
3 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T165 |
0 |
1 |
0 |
0 |
T168 |
0 |
1 |
0 |
0 |
T180 |
0 |
1 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
37 |
0 |
0 |
T12 |
1025 |
1 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T35 |
4876 |
1 |
0 |
0 |
T40 |
1001 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T143 |
0 |
3 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T165 |
0 |
1 |
0 |
0 |
T168 |
0 |
1 |
0 |
0 |
T180 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
37 |
0 |
0 |
T12 |
1025 |
1 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T35 |
4876 |
1 |
0 |
0 |
T40 |
1001 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T143 |
0 |
3 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T165 |
0 |
1 |
0 |
0 |
T168 |
0 |
1 |
0 |
0 |
T180 |
0 |
1 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
48643 |
0 |
0 |
T12 |
1025 |
37 |
0 |
0 |
T13 |
3601 |
0 |
0 |
0 |
T35 |
4876 |
38 |
0 |
0 |
T40 |
1001 |
17 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
87 |
0 |
0 |
T47 |
0 |
89 |
0 |
0 |
T51 |
9191 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T70 |
523 |
0 |
0 |
0 |
T77 |
423 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T143 |
0 |
292 |
0 |
0 |
T152 |
0 |
80 |
0 |
0 |
T165 |
0 |
51 |
0 |
0 |
T168 |
0 |
66 |
0 |
0 |
T180 |
0 |
45789 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
6158 |
0 |
0 |
T1 |
564982 |
0 |
0 |
0 |
T2 |
21127 |
32 |
0 |
0 |
T3 |
825 |
0 |
0 |
0 |
T4 |
25465 |
10 |
0 |
0 |
T6 |
435 |
1 |
0 |
0 |
T7 |
437 |
5 |
0 |
0 |
T8 |
0 |
12 |
0 |
0 |
T14 |
8467 |
28 |
0 |
0 |
T15 |
494 |
7 |
0 |
0 |
T16 |
5016 |
29 |
0 |
0 |
T17 |
457 |
4 |
0 |
0 |
T50 |
0 |
25 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
8489780 |
0 |
0 |
T1 |
564982 |
564582 |
0 |
0 |
T2 |
21127 |
20694 |
0 |
0 |
T3 |
825 |
425 |
0 |
0 |
T4 |
25465 |
23808 |
0 |
0 |
T5 |
738 |
338 |
0 |
0 |
T6 |
435 |
35 |
0 |
0 |
T7 |
437 |
37 |
0 |
0 |
T14 |
8467 |
8060 |
0 |
0 |
T15 |
494 |
94 |
0 |
0 |
T16 |
5016 |
4616 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9133666 |
16 |
0 |
0 |
T25 |
1119 |
0 |
0 |
0 |
T30 |
676 |
0 |
0 |
0 |
T36 |
20520 |
0 |
0 |
0 |
T40 |
1001 |
1 |
0 |
0 |
T44 |
994 |
0 |
0 |
0 |
T45 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T62 |
2265 |
0 |
0 |
0 |
T66 |
491 |
0 |
0 |
0 |
T78 |
6020 |
0 |
0 |
0 |
T111 |
448 |
0 |
0 |
0 |
T143 |
0 |
2 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T180 |
0 |
1 |
0 |
0 |
T181 |
959 |
0 |
0 |
0 |
T194 |
0 |
1 |
0 |
0 |
T213 |
0 |
1 |
0 |
0 |
T214 |
0 |
1 |
0 |
0 |
T215 |
0 |
1 |
0 |
0 |