Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T6,T7,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T6,T7,T2
1	1	Covered	T6,T7,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T41,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T10,T41,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T41,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T35,T41
1	0	Covered	T6,T7,T2
1	1	Covered	T10,T41,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T41,T47
0	1	Covered	T43,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T41,T47
0	1	Covered	T10,T42,T57
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T41,T47
1	-	Covered	T10,T42,T57

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T41,T47
DetectSt	168	Covered	T10,T41,T47
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T10,T41,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T41,T47
DebounceSt->IdleSt	163	Covered	T57,T216,T87
DetectSt->IdleSt	186	Covered	T43,T94
DetectSt->StableSt	191	Covered	T10,T41,T47
IdleSt->DebounceSt	148	Covered	T10,T41,T47
StableSt->IdleSt	206	Covered	T10,T42,T57

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T41,T47
0	1	Covered	T10,T41,T47
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T41,T47
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T41,T47
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T41,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T57,T216
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T41,T47
DetectSt	-	-	-	-	1	-	-	Covered	T43,T94
DetectSt	-	-	-	-	0	1	-	Covered	T10,T41,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T42,T57
StableSt	-	-	-	-	-	-	0	Covered	T10,T41,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	136	0	0
CntIncr_A	9133666	62619	0	0
CntNoWrap_A	9133666	8487303	0	0
DetectStDropOut_A	9133666	2	0	0
DetectedOut_A	9133666	131742	0	0
DetectedPulseOut_A	9133666	64	0	0
DisabledIdleSt_A	9133666	8224238	0	0
DisabledNoDetection_A	9133666	8226520	0	0
EnterDebounceSt_A	9133666	70	0	0
EnterDetectSt_A	9133666	66	0	0
EnterStableSt_A	9133666	64	0	0
PulseIsPulse_A	9133666	64	0	0
StayInStableSt	9133666	131648	0	0
gen_high_level_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	136	0	0
T10	898	2	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T43	0	2	0	0
T45	0	2	0	0
T47	0	2	0	0
T57	0	3	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T94	0	2	0	0
T114	0	2	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	62619	0	0
T10	898	84	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	35	0	0
T42	0	146	0	0
T43	0	32	0	0
T45	0	55	0	0
T47	0	49	0	0
T57	0	180	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T94	0	96	0	0
T114	0	67	0	0
T170	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8487303	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	2	0	0
T38	16041	0	0	0
T43	10802	1	0	0
T68	491	0	0	0
T80	6472	0	0	0
T94	641	1	0	0
T217	406	0	0	0
T218	879	0	0	0
T219	192051	0	0	0
T220	759	0	0	0
T221	421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	131742	0	0
T10	898	60	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	43	0	0
T42	0	90	0	0
T45	0	30	0	0
T47	0	101	0	0
T57	0	22	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T114	0	262	0	0
T156	0	125795	0	0
T170	0	59	0	0
T209	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	64	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T114	0	1	0	0
T156	0	1	0	0
T170	0	1	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8224238	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8226520	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	70	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T57	0	2	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T94	0	1	0	0
T114	0	1	0	0
T170	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	66	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T94	0	1	0	0
T114	0	1	0	0
T170	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	64	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T114	0	1	0	0
T156	0	1	0	0
T170	0	1	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	64	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T114	0	1	0	0
T156	0	1	0	0
T170	0	1	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	131648	0	0
T10	898	59	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T41	0	41	0	0
T42	0	87	0	0
T45	0	29	0	0
T47	0	99	0	0
T57	0	21	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T114	0	260	0	0
T156	0	125794	0	0
T170	0	58	0	0
T209	0	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	34	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T42	0	1	0	0
T45	0	1	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T206	0	1	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T2
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T44,T45,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T44,T45,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T44,T45,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T44,T47,T114
1	0	Covered	T6,T7,T2
1	1	Covered	T44,T45,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T44,T45,T46
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T45,T46
0	1	Covered	T45,T93,T150
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T44,T45,T46
1	-	Covered	T45,T93,T150

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T44,T45,T46
DetectSt	168	Covered	T44,T45,T46
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T44,T45,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T44,T45,T46
DebounceSt->IdleSt	163	Covered	T206,T168,T87
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T44,T45,T46
IdleSt->DebounceSt	148	Covered	T44,T45,T46
StableSt->IdleSt	206	Covered	T45,T93,T150

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T44,T45,T46
0	1	Covered	T44,T45,T46
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T44,T45,T46
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T44,T45,T46
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T44,T45,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T206,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T44,T45,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T44,T45,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T93,T150
StableSt	-	-	-	-	-	-	0	Covered	T44,T45,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	82	0	0
CntIncr_A	9133666	150777	0	0
CntNoWrap_A	9133666	8487357	0	0
DetectStDropOut_A	9133666	0	0	0
DetectedOut_A	9133666	2112	0	0
DetectedPulseOut_A	9133666	39	0	0
DisabledIdleSt_A	9133666	7843049	0	0
DisabledNoDetection_A	9133666	7845338	0	0
EnterDebounceSt_A	9133666	43	0	0
EnterDetectSt_A	9133666	39	0	0
EnterStableSt_A	9133666	39	0	0
PulseIsPulse_A	9133666	39	0	0
StayInStableSt	9133666	2058	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9133666	6148	0	0
gen_low_level_sva.LowLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	82	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T44	994	2	0	0
T45	0	4	0	0
T46	0	2	0	0
T59	26940	0	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T93	0	2	0	0
T138	450	0	0	0
T150	0	2	0	0
T156	0	2	0	0
T165	0	2	0	0
T168	0	1	0	0
T181	959	0	0	0
T206	0	1	0	0
T222	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	150777	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T44	994	64	0	0
T45	0	152	0	0
T46	0	28	0	0
T59	26940	0	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T93	0	42362	0	0
T138	450	0	0	0
T150	0	65	0	0
T156	0	58822	0	0
T165	0	12	0	0
T168	0	62	0	0
T181	959	0	0	0
T206	0	42	0	0
T222	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8487357	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	2112	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T44	994	39	0	0
T45	0	233	0	0
T46	0	135	0	0
T59	26940	0	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T93	0	43	0	0
T96	0	52	0	0
T138	450	0	0	0
T143	0	64	0	0
T150	0	10	0	0
T156	0	41	0	0
T165	0	40	0	0
T181	959	0	0	0
T222	0	127	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	39	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T44	994	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T59	26940	0	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T93	0	1	0	0
T96	0	1	0	0
T138	450	0	0	0
T143	0	1	0	0
T150	0	1	0	0
T156	0	1	0	0
T165	0	1	0	0
T181	959	0	0	0
T222	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	7843049	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	7845338	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	43	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T44	994	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T59	26940	0	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T93	0	1	0	0
T138	450	0	0	0
T150	0	1	0	0
T156	0	1	0	0
T165	0	1	0	0
T168	0	1	0	0
T181	959	0	0	0
T206	0	1	0	0
T222	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	39	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T44	994	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T59	26940	0	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T93	0	1	0	0
T96	0	1	0	0
T138	450	0	0	0
T143	0	1	0	0
T150	0	1	0	0
T156	0	1	0	0
T165	0	1	0	0
T181	959	0	0	0
T222	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	39	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T44	994	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T59	26940	0	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T93	0	1	0	0
T96	0	1	0	0
T138	450	0	0	0
T143	0	1	0	0
T150	0	1	0	0
T156	0	1	0	0
T165	0	1	0	0
T181	959	0	0	0
T222	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	39	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T44	994	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T59	26940	0	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T93	0	1	0	0
T96	0	1	0	0
T138	450	0	0	0
T143	0	1	0	0
T150	0	1	0	0
T156	0	1	0	0
T165	0	1	0	0
T181	959	0	0	0
T222	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	2058	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T44	994	37	0	0
T45	0	230	0	0
T46	0	133	0	0
T59	26940	0	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T93	0	42	0	0
T96	0	51	0	0
T138	450	0	0	0
T143	0	62	0	0
T150	0	9	0	0
T156	0	39	0	0
T165	0	39	0	0
T181	959	0	0	0
T222	0	124	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	6148	0	0
T1	564982	0	0	0
T2	21127	25	0	0
T3	825	0	0	0
T4	25465	14	0	0
T6	435	1	0	0
T7	437	3	0	0
T8	0	13	0	0
T14	8467	29	0	0
T15	494	7	0	0
T16	5016	25	0	0
T17	457	4	0	0
T50	0	24	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	24	0	0
T39	12084	0	0	0
T45	44207	1	0	0
T93	0	1	0	0
T96	0	1	0	0
T150	0	1	0	0
T153	0	1	0	0
T165	0	1	0	0
T194	0	3	0	0
T215	0	2	0	0
T222	0	1	0	0
T223	0	1	0	0
T224	422	0	0	0
T225	503	0	0	0
T226	32071	0	0	0
T227	947	0	0	0
T228	732	0	0	0
T229	433	0	0	0
T230	459	0	0	0
T231	502	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T6,T7,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T6,T7,T2
1	1	Covered	T6,T7,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T9,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T12
1	0	Covered	T6,T7,T2
1	1	Covered	T9,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T13
0	1	Covered	T9,T45,T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T13
0	1	Covered	T10,T12,T13
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T12,T13
1	-	Covered	T10,T12,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T10,T12
DetectSt	168	Covered	T9,T10,T12
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T10,T12,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T12
DebounceSt->IdleSt	163	Covered	T93,T87,T88
DetectSt->IdleSt	186	Covered	T9,T45,T154
DetectSt->StableSt	191	Covered	T10,T12,T13
IdleSt->DebounceSt	148	Covered	T9,T10,T12
StableSt->IdleSt	206	Covered	T10,T12,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T10,T12
0	1	Covered	T9,T10,T12
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T12
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T12
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T10,T12
DetectSt	-	-	-	-	1	-	-	Covered	T9,T45,T154
DetectSt	-	-	-	-	0	1	-	Covered	T10,T12,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T12,T13
StableSt	-	-	-	-	-	-	0	Covered	T10,T12,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	122	0	0
CntIncr_A	9133666	115600	0	0
CntNoWrap_A	9133666	8487317	0	0
DetectStDropOut_A	9133666	3	0	0
DetectedOut_A	9133666	15925	0	0
DetectedPulseOut_A	9133666	57	0	0
DisabledIdleSt_A	9133666	8053958	0	0
DisabledNoDetection_A	9133666	8056240	0	0
EnterDebounceSt_A	9133666	63	0	0
EnterDetectSt_A	9133666	60	0	0
EnterStableSt_A	9133666	57	0	0
PulseIsPulse_A	9133666	57	0	0
StayInStableSt	9133666	15849	0	0
gen_high_level_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	122	0	0
T9	2955	2	0	0
T10	898	2	0	0
T11	22238	0	0	0
T12	1025	4	0	0
T13	3601	2	0	0
T27	1322	0	0	0
T29	525	0	0	0
T42	0	2	0	0
T45	0	8	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	2	0	0
T114	0	2	0	0
T151	0	2	0	0
T156	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	115600	0	0
T9	2955	25	0	0
T10	898	84	0	0
T11	22238	0	0	0
T12	1025	120	0	0
T13	3601	855	0	0
T27	1322	0	0	0
T29	525	0	0	0
T42	0	73	0	0
T45	0	188	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	52864	0	0
T114	0	67	0	0
T151	0	21	0	0
T156	0	58822	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8487317	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	3	0	0
T9	2955	1	0	0
T10	898	0	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T45	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T154	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	15925	0	0
T10	898	128	0	0
T11	22238	0	0	0
T12	1025	199	0	0
T13	3601	41	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T42	0	582	0	0
T45	0	238	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	4754	0	0
T114	0	148	0	0
T151	0	15	0	0
T156	0	6215	0	0
T165	0	62	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	57	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	2	0	0
T13	3601	1	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T42	0	1	0	0
T45	0	3	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T114	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8053958	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8056240	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	63	0	0
T9	2955	1	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	2	0	0
T13	3601	1	0	0
T27	1322	0	0	0
T29	525	0	0	0
T42	0	1	0	0
T45	0	4	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	2	0	0
T114	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	60	0	0
T9	2955	1	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	2	0	0
T13	3601	1	0	0
T27	1322	0	0	0
T29	525	0	0	0
T42	0	1	0	0
T45	0	4	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T114	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	57	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	2	0	0
T13	3601	1	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T42	0	1	0	0
T45	0	3	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T114	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	57	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	2	0	0
T13	3601	1	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T42	0	1	0	0
T45	0	3	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T114	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	15849	0	0
T10	898	127	0	0
T11	22238	0	0	0
T12	1025	197	0	0
T13	3601	40	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T42	0	580	0	0
T45	0	234	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	4753	0	0
T114	0	147	0	0
T151	0	14	0	0
T156	0	6214	0	0
T165	0	61	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	38	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	2	0	0
T13	3601	1	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T45	0	2	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T114	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0
T165	0	1	0	0
T222	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T2
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T13,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T10,T13,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T13,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T35
1	0	Covered	T6,T7,T2
1	1	Covered	T10,T13,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T43
0	1	Covered	T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T43
0	1	Covered	T57,T45,T93
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T13,T43
1	-	Covered	T57,T45,T93

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T13,T43
DetectSt	168	Covered	T10,T13,T43
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T10,T13,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T13,T43
DebounceSt->IdleSt	163	Covered	T45,T170,T87
DetectSt->IdleSt	186	Covered	T154
DetectSt->StableSt	191	Covered	T10,T13,T43
IdleSt->DebounceSt	148	Covered	T10,T13,T43
StableSt->IdleSt	206	Covered	T43,T57,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T13,T43
0	1	Covered	T10,T13,T43
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T13,T43
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T13,T43
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T13,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T170
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T13,T43
DetectSt	-	-	-	-	1	-	-	Covered	T154
DetectSt	-	-	-	-	0	1	-	Covered	T10,T13,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T57,T45,T93
StableSt	-	-	-	-	-	-	0	Covered	T10,T13,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	85	0	0
CntIncr_A	9133666	149781	0	0
CntNoWrap_A	9133666	8487354	0	0
DetectStDropOut_A	9133666	1	0	0
DetectedOut_A	9133666	50491	0	0
DetectedPulseOut_A	9133666	39	0	0
DisabledIdleSt_A	9133666	7856369	0	0
DisabledNoDetection_A	9133666	7858651	0	0
EnterDebounceSt_A	9133666	46	0	0
EnterDetectSt_A	9133666	40	0	0
EnterStableSt_A	9133666	39	0	0
PulseIsPulse_A	9133666	39	0	0
StayInStableSt	9133666	50427	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9133666	6159	0	0
gen_low_level_sva.LowLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	85	0	0
T10	898	2	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	2	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T43	0	2	0	0
T45	0	7	0	0
T57	0	2	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	2	0	0
T151	0	2	0	0
T156	0	2	0	0
T166	0	2	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	149781	0	0
T10	898	84	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	855	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T43	0	39	0	0
T45	0	244	0	0
T57	0	90	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	42362	0	0
T151	0	21	0	0
T156	0	58822	0	0
T166	0	44	0	0
T170	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8487354	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	1	0	0
T147	2419	0	0	0
T154	5621	1	0	0
T157	618	0	0	0
T158	5591	0	0	0
T159	6218	0	0	0
T160	497	0	0	0
T161	11610	0	0	0
T162	503	0	0	0
T163	17887	0	0	0
T164	549	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	50491	0	0
T10	898	47	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	1325	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T43	0	37	0	0
T45	0	611	0	0
T57	0	40	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	44	0	0
T151	0	228	0	0
T156	0	42	0	0
T166	0	61	0	0
T222	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	39	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	1	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T43	0	1	0	0
T45	0	3	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0
T166	0	1	0	0
T222	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	7856369	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	7858651	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	46	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	1	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T43	0	1	0	0
T45	0	4	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0
T166	0	1	0	0
T170	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	40	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	1	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T43	0	1	0	0
T45	0	3	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0
T166	0	1	0	0
T222	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	39	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	1	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T43	0	1	0	0
T45	0	3	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0
T166	0	1	0	0
T222	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	39	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	1	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T43	0	1	0	0
T45	0	3	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0
T166	0	1	0	0
T222	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	50427	0	0
T10	898	45	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	1323	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T43	0	35	0	0
T45	0	606	0	0
T57	0	39	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T93	0	43	0	0
T151	0	226	0	0
T156	0	40	0	0
T166	0	59	0	0
T222	0	83	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	6159	0	0
T1	564982	0	0	0
T2	21127	28	0	0
T3	825	0	0	0
T4	25465	18	0	0
T6	435	1	0	0
T7	437	3	0	0
T8	0	13	0	0
T14	8467	26	0	0
T15	494	9	0	0
T16	5016	28	0	0
T17	457	7	0	0
T50	0	22	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	14	0	0
T45	0	1	0	0
T57	10924	1	0	0
T82	1782	0	0	0
T93	0	1	0	0
T112	4404	0	0	0
T113	66142	0	0	0
T114	824	0	0	0
T115	422	0	0	0
T116	162493	0	0	0
T117	796	0	0	0
T118	436	0	0	0
T119	426	0	0	0
T143	0	1	0	0
T146	0	1	0	0
T169	0	2	0	0
T180	0	1	0	0
T182	0	1	0	0
T214	0	1	0	0
T232	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T7,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T7,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T12,T40,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T12,T40,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T12,T40,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T40,T44
1	0	Covered	T5,T7,T1
1	1	Covered	T12,T40,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T40,T44
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T40,T44
0	1	Covered	T12,T40,T44
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T40,T44
1	-	Covered	T12,T40,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T40,T44
DetectSt	168	Covered	T12,T40,T44
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T12,T40,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T40,T44
DebounceSt->IdleSt	163	Covered	T63,T46,T93
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T12,T40,T44
IdleSt->DebounceSt	148	Covered	T12,T40,T44
StableSt->IdleSt	206	Covered	T12,T40,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T40,T44
0	1	Covered	T12,T40,T44
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T40,T44
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T40,T44
IdleSt	0	-	-	-	-	-	-	Covered	T5,T7,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T40,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T46,T166,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T40,T44
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T40,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T40,T44
StableSt	-	-	-	-	-	-	0	Covered	T12,T40,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	127	0	0
CntIncr_A	9133666	109960	0	0
CntNoWrap_A	9133666	8487312	0	0
DetectStDropOut_A	9133666	0	0	0
DetectedOut_A	9133666	75826	0	0
DetectedPulseOut_A	9133666	59	0	0
DisabledIdleSt_A	9133666	8087108	0	0
DisabledNoDetection_A	9133666	8089396	0	0
EnterDebounceSt_A	9133666	70	0	0
EnterDetectSt_A	9133666	59	0	0
EnterStableSt_A	9133666	59	0	0
PulseIsPulse_A	9133666	59	0	0
StayInStableSt	9133666	75747	0	0
gen_high_level_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	127	0	0
T12	1025	4	0	0
T13	3601	0	0	0
T35	4876	0	0	0
T40	1001	6	0	0
T41	0	2	0	0
T43	0	6	0	0
T44	994	4	0	0
T45	0	2	0	0
T46	0	3	0	0
T51	9191	0	0	0
T57	0	4	0	0
T66	491	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T111	448	0	0	0
T166	0	1	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	109960	0	0
T12	1025	120	0	0
T13	3601	0	0	0
T35	4876	0	0	0
T40	1001	222	0	0
T41	0	35	0	0
T43	0	110	0	0
T44	994	128	0	0
T45	0	39	0	0
T46	0	56	0	0
T51	9191	0	0	0
T57	0	180	0	0
T63	0	352	0	0
T66	491	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T111	448	0	0	0
T170	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8487312	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	75826	0	0
T12	1025	72	0	0
T13	3601	0	0	0
T35	4876	0	0	0
T40	1001	19	0	0
T41	0	2	0	0
T43	0	114	0	0
T44	994	227	0	0
T45	0	35	0	0
T46	0	20	0	0
T51	9191	0	0	0
T57	0	199	0	0
T66	491	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T111	448	0	0	0
T170	0	146	0	0
T209	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	59	0	0
T12	1025	2	0	0
T13	3601	0	0	0
T35	4876	0	0	0
T40	1001	3	0	0
T41	0	1	0	0
T43	0	3	0	0
T44	994	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	9191	0	0	0
T57	0	2	0	0
T66	491	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T111	448	0	0	0
T170	0	1	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8087108	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8089396	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	70	0	0
T12	1025	2	0	0
T13	3601	0	0	0
T35	4876	0	0	0
T40	1001	3	0	0
T41	0	1	0	0
T43	0	3	0	0
T44	994	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T51	9191	0	0	0
T57	0	2	0	0
T63	0	1	0	0
T66	491	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T111	448	0	0	0
T170	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	59	0	0
T12	1025	2	0	0
T13	3601	0	0	0
T35	4876	0	0	0
T40	1001	3	0	0
T41	0	1	0	0
T43	0	3	0	0
T44	994	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	9191	0	0	0
T57	0	2	0	0
T66	491	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T111	448	0	0	0
T170	0	1	0	0
T209	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	59	0	0
T12	1025	2	0	0
T13	3601	0	0	0
T35	4876	0	0	0
T40	1001	3	0	0
T41	0	1	0	0
T43	0	3	0	0
T44	994	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	9191	0	0	0
T57	0	2	0	0
T66	491	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T111	448	0	0	0
T170	0	1	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	59	0	0
T12	1025	2	0	0
T13	3601	0	0	0
T35	4876	0	0	0
T40	1001	3	0	0
T41	0	1	0	0
T43	0	3	0	0
T44	994	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	9191	0	0	0
T57	0	2	0	0
T66	491	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T111	448	0	0	0
T170	0	1	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	75747	0	0
T12	1025	70	0	0
T13	3601	0	0	0
T35	4876	0	0	0
T40	1001	16	0	0
T41	0	1	0	0
T43	0	109	0	0
T44	994	225	0	0
T45	0	34	0	0
T46	0	19	0	0
T51	9191	0	0	0
T57	0	196	0	0
T66	491	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T111	448	0	0	0
T170	0	145	0	0
T209	0	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	39	0	0
T12	1025	2	0	0
T13	3601	0	0	0
T35	4876	0	0	0
T40	1001	3	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	994	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	9191	0	0	0
T57	0	1	0	0
T66	491	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T111	448	0	0	0
T170	0	1	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T7,T1
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T1
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T40,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T10,T35,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T40,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T35,T40
1	0	Covered	T5,T7,T1
1	1	Covered	T10,T35,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T42
0	1	Covered	T10
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T42
0	1	Covered	T40,T57,T46
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T41,T42
1	-	Covered	T40,T57,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T35,T40
DetectSt	168	Covered	T10,T40,T41
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T40,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T40,T41
DebounceSt->IdleSt	163	Covered	T35,T87,T88
DetectSt->IdleSt	186	Covered	T10
DetectSt->StableSt	191	Covered	T40,T41,T42
IdleSt->DebounceSt	148	Covered	T10,T35,T40
StableSt->IdleSt	206	Covered	T40,T42,T57

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T40,T41
0	1	Covered	T10,T35,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T40,T41
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T35,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T40,T41
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T35,T40
DetectSt	-	-	-	-	1	-	-	Covered	T10
DetectSt	-	-	-	-	0	1	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T57,T46
StableSt	-	-	-	-	-	-	0	Covered	T40,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	96	0	0
CntIncr_A	9133666	50585	0	0
CntNoWrap_A	9133666	8487343	0	0
DetectStDropOut_A	9133666	1	0	0
DetectedOut_A	9133666	3177	0	0
DetectedPulseOut_A	9133666	46	0	0
DisabledIdleSt_A	9133666	7841692	0	0
DisabledNoDetection_A	9133666	7843974	0	0
EnterDebounceSt_A	9133666	50	0	0
EnterDetectSt_A	9133666	47	0	0
EnterStableSt_A	9133666	46	0	0
PulseIsPulse_A	9133666	46	0	0
StayInStableSt	9133666	3104	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9133666	6893	0	0
gen_low_level_sva.LowLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	96	0	0
T10	898	2	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T40	0	6	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	4	0	0
T46	0	4	0	0
T57	0	2	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T114	0	2	0	0
T166	0	2	0	0
T209	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	50585	0	0
T10	898	84	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	27	0	0
T40	0	222	0	0
T41	0	35	0	0
T42	0	73	0	0
T45	0	136	0	0
T46	0	56	0	0
T57	0	90	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T114	0	67	0	0
T166	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8487343	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	1	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	3177	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T40	1001	124	0	0
T41	0	42	0	0
T42	0	45	0	0
T44	994	0	0	0
T45	0	416	0	0
T46	0	94	0	0
T57	0	1	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T111	448	0	0	0
T114	0	154	0	0
T166	0	47	0	0
T181	959	0	0	0
T193	0	171	0	0
T209	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	46	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T40	1001	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	994	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T57	0	1	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T111	448	0	0	0
T114	0	1	0	0
T166	0	1	0	0
T181	959	0	0	0
T193	0	2	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	7841692	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	7843974	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	50	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	1	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T114	0	1	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	47	0	0
T10	898	1	0	0
T11	22238	0	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T27	1322	0	0	0
T29	525	0	0	0
T35	4876	0	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T57	0	1	0	0
T58	691	0	0	0
T70	523	0	0	0
T77	423	0	0	0
T114	0	1	0	0
T166	0	1	0	0
T209	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	46	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T40	1001	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	994	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T57	0	1	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T111	448	0	0	0
T114	0	1	0	0
T166	0	1	0	0
T181	959	0	0	0
T193	0	2	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	46	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T40	1001	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	994	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T57	0	1	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T111	448	0	0	0
T114	0	1	0	0
T166	0	1	0	0
T181	959	0	0	0
T193	0	2	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	3104	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T40	1001	120	0	0
T41	0	40	0	0
T42	0	43	0	0
T44	994	0	0	0
T45	0	412	0	0
T46	0	91	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T111	448	0	0	0
T114	0	152	0	0
T166	0	45	0	0
T181	959	0	0	0
T193	0	168	0	0
T209	0	44	0	0
T222	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	6893	0	0
T1	564982	7	0	0
T2	21127	22	0	0
T3	825	4	0	0
T4	25465	16	0	0
T5	738	3	0	0
T6	435	0	0	0
T7	437	5	0	0
T14	8467	31	0	0
T15	494	9	0	0
T16	5016	29	0	0
T17	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	19	0	0
T25	1119	0	0	0
T30	676	0	0	0
T36	20520	0	0	0
T40	1001	2	0	0
T44	994	0	0	0
T46	0	1	0	0
T57	0	1	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T111	448	0	0	0
T143	0	1	0	0
T152	0	2	0	0
T181	959	0	0	0
T193	0	1	0	0
T194	0	1	0	0
T207	0	1	0	0
T213	0	1	0	0
T216	0	1	0	0