Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T14,T16
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T14,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T14,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T14,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T49
1	1	Covered	T2,T14,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T14,T50
0	1	Covered	T16,T50,T78
1	0	Covered	T49,T79,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T14,T48
0	1	Covered	T2,T14,T81
1	0	Covered	T91,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T14,T48
1	-	Covered	T2,T14,T81

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T14,T16
DetectSt	168	Covered	T2,T14,T16
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T14,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T14,T16
DebounceSt->IdleSt	163	Covered	T16,T233,T234
DetectSt->IdleSt	186	Covered	T16,T50,T78
DetectSt->StableSt	191	Covered	T2,T14,T48
IdleSt->DebounceSt	148	Covered	T2,T14,T16
StableSt->IdleSt	206	Covered	T2,T14,T81

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T14,T16
0	1	Covered	T2,T14,T16
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T14,T16
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T14,T16
IdleSt	0	-	-	-	-	-	-	Covered	T2,T14,T16
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T14,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T233,T234
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T14,T16
DetectSt	-	-	-	-	1	-	-	Covered	T16,T50,T78
DetectSt	-	-	-	-	0	1	-	Covered	T2,T14,T48
DetectSt	-	-	-	-	0	0	-	Covered	T2,T14,T50
StableSt	-	-	-	-	-	-	1	Covered	T2,T14,T81
StableSt	-	-	-	-	-	-	0	Covered	T2,T14,T48
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	3070	0	0
CntIncr_A	9133666	107679	0	0
CntNoWrap_A	9133666	8484369	0	0
DetectStDropOut_A	9133666	482	0	0
DetectedOut_A	9133666	71417	0	0
DetectedPulseOut_A	9133666	847	0	0
DisabledIdleSt_A	9133666	8033659	0	0
DisabledNoDetection_A	9133666	8035802	0	0
EnterDebounceSt_A	9133666	1552	0	0
EnterDetectSt_A	9133666	1518	0	0
EnterStableSt_A	9133666	847	0	0
PulseIsPulse_A	9133666	847	0	0
StayInStableSt	9133666	70464	0	0
gen_high_event_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_high_level_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	730	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	3070	0	0
T2	21127	58	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	60	0	0
T15	494	0	0	0
T16	5016	14	0	0
T17	457	0	0	0
T18	878	0	0	0
T48	0	2	0	0
T49	0	26	0	0
T50	5366	24	0	0
T78	0	58	0	0
T79	0	10	0	0
T80	0	28	0	0
T81	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	107679	0	0
T2	21127	2465	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	990	0	0
T15	494	0	0	0
T16	5016	637	0	0
T17	457	0	0	0
T18	878	0	0	0
T48	0	21	0	0
T49	0	702	0	0
T50	5366	655	0	0
T78	0	1967	0	0
T79	0	269	0	0
T80	0	748	0	0
T81	0	950	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8484369	0	0
T1	564982	564581	0	0
T2	21127	20630	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	7998	0	0
T15	494	93	0	0
T16	5016	4601	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	482	0	0
T8	19601	0	0	0
T16	5016	1	0	0
T17	457	0	0	0
T18	878	0	0	0
T26	493	0	0	0
T28	506	0	0	0
T49	0	7	0	0
T50	5366	12	0	0
T61	627	0	0	0
T69	402	0	0	0
T75	402	0	0	0
T78	0	29	0	0
T79	0	4	0	0
T99	0	5	0	0
T101	0	12	0	0
T102	0	5	0	0
T235	0	10	0	0
T236	0	27	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	71417	0	0
T2	21127	2889	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	1650	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	53	0	0
T48	0	47	0	0
T50	5366	0	0	0
T81	0	1980	0	0
T226	0	622	0	0
T230	0	34	0	0
T237	0	1032	0	0
T238	0	1977	0	0
T239	0	2955	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	847	0	0
T2	21127	29	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	30	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	10	0	0
T48	0	1	0	0
T50	5366	0	0	0
T81	0	25	0	0
T226	0	8	0	0
T230	0	1	0	0
T237	0	19	0	0
T238	0	15	0	0
T239	0	35	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8033659	0	0
T1	564982	564581	0	0
T2	21127	12584	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	4160	0	0
T15	494	93	0	0
T16	5016	2014	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8035802	0	0
T1	564982	564582	0	0
T2	21127	12587	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	4161	0	0
T15	494	94	0	0
T16	5016	2014	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	1552	0	0
T2	21127	29	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	30	0	0
T15	494	0	0	0
T16	5016	13	0	0
T17	457	0	0	0
T18	878	0	0	0
T48	0	1	0	0
T49	0	13	0	0
T50	5366	12	0	0
T78	0	29	0	0
T79	0	5	0	0
T80	0	14	0	0
T81	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	1518	0	0
T2	21127	29	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	30	0	0
T15	494	0	0	0
T16	5016	1	0	0
T17	457	0	0	0
T18	878	0	0	0
T48	0	1	0	0
T49	0	13	0	0
T50	5366	12	0	0
T78	0	29	0	0
T79	0	5	0	0
T80	0	14	0	0
T81	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	847	0	0
T2	21127	29	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	30	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	10	0	0
T48	0	1	0	0
T50	5366	0	0	0
T81	0	25	0	0
T226	0	8	0	0
T230	0	1	0	0
T237	0	19	0	0
T238	0	15	0	0
T239	0	35	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	847	0	0
T2	21127	29	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	30	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	10	0	0
T48	0	1	0	0
T50	5366	0	0	0
T81	0	25	0	0
T226	0	8	0	0
T230	0	1	0	0
T237	0	19	0	0
T238	0	15	0	0
T239	0	35	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	70464	0	0
T2	21127	2858	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	1620	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	43	0	0
T48	0	45	0	0
T50	5366	0	0	0
T81	0	1953	0	0
T226	0	614	0	0
T230	0	32	0	0
T237	0	1013	0	0
T238	0	1959	0	0
T239	0	2916	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	730	0	0
T2	21127	27	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	30	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	10	0	0
T50	5366	0	0	0
T81	0	23	0	0
T226	0	8	0	0
T237	0	19	0	0
T238	0	12	0	0
T239	0	31	0	0
T240	0	5	0	0
T241	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T2,T4
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T4
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T6,T2,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T6,T2,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T4
1	0	Covered	T2,T4,T14
1	1	Covered	T6,T2,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T11
0	1	Covered	T11,T51,T45
1	0	Covered	T87,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T35
0	1	Covered	T4,T35,T36
1	0	Covered	T89,T87

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T35
1	-	Covered	T4,T35,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T2,T4
DetectSt	168	Covered	T2,T4,T11
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T4,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T11
DebounceSt->IdleSt	163	Covered	T6,T4,T9
DetectSt->IdleSt	186	Covered	T11,T51,T45
DetectSt->StableSt	191	Covered	T2,T4,T35
IdleSt->DebounceSt	148	Covered	T6,T2,T4
StableSt->IdleSt	206	Covered	T2,T4,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T2,T4
0	1	Covered	T6,T2,T4
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T11
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T2,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T4,T9
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T2,T4
DetectSt	-	-	-	-	1	-	-	Covered	T11,T51,T45
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T35
DetectSt	-	-	-	-	0	0	-	Covered	T2,T4,T11
StableSt	-	-	-	-	-	-	1	Covered	T4,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	849	0	0
CntIncr_A	9133666	41234	0	0
CntNoWrap_A	9133666	8486590	0	0
DetectStDropOut_A	9133666	58	0	0
DetectedOut_A	9133666	13120	0	0
DetectedPulseOut_A	9133666	318	0	0
DisabledIdleSt_A	9133666	8140549	0	0
DisabledNoDetection_A	9133666	8142190	0	0
EnterDebounceSt_A	9133666	469	0	0
EnterDetectSt_A	9133666	380	0	0
EnterStableSt_A	9133666	318	0	0
PulseIsPulse_A	9133666	318	0	0
StayInStableSt	9133666	12777	0	0
gen_high_level_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	289	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	849	0	0
T1	564982	0	0	0
T2	21127	4	0	0
T3	825	0	0	0
T4	25465	7	0	0
T6	435	1	0	0
T7	437	0	0	0
T9	0	1	0	0
T11	0	6	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T51	0	7	0	0
T59	0	6	0	0
T60	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	41234	0	0
T1	564982	0	0	0
T2	21127	192	0	0
T3	825	0	0	0
T4	25465	254	0	0
T6	435	20	0	0
T7	437	0	0	0
T9	0	20	0	0
T11	0	298	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T35	0	25	0	0
T36	0	89	0	0
T51	0	342	0	0
T59	0	309	0	0
T60	0	346	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8486590	0	0
T1	564982	564581	0	0
T2	21127	20684	0	0
T3	825	424	0	0
T4	25465	23789	0	0
T5	738	337	0	0
T6	435	33	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	58	0	0
T11	22238	3	0	0
T12	1025	0	0	0
T13	3601	0	0	0
T35	4876	0	0	0
T40	1001	0	0	0
T44	994	0	0	0
T45	0	2	0	0
T51	9191	3	0	0
T70	523	0	0	0
T77	423	0	0	0
T100	0	1	0	0
T103	0	3	0	0
T104	0	6	0	0
T105	0	6	0	0
T106	0	1	0	0
T109	0	7	0	0
T110	0	7	0	0
T111	448	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	13120	0	0
T2	21127	99	0	0
T3	825	0	0	0
T4	25465	16	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T35	0	3	0	0
T36	0	5	0	0
T37	0	50	0	0
T43	0	5	0	0
T50	5366	0	0	0
T59	0	172	0	0
T60	0	8	0	0
T63	0	3	0	0
T120	0	254	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	318	0	0
T2	21127	2	0	0
T3	825	0	0	0
T4	25465	3	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T43	0	1	0	0
T50	5366	0	0	0
T59	0	3	0	0
T60	0	2	0	0
T63	0	1	0	0
T120	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8140549	0	0
T1	564982	564581	0	0
T2	21127	17801	0	0
T3	825	424	0	0
T4	25465	20528	0	0
T5	738	337	0	0
T6	435	4	0	0
T7	437	36	0	0
T14	8467	6408	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8142190	0	0
T1	564982	564582	0	0
T2	21127	17805	0	0
T3	825	425	0	0
T4	25465	20529	0	0
T5	738	338	0	0
T6	435	4	0	0
T7	437	37	0	0
T14	8467	6410	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	469	0	0
T1	564982	0	0	0
T2	21127	2	0	0
T3	825	0	0	0
T4	25465	4	0	0
T6	435	1	0	0
T7	437	0	0	0
T9	0	1	0	0
T11	0	3	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T51	0	4	0	0
T59	0	3	0	0
T60	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	380	0	0
T2	21127	2	0	0
T3	825	0	0	0
T4	25465	3	0	0
T8	19601	0	0	0
T11	0	3	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T50	5366	0	0	0
T51	0	3	0	0
T59	0	3	0	0
T60	0	2	0	0
T63	0	1	0	0
T120	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	318	0	0
T2	21127	2	0	0
T3	825	0	0	0
T4	25465	3	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T43	0	1	0	0
T50	5366	0	0	0
T59	0	3	0	0
T60	0	2	0	0
T63	0	1	0	0
T120	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	318	0	0
T2	21127	2	0	0
T3	825	0	0	0
T4	25465	3	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T43	0	1	0	0
T50	5366	0	0	0
T59	0	3	0	0
T60	0	2	0	0
T63	0	1	0	0
T120	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	12777	0	0
T2	21127	95	0	0
T3	825	0	0	0
T4	25465	13	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T35	0	2	0	0
T36	0	4	0	0
T37	0	49	0	0
T43	0	4	0	0
T50	5366	0	0	0
T59	0	169	0	0
T60	0	6	0	0
T63	0	2	0	0
T120	0	246	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	289	0	0
T4	25465	3	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T26	493	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	0	1	0	0
T50	5366	0	0	0
T59	0	3	0	0
T60	0	2	0	0
T61	627	0	0	0
T63	0	1	0	0
T120	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T14,T16
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T14,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T14,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T14,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T49
1	1	Covered	T2,T14,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T14,T50
0	1	Covered	T16,T50,T78
1	0	Covered	T79,T80,T238

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T14,T49
0	1	Covered	T2,T14,T49
1	0	Covered	T90,T242

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T14,T49
1	-	Covered	T2,T14,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T14,T16
DetectSt	168	Covered	T2,T14,T16
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T14,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T14,T16
DebounceSt->IdleSt	163	Covered	T16,T233,T234
DetectSt->IdleSt	186	Covered	T16,T50,T78
DetectSt->StableSt	191	Covered	T2,T14,T49
IdleSt->DebounceSt	148	Covered	T2,T14,T16
StableSt->IdleSt	206	Covered	T2,T14,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T14,T16
0	1	Covered	T2,T14,T16
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T14,T16
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T14,T16
IdleSt	0	-	-	-	-	-	-	Covered	T2,T14,T16
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T14,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T233,T234
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T14,T16
DetectSt	-	-	-	-	1	-	-	Covered	T16,T50,T78
DetectSt	-	-	-	-	0	1	-	Covered	T2,T14,T49
DetectSt	-	-	-	-	0	0	-	Covered	T2,T14,T50
StableSt	-	-	-	-	-	-	1	Covered	T2,T14,T49
StableSt	-	-	-	-	-	-	0	Covered	T2,T14,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	3185	0	0
CntIncr_A	9133666	102534	0	0
CntNoWrap_A	9133666	8484254	0	0
DetectStDropOut_A	9133666	455	0	0
DetectedOut_A	9133666	67080	0	0
DetectedPulseOut_A	9133666	821	0	0
DisabledIdleSt_A	9133666	8036006	0	0
DisabledNoDetection_A	9133666	8038129	0	0
EnterDebounceSt_A	9133666	1608	0	0
EnterDetectSt_A	9133666	1579	0	0
EnterStableSt_A	9133666	821	0	0
PulseIsPulse_A	9133666	821	0	0
StayInStableSt	9133666	66132	0	0
gen_high_event_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_high_level_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	690	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	3185	0	0
T2	21127	22	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	38	0	0
T15	494	0	0	0
T16	5016	12	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	38	0	0
T49	0	10	0	0
T50	5366	14	0	0
T78	0	34	0	0
T79	0	24	0	0
T80	0	34	0	0
T81	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	102534	0	0
T2	21127	715	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	551	0	0
T15	494	0	0	0
T16	5016	539	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	1273	0	0
T49	0	150	0	0
T50	5366	381	0	0
T78	0	1146	0	0
T79	0	644	0	0
T80	0	912	0	0
T81	0	268	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8484254	0	0
T1	564982	564581	0	0
T2	21127	20666	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8020	0	0
T15	494	93	0	0
T16	5016	4603	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	455	0	0
T8	19601	0	0	0
T16	5016	1	0	0
T17	457	0	0	0
T18	878	0	0	0
T26	493	0	0	0
T28	506	0	0	0
T50	5366	7	0	0
T61	627	0	0	0
T69	402	0	0	0
T75	402	0	0	0
T78	0	17	0	0
T79	0	9	0	0
T99	0	24	0	0
T102	0	23	0	0
T236	0	8	0	0
T238	0	4	0	0
T241	0	7	0	0
T243	0	24	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	67080	0	0
T2	21127	948	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	1474	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	734	0	0
T49	0	202	0	0
T50	5366	0	0	0
T81	0	29	0	0
T101	0	216	0	0
T226	0	303	0	0
T235	0	2013	0	0
T237	0	1601	0	0
T239	0	2360	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	821	0	0
T2	21127	11	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	19	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	19	0	0
T49	0	5	0	0
T50	5366	0	0	0
T81	0	4	0	0
T101	0	6	0	0
T226	0	4	0	0
T235	0	32	0	0
T237	0	31	0	0
T239	0	35	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8036006	0	0
T1	564982	564581	0	0
T2	21127	14116	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	4198	0	0
T15	494	93	0	0
T16	5016	2014	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8038129	0	0
T1	564982	564582	0	0
T2	21127	14119	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	4199	0	0
T15	494	94	0	0
T16	5016	2014	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	1608	0	0
T2	21127	11	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	19	0	0
T15	494	0	0	0
T16	5016	11	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	19	0	0
T49	0	5	0	0
T50	5366	7	0	0
T78	0	17	0	0
T79	0	12	0	0
T80	0	17	0	0
T81	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	1579	0	0
T2	21127	11	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	19	0	0
T15	494	0	0	0
T16	5016	1	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	19	0	0
T49	0	5	0	0
T50	5366	7	0	0
T78	0	17	0	0
T79	0	12	0	0
T80	0	17	0	0
T81	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	821	0	0
T2	21127	11	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	19	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	19	0	0
T49	0	5	0	0
T50	5366	0	0	0
T81	0	4	0	0
T101	0	6	0	0
T226	0	4	0	0
T235	0	32	0	0
T237	0	31	0	0
T239	0	35	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	821	0	0
T2	21127	11	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	19	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	19	0	0
T49	0	5	0	0
T50	5366	0	0	0
T81	0	4	0	0
T101	0	6	0	0
T226	0	4	0	0
T235	0	32	0	0
T237	0	31	0	0
T239	0	35	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	66132	0	0
T2	21127	935	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	1455	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	715	0	0
T49	0	196	0	0
T50	5366	0	0	0
T81	0	25	0	0
T101	0	210	0	0
T226	0	299	0	0
T235	0	1976	0	0
T237	0	1570	0	0
T239	0	2321	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	690	0	0
T2	21127	9	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	19	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	19	0	0
T49	0	4	0	0
T50	5366	0	0	0
T81	0	4	0	0
T101	0	6	0	0
T226	0	4	0	0
T235	0	27	0	0
T237	0	31	0	0
T239	0	31	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T4,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T4,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T4,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T11
0	1	Covered	T4,T36,T60
1	0	Covered	T87,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T51
0	1	Covered	T8,T11,T51
1	0	Covered	T87,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T11,T51
1	-	Covered	T8,T11,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T8,T11
DetectSt	168	Covered	T4,T8,T11
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T8,T11,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T8,T11
DebounceSt->IdleSt	163	Covered	T4,T11,T51
DetectSt->IdleSt	186	Covered	T4,T36,T60
DetectSt->StableSt	191	Covered	T8,T11,T51
IdleSt->DebounceSt	148	Covered	T4,T8,T11
StableSt->IdleSt	206	Covered	T8,T11,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T8,T11
0	1	Covered	T4,T8,T11
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T11
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T11,T51
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T4,T36,T60
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T51
DetectSt	-	-	-	-	0	0	-	Covered	T4,T8,T11
StableSt	-	-	-	-	-	-	1	Covered	T8,T11,T51
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	756	0	0
CntIncr_A	9133666	41388	0	0
CntNoWrap_A	9133666	8486683	0	0
DetectStDropOut_A	9133666	68	0	0
DetectedOut_A	9133666	10393	0	0
DetectedPulseOut_A	9133666	287	0	0
DisabledIdleSt_A	9133666	8156311	0	0
DisabledNoDetection_A	9133666	8158023	0	0
EnterDebounceSt_A	9133666	398	0	0
EnterDetectSt_A	9133666	359	0	0
EnterStableSt_A	9133666	287	0	0
PulseIsPulse_A	9133666	287	0	0
StayInStableSt	9133666	10084	0	0
gen_high_level_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	263	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	756	0	0
T4	25465	5	0	0
T8	19601	12	0	0
T11	0	13	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T26	493	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T38	0	9	0	0
T50	5366	0	0	0
T51	0	5	0	0
T59	0	2	0	0
T60	0	6	0	0
T61	627	0	0	0
T120	0	11	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	41388	0	0
T4	25465	242	0	0
T8	19601	1122	0	0
T11	0	555	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T26	493	0	0	0
T36	0	189	0	0
T37	0	106	0	0
T38	0	887	0	0
T50	5366	0	0	0
T51	0	215	0	0
T59	0	127	0	0
T60	0	531	0	0
T61	627	0	0	0
T120	0	907	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8486683	0	0
T1	564982	564581	0	0
T2	21127	20688	0	0
T3	825	424	0	0
T4	25465	23791	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	68	0	0
T4	25465	2	0	0
T8	19601	0	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T26	493	0	0	0
T36	0	2	0	0
T50	5366	0	0	0
T60	0	3	0	0
T61	627	0	0	0
T105	0	5	0	0
T120	0	5	0	0
T143	0	10	0	0
T244	0	1	0	0
T245	0	2	0	0
T246	0	10	0	0
T247	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	10393	0	0
T8	19601	57	0	0
T9	2955	0	0	0
T10	898	0	0	0
T11	0	57	0	0
T26	493	0	0	0
T28	506	0	0	0
T37	0	102	0	0
T38	0	18	0	0
T39	0	273	0	0
T45	0	134	0	0
T50	5366	0	0	0
T51	0	33	0	0
T59	0	33	0	0
T61	627	0	0	0
T69	402	0	0	0
T75	402	0	0	0
T76	423	0	0	0
T100	0	30	0	0
T237	0	105	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	287	0	0
T8	19601	6	0	0
T9	2955	0	0	0
T10	898	0	0	0
T11	0	6	0	0
T26	493	0	0	0
T28	506	0	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	4	0	0
T45	0	2	0	0
T50	5366	0	0	0
T51	0	2	0	0
T59	0	1	0	0
T61	627	0	0	0
T69	402	0	0	0
T75	402	0	0	0
T76	423	0	0	0
T100	0	3	0	0
T237	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8156311	0	0
T1	564982	564581	0	0
T2	21127	19742	0	0
T3	825	424	0	0
T4	25465	20609	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	6584	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8158023	0	0
T1	564982	564582	0	0
T2	21127	19746	0	0
T3	825	425	0	0
T4	25465	20611	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	6586	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	398	0	0
T4	25465	3	0	0
T8	19601	6	0	0
T11	0	7	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T26	493	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	5	0	0
T50	5366	0	0	0
T51	0	3	0	0
T59	0	1	0	0
T60	0	3	0	0
T61	627	0	0	0
T120	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	359	0	0
T4	25465	2	0	0
T8	19601	6	0	0
T11	0	6	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T26	493	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T50	5366	0	0	0
T51	0	2	0	0
T59	0	1	0	0
T60	0	3	0	0
T61	627	0	0	0
T120	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	287	0	0
T8	19601	6	0	0
T9	2955	0	0	0
T10	898	0	0	0
T11	0	6	0	0
T26	493	0	0	0
T28	506	0	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	4	0	0
T45	0	2	0	0
T50	5366	0	0	0
T51	0	2	0	0
T59	0	1	0	0
T61	627	0	0	0
T69	402	0	0	0
T75	402	0	0	0
T76	423	0	0	0
T100	0	3	0	0
T237	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	287	0	0
T8	19601	6	0	0
T9	2955	0	0	0
T10	898	0	0	0
T11	0	6	0	0
T26	493	0	0	0
T28	506	0	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	4	0	0
T45	0	2	0	0
T50	5366	0	0	0
T51	0	2	0	0
T59	0	1	0	0
T61	627	0	0	0
T69	402	0	0	0
T75	402	0	0	0
T76	423	0	0	0
T100	0	3	0	0
T237	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	10084	0	0
T8	19601	51	0	0
T9	2955	0	0	0
T10	898	0	0	0
T11	0	51	0	0
T26	493	0	0	0
T28	506	0	0	0
T37	0	100	0	0
T38	0	14	0	0
T39	0	269	0	0
T45	0	132	0	0
T50	5366	0	0	0
T51	0	31	0	0
T59	0	32	0	0
T61	627	0	0	0
T69	402	0	0	0
T75	402	0	0	0
T76	423	0	0	0
T100	0	27	0	0
T237	0	103	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	263	0	0
T8	19601	6	0	0
T9	2955	0	0	0
T10	898	0	0	0
T11	0	6	0	0
T26	493	0	0	0
T28	506	0	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	4	0	0
T45	0	2	0	0
T50	5366	0	0	0
T51	0	2	0	0
T59	0	1	0	0
T61	627	0	0	0
T69	402	0	0	0
T75	402	0	0	0
T76	423	0	0	0
T100	0	3	0	0
T237	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T14,T16
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T14,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T14,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T14,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T49
1	1	Covered	T2,T14,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T14,T50
0	1	Covered	T50,T78,T99
1	0	Covered	T80,T238,T248

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T14,T49
0	1	Covered	T2,T14,T49
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T14,T49
1	-	Covered	T2,T14,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T14,T16
DetectSt	168	Covered	T2,T14,T50
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T14,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T14,T50
DebounceSt->IdleSt	163	Covered	T16,T233,T234
DetectSt->IdleSt	186	Covered	T50,T78,T80
DetectSt->StableSt	191	Covered	T2,T14,T49
IdleSt->DebounceSt	148	Covered	T2,T14,T16
StableSt->IdleSt	206	Covered	T2,T14,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T14,T16
0	1	Covered	T2,T14,T16
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T14,T50
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T14,T16
IdleSt	0	-	-	-	-	-	-	Covered	T2,T14,T16
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T14,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T233,T234
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T14,T16
DetectSt	-	-	-	-	1	-	-	Covered	T50,T78,T80
DetectSt	-	-	-	-	0	1	-	Covered	T2,T14,T49
DetectSt	-	-	-	-	0	0	-	Covered	T2,T14,T50
StableSt	-	-	-	-	-	-	1	Covered	T2,T14,T49
StableSt	-	-	-	-	-	-	0	Covered	T2,T14,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	2503	0	0
CntIncr_A	9133666	86240	0	0
CntNoWrap_A	9133666	8484936	0	0
DetectStDropOut_A	9133666	305	0	0
DetectedOut_A	9133666	71589	0	0
DetectedPulseOut_A	9133666	829	0	0
DisabledIdleSt_A	9133666	8027776	0	0
DisabledNoDetection_A	9133666	8029907	0	0
EnterDebounceSt_A	9133666	1270	0	0
EnterDetectSt_A	9133666	1235	0	0
EnterStableSt_A	9133666	829	0	0
PulseIsPulse_A	9133666	829	0	0
StayInStableSt	9133666	70644	0	0
gen_high_event_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_high_level_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	713	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	2503	0	0
T2	21127	20	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	56	0	0
T15	494	0	0	0
T16	5016	7	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	56	0	0
T49	0	24	0	0
T50	5366	12	0	0
T78	0	22	0	0
T79	0	14	0	0
T80	0	14	0	0
T81	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	86240	0	0
T2	21127	670	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	1428	0	0
T15	494	0	0	0
T16	5016	343	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	1260	0	0
T49	0	444	0	0
T50	5366	326	0	0
T78	0	737	0	0
T79	0	364	0	0
T80	0	374	0	0
T81	0	1809	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8484936	0	0
T1	564982	564581	0	0
T2	21127	20668	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8002	0	0
T15	494	93	0	0
T16	5016	4608	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	305	0	0
T9	2955	0	0	0
T10	898	0	0	0
T26	493	0	0	0
T27	1322	0	0	0
T28	506	0	0	0
T50	5366	6	0	0
T61	627	0	0	0
T69	402	0	0	0
T75	402	0	0	0
T76	423	0	0	0
T78	0	11	0	0
T99	0	10	0	0
T102	0	8	0	0
T236	0	19	0	0
T238	0	1	0	0
T239	0	1	0	0
T243	0	24	0	0
T248	0	7	0	0
T249	0	24	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	71589	0	0
T2	21127	1744	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	1203	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	2513	0	0
T49	0	866	0	0
T50	5366	0	0	0
T79	0	1669	0	0
T81	0	1291	0	0
T101	0	1115	0	0
T226	0	7211	0	0
T235	0	162	0	0
T237	0	559	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	829	0	0
T2	21127	10	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	28	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	28	0	0
T49	0	12	0	0
T50	5366	0	0	0
T79	0	7	0	0
T81	0	27	0	0
T101	0	8	0	0
T226	0	21	0	0
T235	0	7	0	0
T237	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8027776	0	0
T1	564982	564581	0	0
T2	21127	13253	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	4070	0	0
T15	494	93	0	0
T16	5016	2014	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8029907	0	0
T1	564982	564582	0	0
T2	21127	13256	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	4070	0	0
T15	494	94	0	0
T16	5016	2014	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	1270	0	0
T2	21127	10	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	28	0	0
T15	494	0	0	0
T16	5016	7	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	28	0	0
T49	0	12	0	0
T50	5366	6	0	0
T78	0	11	0	0
T79	0	7	0	0
T80	0	7	0	0
T81	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	1235	0	0
T2	21127	10	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	28	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	28	0	0
T49	0	12	0	0
T50	5366	6	0	0
T78	0	11	0	0
T79	0	7	0	0
T80	0	7	0	0
T81	0	27	0	0
T226	0	21	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	829	0	0
T2	21127	10	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	28	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	28	0	0
T49	0	12	0	0
T50	5366	0	0	0
T79	0	7	0	0
T81	0	27	0	0
T101	0	8	0	0
T226	0	21	0	0
T235	0	7	0	0
T237	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	829	0	0
T2	21127	10	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	28	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	28	0	0
T49	0	12	0	0
T50	5366	0	0	0
T79	0	7	0	0
T81	0	27	0	0
T101	0	8	0	0
T226	0	21	0	0
T235	0	7	0	0
T237	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	70644	0	0
T2	21127	1732	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	1174	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	2483	0	0
T49	0	848	0	0
T50	5366	0	0	0
T79	0	1657	0	0
T81	0	1260	0	0
T101	0	1107	0	0
T226	0	7189	0	0
T235	0	154	0	0
T237	0	545	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	713	0	0
T2	21127	8	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	27	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	26	0	0
T49	0	6	0	0
T50	5366	0	0	0
T79	0	2	0	0
T81	0	23	0	0
T101	0	8	0	0
T226	0	20	0	0
T235	0	6	0	0
T237	0	14	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T4,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T4,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T2,T4,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T14
0	1	Covered	T51,T36,T60
1	0	Covered	T87,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T14
0	1	Covered	T4,T8,T11
1	0	Covered	T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T14
1	-	Covered	T4,T8,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T14
DetectSt	168	Covered	T2,T4,T14
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T4,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T14
DebounceSt->IdleSt	163	Covered	T2,T4,T8
DetectSt->IdleSt	186	Covered	T51,T36,T60
DetectSt->StableSt	191	Covered	T2,T4,T14
IdleSt->DebounceSt	148	Covered	T2,T4,T14
StableSt->IdleSt	206	Covered	T2,T4,T14

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T14
0	1	Covered	T2,T4,T14
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T14
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T14
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T4,T8
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T14
DetectSt	-	-	-	-	1	-	-	Covered	T51,T36,T60
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T14
DetectSt	-	-	-	-	0	0	-	Covered	T2,T4,T14
StableSt	-	-	-	-	-	-	1	Covered	T4,T8,T11
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	828	0	0
CntIncr_A	9133666	43406	0	0
CntNoWrap_A	9133666	8486611	0	0
DetectStDropOut_A	9133666	76	0	0
DetectedOut_A	9133666	14350	0	0
DetectedPulseOut_A	9133666	310	0	0
DisabledIdleSt_A	9133666	8143536	0	0
DisabledNoDetection_A	9133666	8145237	0	0
EnterDebounceSt_A	9133666	439	0	0
EnterDetectSt_A	9133666	390	0	0
EnterStableSt_A	9133666	310	0	0
PulseIsPulse_A	9133666	310	0	0
StayInStableSt	9133666	14004	0	0
gen_high_level_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	272	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	828	0	0
T2	21127	6	0	0
T3	825	0	0	0
T4	25465	15	0	0
T8	19601	3	0	0
T11	0	8	0	0
T14	8467	2	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T36	0	8	0	0
T50	5366	0	0	0
T51	0	3	0	0
T59	0	17	0	0
T60	0	6	0	0
T120	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	43406	0	0
T2	21127	218	0	0
T3	825	0	0	0
T4	25465	605	0	0
T8	19601	259	0	0
T11	0	380	0	0
T14	8467	36	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T36	0	378	0	0
T50	5366	0	0	0
T51	0	153	0	0
T59	0	1327	0	0
T60	0	531	0	0
T120	0	552	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8486611	0	0
T1	564982	564581	0	0
T2	21127	20682	0	0
T3	825	424	0	0
T4	25465	23781	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8056	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	76	0	0
T30	676	0	0	0
T36	20520	4	0	0
T40	1001	0	0	0
T44	994	0	0	0
T45	0	6	0	0
T51	9191	1	0	0
T60	0	3	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T100	0	2	0	0
T111	448	0	0	0
T143	0	5	0	0
T181	959	0	0	0
T204	0	4	0	0
T250	0	5	0	0
T251	0	2	0	0
T252	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	14350	0	0
T2	21127	171	0	0
T3	825	0	0	0
T4	25465	92	0	0
T8	19601	30	0	0
T11	0	20	0	0
T14	8467	60	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T37	0	234	0	0
T49	0	156	0	0
T50	5366	0	0	0
T59	0	38	0	0
T79	0	207	0	0
T120	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	310	0	0
T2	21127	2	0	0
T3	825	0	0	0
T4	25465	5	0	0
T8	19601	1	0	0
T11	0	4	0	0
T14	8467	1	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T37	0	11	0	0
T49	0	5	0	0
T50	5366	0	0	0
T59	0	8	0	0
T79	0	5	0	0
T120	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8143536	0	0
T1	564982	564581	0	0
T2	21127	18946	0	0
T3	825	424	0	0
T4	25465	20609	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	6856	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8145237	0	0
T1	564982	564582	0	0
T2	21127	18950	0	0
T3	825	425	0	0
T4	25465	20611	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	6857	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	439	0	0
T2	21127	4	0	0
T3	825	0	0	0
T4	25465	10	0	0
T8	19601	2	0	0
T11	0	4	0	0
T14	8467	1	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T36	0	4	0	0
T50	5366	0	0	0
T51	0	2	0	0
T59	0	9	0	0
T60	0	3	0	0
T120	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	390	0	0
T2	21127	2	0	0
T3	825	0	0	0
T4	25465	5	0	0
T8	19601	1	0	0
T11	0	4	0	0
T14	8467	1	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T36	0	4	0	0
T50	5366	0	0	0
T51	0	1	0	0
T59	0	8	0	0
T60	0	3	0	0
T120	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	310	0	0
T2	21127	2	0	0
T3	825	0	0	0
T4	25465	5	0	0
T8	19601	1	0	0
T11	0	4	0	0
T14	8467	1	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T37	0	11	0	0
T49	0	5	0	0
T50	5366	0	0	0
T59	0	8	0	0
T79	0	5	0	0
T120	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	310	0	0
T2	21127	2	0	0
T3	825	0	0	0
T4	25465	5	0	0
T8	19601	1	0	0
T11	0	4	0	0
T14	8467	1	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T37	0	11	0	0
T49	0	5	0	0
T50	5366	0	0	0
T59	0	8	0	0
T79	0	5	0	0
T120	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	14004	0	0
T2	21127	167	0	0
T3	825	0	0	0
T4	25465	87	0	0
T8	19601	29	0	0
T11	0	16	0	0
T14	8467	58	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T37	0	223	0	0
T49	0	148	0	0
T50	5366	0	0	0
T59	0	30	0	0
T79	0	202	0	0
T120	0	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	272	0	0
T4	25465	5	0	0
T8	19601	1	0	0
T11	0	4	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T26	493	0	0	0
T37	0	11	0	0
T45	0	1	0	0
T49	0	2	0	0
T50	5366	0	0	0
T59	0	8	0	0
T61	627	0	0	0
T79	0	5	0	0
T81	0	3	0	0
T120	0	4	0	0