Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T14,T16
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T14,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T14,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T14,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T49
1	1	Covered	T2,T14,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T14,T50
0	1	Covered	T50,T78,T79
1	0	Covered	T79,T101,T238

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T14,T49
0	1	Covered	T2,T14,T49
1	0	Covered	T92

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T14,T49
1	-	Covered	T2,T14,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T14,T16
DetectSt	168	Covered	T2,T14,T50
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T14,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T14,T50
DebounceSt->IdleSt	163	Covered	T16,T233,T234
DetectSt->IdleSt	186	Covered	T50,T78,T79
DetectSt->StableSt	191	Covered	T2,T14,T49
IdleSt->DebounceSt	148	Covered	T2,T14,T16
StableSt->IdleSt	206	Covered	T2,T14,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T14,T16
0	1	Covered	T2,T14,T16
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T14,T50
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T14,T16
IdleSt	0	-	-	-	-	-	-	Covered	T2,T14,T16
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T14,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T233,T234
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T14,T16
DetectSt	-	-	-	-	1	-	-	Covered	T50,T78,T79
DetectSt	-	-	-	-	0	1	-	Covered	T2,T14,T49
DetectSt	-	-	-	-	0	0	-	Covered	T2,T14,T50
StableSt	-	-	-	-	-	-	1	Covered	T2,T14,T49
StableSt	-	-	-	-	-	-	0	Covered	T2,T14,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	2913	0	0
CntIncr_A	9133666	104104	0	0
CntNoWrap_A	9133666	8484526	0	0
DetectStDropOut_A	9133666	360	0	0
DetectedOut_A	9133666	82315	0	0
DetectedPulseOut_A	9133666	883	0	0
DisabledIdleSt_A	9133666	8021687	0	0
DisabledNoDetection_A	9133666	8023825	0	0
EnterDebounceSt_A	9133666	1471	0	0
EnterDetectSt_A	9133666	1443	0	0
EnterStableSt_A	9133666	883	0	0
PulseIsPulse_A	9133666	883	0	0
StayInStableSt	9133666	81322	0	0
gen_high_event_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_high_level_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	772	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	2913	0	0
T2	21127	40	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	26	0	0
T15	494	0	0	0
T16	5016	6	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	16	0	0
T49	0	46	0	0
T50	5366	8	0	0
T78	0	8	0	0
T79	0	46	0	0
T80	0	50	0	0
T81	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	104104	0	0
T2	21127	1500	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	507	0	0
T15	494	0	0	0
T16	5016	294	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	336	0	0
T49	0	1150	0	0
T50	5366	216	0	0
T78	0	268	0	0
T79	0	1251	0	0
T80	0	850	0	0
T81	0	990	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8484526	0	0
T1	564982	564581	0	0
T2	21127	20648	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8032	0	0
T15	494	93	0	0
T16	5016	4609	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	360	0	0
T9	2955	0	0	0
T10	898	0	0	0
T26	493	0	0	0
T27	1322	0	0	0
T28	506	0	0	0
T50	5366	4	0	0
T61	627	0	0	0
T69	402	0	0	0
T75	402	0	0	0
T76	423	0	0	0
T78	0	4	0	0
T79	0	16	0	0
T99	0	10	0	0
T101	0	20	0	0
T102	0	7	0	0
T236	0	23	0	0
T238	0	5	0	0
T243	0	28	0	0
T249	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	82315	0	0
T2	21127	1434	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	201	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	811	0	0
T49	0	1431	0	0
T50	5366	0	0	0
T80	0	1668	0	0
T81	0	352	0	0
T226	0	11067	0	0
T235	0	1693	0	0
T237	0	373	0	0
T248	0	2486	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	883	0	0
T2	21127	20	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	13	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	8	0	0
T49	0	23	0	0
T50	5366	0	0	0
T80	0	25	0	0
T81	0	15	0	0
T226	0	24	0	0
T235	0	32	0	0
T237	0	13	0	0
T248	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8021687	0	0
T1	564982	564581	0	0
T2	21127	13935	0	0
T3	825	424	0	0
T4	25465	23796	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	5211	0	0
T15	494	93	0	0
T16	5016	2014	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8023825	0	0
T1	564982	564582	0	0
T2	21127	13937	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	5212	0	0
T15	494	94	0	0
T16	5016	2014	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	1471	0	0
T2	21127	20	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	13	0	0
T15	494	0	0	0
T16	5016	6	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	8	0	0
T49	0	23	0	0
T50	5366	4	0	0
T78	0	4	0	0
T79	0	23	0	0
T80	0	25	0	0
T81	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	1443	0	0
T2	21127	20	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	13	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	8	0	0
T49	0	23	0	0
T50	5366	4	0	0
T78	0	4	0	0
T79	0	23	0	0
T80	0	25	0	0
T81	0	15	0	0
T226	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	883	0	0
T2	21127	20	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	13	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	8	0	0
T49	0	23	0	0
T50	5366	0	0	0
T80	0	25	0	0
T81	0	15	0	0
T226	0	24	0	0
T235	0	32	0	0
T237	0	13	0	0
T248	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	883	0	0
T2	21127	20	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	13	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	8	0	0
T49	0	23	0	0
T50	5366	0	0	0
T80	0	25	0	0
T81	0	15	0	0
T226	0	24	0	0
T235	0	32	0	0
T237	0	13	0	0
T248	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	81322	0	0
T2	21127	1411	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	188	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	801	0	0
T49	0	1398	0	0
T50	5366	0	0	0
T80	0	1643	0	0
T81	0	335	0	0
T226	0	11042	0	0
T235	0	1656	0	0
T237	0	360	0	0
T248	0	2456	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	772	0	0
T2	21127	17	0	0
T3	825	0	0	0
T4	25465	0	0	0
T8	19601	0	0	0
T14	8467	13	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T39	0	6	0	0
T49	0	13	0	0
T50	5366	0	0	0
T80	0	25	0	0
T81	0	13	0	0
T226	0	23	0	0
T235	0	27	0	0
T237	0	13	0	0
T248	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T4,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T4,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T2,T4,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T8
0	1	Covered	T51,T59,T120
1	0	Covered	T87,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T8
0	1	Covered	T2,T4,T8
1	0	Covered	T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T8
1	-	Covered	T2,T4,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T8
DetectSt	168	Covered	T2,T4,T8
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T4,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T8
DebounceSt->IdleSt	163	Covered	T4,T8,T51
DetectSt->IdleSt	186	Covered	T51,T59,T120
DetectSt->StableSt	191	Covered	T2,T4,T8
IdleSt->DebounceSt	148	Covered	T2,T4,T8
StableSt->IdleSt	206	Covered	T2,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T8
0	1	Covered	T2,T4,T8
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T8
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T8,T51
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T8
DetectSt	-	-	-	-	1	-	-	Covered	T51,T59,T120
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T8
DetectSt	-	-	-	-	0	0	-	Covered	T2,T4,T8
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9133666	819	0	0
CntIncr_A	9133666	40964	0	0
CntNoWrap_A	9133666	8486620	0	0
DetectStDropOut_A	9133666	30	0	0
DetectedOut_A	9133666	16374	0	0
DetectedPulseOut_A	9133666	347	0	0
DisabledIdleSt_A	9133666	8142058	0	0
DisabledNoDetection_A	9133666	8143778	0	0
EnterDebounceSt_A	9133666	440	0	0
EnterDetectSt_A	9133666	382	0	0
EnterStableSt_A	9133666	347	0	0
PulseIsPulse_A	9133666	347	0	0
StayInStableSt	9133666	16003	0	0
gen_high_level_sva.HighLevelEvent_A	9133666	8489780	0	0
gen_not_sticky_sva.StableStDropOut_A	9133666	320	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	819	0	0
T2	21127	6	0	0
T3	825	0	0	0
T4	25465	19	0	0
T8	19601	11	0	0
T11	0	4	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T36	0	14	0	0
T49	0	15	0	0
T50	5366	0	0	0
T51	0	9	0	0
T59	0	9	0	0
T60	0	14	0	0
T120	0	13	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	40964	0	0
T2	21127	222	0	0
T3	825	0	0	0
T4	25465	599	0	0
T8	19601	758	0	0
T11	0	166	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T36	0	532	0	0
T49	0	262	0	0
T50	5366	0	0	0
T51	0	437	0	0
T59	0	721	0	0
T60	0	1176	0	0
T120	0	1065	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8486620	0	0
T1	564982	564581	0	0
T2	21127	20682	0	0
T3	825	424	0	0
T4	25465	23777	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	8058	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	30	0	0
T30	676	0	0	0
T36	20520	0	0	0
T40	1001	0	0	0
T44	994	0	0	0
T51	9191	4	0	0
T59	0	4	0	0
T62	2265	0	0	0
T66	491	0	0	0
T78	6020	0	0	0
T95	0	2	0	0
T103	0	3	0	0
T111	448	0	0	0
T120	0	6	0	0
T181	959	0	0	0
T251	0	2	0	0
T252	0	1	0	0
T253	0	1	0	0
T254	0	3	0	0
T255	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	16374	0	0
T2	21127	220	0	0
T3	825	0	0	0
T4	25465	332	0	0
T8	19601	315	0	0
T11	0	32	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T36	0	129	0	0
T37	0	310	0	0
T38	0	283	0	0
T49	0	165	0	0
T50	5366	0	0	0
T60	0	66	0	0
T81	0	86	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	347	0	0
T2	21127	3	0	0
T3	825	0	0	0
T4	25465	8	0	0
T8	19601	5	0	0
T11	0	2	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T36	0	7	0	0
T37	0	6	0	0
T38	0	3	0	0
T49	0	7	0	0
T50	5366	0	0	0
T60	0	7	0	0
T81	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8142058	0	0
T1	564982	564581	0	0
T2	21127	19257	0	0
T3	825	424	0	0
T4	25465	20609	0	0
T5	738	337	0	0
T6	435	34	0	0
T7	437	36	0	0
T14	8467	7857	0	0
T15	494	93	0	0
T16	5016	4615	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8143778	0	0
T1	564982	564582	0	0
T2	21127	19260	0	0
T3	825	425	0	0
T4	25465	20611	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	7859	0	0
T15	494	94	0	0
T16	5016	4616	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	440	0	0
T2	21127	3	0	0
T3	825	0	0	0
T4	25465	11	0	0
T8	19601	6	0	0
T11	0	2	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T36	0	7	0	0
T49	0	8	0	0
T50	5366	0	0	0
T51	0	5	0	0
T59	0	5	0	0
T60	0	7	0	0
T120	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	382	0	0
T2	21127	3	0	0
T3	825	0	0	0
T4	25465	8	0	0
T8	19601	5	0	0
T11	0	2	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T36	0	7	0	0
T49	0	7	0	0
T50	5366	0	0	0
T51	0	4	0	0
T59	0	4	0	0
T60	0	7	0	0
T120	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	347	0	0
T2	21127	3	0	0
T3	825	0	0	0
T4	25465	8	0	0
T8	19601	5	0	0
T11	0	2	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T36	0	7	0	0
T37	0	6	0	0
T38	0	3	0	0
T49	0	7	0	0
T50	5366	0	0	0
T60	0	7	0	0
T81	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	347	0	0
T2	21127	3	0	0
T3	825	0	0	0
T4	25465	8	0	0
T8	19601	5	0	0
T11	0	2	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T36	0	7	0	0
T37	0	6	0	0
T38	0	3	0	0
T49	0	7	0	0
T50	5366	0	0	0
T60	0	7	0	0
T81	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	16003	0	0
T2	21127	217	0	0
T3	825	0	0	0
T4	25465	324	0	0
T8	19601	310	0	0
T11	0	30	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T36	0	122	0	0
T37	0	304	0	0
T38	0	280	0	0
T49	0	158	0	0
T50	5366	0	0	0
T60	0	59	0	0
T81	0	84	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	8489780	0	0
T1	564982	564582	0	0
T2	21127	20694	0	0
T3	825	425	0	0
T4	25465	23808	0	0
T5	738	338	0	0
T6	435	35	0	0
T7	437	37	0	0
T14	8467	8060	0	0
T15	494	94	0	0
T16	5016	4616	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9133666	320	0	0
T2	21127	3	0	0
T3	825	0	0	0
T4	25465	8	0	0
T8	19601	5	0	0
T11	0	2	0	0
T14	8467	0	0	0
T15	494	0	0	0
T16	5016	0	0	0
T17	457	0	0	0
T18	878	0	0	0
T36	0	7	0	0
T37	0	6	0	0
T38	0	3	0	0
T49	0	7	0	0
T50	5366	0	0	0
T60	0	7	0	0
T81	0	2	0	0