Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T1,T3,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T3,T25
1	1	Covered	T6,T1,T2

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	226806	0	0
SrcPulseCheck_M	2147483647	229319	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	226806
T1	3706494	0
T2	20895316	18
T3	1248624	0
T4	14642766	32
T5	703222	16
T6	316506	2
T7	317682	0
T8	2999004	21
T9	322046	2
T10	50294	0
T11	111191	27
T12	414115	0
T14	9347775	6
T15	2968909	0
T16	5595762	3
T17	1256388	0
T18	7331811	0
T27	330836	0
T29	62963	0
T30	0	16
T31	0	14
T35	0	2
T43	0	14
T50	4469589	3
T51	0	3
T52	0	14
T53	0	14
T54	0	14
T55	0	14
T56	0	16
T57	0	80
T58	200952	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	229319
T1	3706494	0
T2	20895316	18
T3	1248624	0
T4	14642766	32
T5	703222	16
T6	316506	2
T7	317682	0
T8	2999004	21
T9	2955	2
T10	898	0
T11	22238	27
T12	1025	0
T14	9347775	6
T15	2968909	0
T16	5595762	3
T17	1256388	0
T18	7331811	0
T27	1322	0
T29	525	0
T30	0	16
T31	0	14
T35	0	2
T43	0	14
T50	4469589	3
T51	0	3
T52	0	14
T53	0	14
T54	0	14
T55	0	14
T56	0	16
T57	0	80
T58	691	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T6,T2,T4
1	1	Covered	T34,T264,T297

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T34,T264,T297
1	1	Covered	T6,T2,T4

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1919	0	0
SrcPulseCheck_M	1249995120	1994	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1919
T1	564982	0
T2	21127	6
T3	825	0
T4	25465	12
T6	435	1
T7	437	0
T8	0	7
T9	0	1
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	0	1
T50	0	1
T61	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1994
T1	52767	0
T2	887365	6
T3	53463	0
T4	611177	12
T6	52316	1
T7	52510	0
T8	0	7
T9	0	1
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	0	1
T50	0	1
T61	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T6,T2,T4
1	1	Covered	T34,T264,T297

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T34,T264,T297
1	1	Covered	T6,T2,T4

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1982	0	0
SrcPulseCheck_M	9385728	1982	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1982
T1	52767	0
T2	887365	6
T3	53463	0
T4	611177	12
T6	52316	1
T7	52510	0
T8	0	7
T9	0	1
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	0	1
T50	0	1
T61	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1982
T1	564982	0
T2	21127	6
T3	825	0
T4	25465	12
T6	435	1
T7	437	0
T8	0	7
T9	0	1
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	0	1
T50	0	1
T61	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T64

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T64
1	1	Covered	T1,T3,T9

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	951	0	0
SrcPulseCheck_M	1249995120	1020	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	951
T1	564982	2
T2	21127	0
T3	825	2
T4	25465	0
T8	19601	0
T9	0	1
T14	8467	0
T15	494	0
T16	5016	0
T17	457	0
T18	878	0
T25	0	1
T43	0	1
T58	0	1
T62	0	1
T63	0	1
T64	0	3
T65	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1020
T1	52767	2
T2	887365	0
T3	53463	2
T4	611177	0
T8	156811	0
T9	0	1
T14	397958	0
T15	128589	0
T16	238278	0
T17	59371	0
T18	430405	0
T25	0	1
T43	0	1
T58	0	1
T62	0	1
T63	0	1
T64	0	3
T65	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T64

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T64
1	1	Covered	T1,T3,T9

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1011	0	0
SrcPulseCheck_M	9385728	1011	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1011
T1	52767	2
T2	887365	0
T3	53463	2
T4	611177	0
T8	156811	0
T9	0	1
T14	397958	0
T15	128589	0
T16	238278	0
T17	59371	0
T18	430405	0
T25	0	1
T43	0	1
T58	0	1
T62	0	1
T63	0	1
T64	0	3
T65	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1011
T1	564982	2
T2	21127	0
T3	825	2
T4	25465	0
T8	19601	0
T9	0	1
T14	8467	0
T15	494	0
T16	5016	0
T17	457	0
T18	878	0
T25	0	1
T43	0	1
T58	0	1
T62	0	1
T63	0	1
T64	0	3
T65	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T64

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T64
1	1	Covered	T1,T3,T9

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	973	0	0
SrcPulseCheck_M	1249995120	1045	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	973
T1	564982	2
T2	21127	0
T3	825	2
T4	25465	0
T8	19601	0
T9	0	1
T14	8467	0
T15	494	0
T16	5016	0
T17	457	0
T18	878	0
T25	0	1
T43	0	1
T58	0	1
T62	0	1
T63	0	1
T64	0	3
T65	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1045
T1	52767	2
T2	887365	0
T3	53463	2
T4	611177	0
T8	156811	0
T9	0	1
T14	397958	0
T15	128589	0
T16	238278	0
T17	59371	0
T18	430405	0
T25	0	1
T43	0	1
T58	0	1
T62	0	1
T63	0	1
T64	0	3
T65	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T64

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T64
1	1	Covered	T1,T3,T9

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1034	0	0
SrcPulseCheck_M	9385728	1034	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1034
T1	52767	2
T2	887365	0
T3	53463	2
T4	611177	0
T8	156811	0
T9	0	1
T14	397958	0
T15	128589	0
T16	238278	0
T17	59371	0
T18	430405	0
T25	0	1
T43	0	1
T58	0	1
T62	0	1
T63	0	1
T64	0	3
T65	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1034
T1	564982	2
T2	21127	0
T3	825	2
T4	25465	0
T8	19601	0
T9	0	1
T14	8467	0
T15	494	0
T16	5016	0
T17	457	0
T18	878	0
T25	0	1
T43	0	1
T58	0	1
T62	0	1
T63	0	1
T64	0	3
T65	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T64

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T64
1	1	Covered	T1,T3,T9

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	978	0	0
SrcPulseCheck_M	1249995120	1049	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	978
T1	564982	2
T2	21127	0
T3	825	2
T4	25465	0
T8	19601	0
T9	0	1
T14	8467	0
T15	494	0
T16	5016	0
T17	457	0
T18	878	0
T25	0	1
T43	0	1
T58	0	1
T62	0	1
T63	0	1
T64	0	3
T65	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1049
T1	52767	2
T2	887365	0
T3	53463	2
T4	611177	0
T8	156811	0
T9	0	1
T14	397958	0
T15	128589	0
T16	238278	0
T17	59371	0
T18	430405	0
T25	0	1
T43	0	1
T58	0	1
T62	0	1
T63	0	1
T64	0	3
T65	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T64

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T64
1	1	Covered	T1,T3,T9

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1038	0	0
SrcPulseCheck_M	9385728	1038	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1038
T1	52767	2
T2	887365	0
T3	53463	2
T4	611177	0
T8	156811	0
T9	0	1
T14	397958	0
T15	128589	0
T16	238278	0
T17	59371	0
T18	430405	0
T25	0	1
T43	0	1
T58	0	1
T62	0	1
T63	0	1
T64	0	3
T65	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1038
T1	564982	2
T2	21127	0
T3	825	2
T4	25465	0
T8	19601	0
T9	0	1
T14	8467	0
T15	494	0
T16	5016	0
T17	457	0
T18	878	0
T25	0	1
T43	0	1
T58	0	1
T62	0	1
T63	0	1
T64	0	3
T65	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T25
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T25
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	992	0	0
SrcPulseCheck_M	1249995120	1065	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	992
T1	564982	2
T2	21127	0
T3	825	2
T4	25465	0
T8	19601	0
T14	8467	0
T15	494	0
T16	5016	0
T17	457	0
T18	878	0
T25	0	2
T43	0	2
T64	0	6
T82	0	2
T83	0	2
T84	0	2
T85	0	2
T86	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1065
T1	52767	2
T2	887365	0
T3	53463	2
T4	611177	0
T8	156811	0
T14	397958	0
T15	128589	0
T16	238278	0
T17	59371	0
T18	430405	0
T25	0	2
T43	0	2
T64	0	6
T82	0	2
T83	0	2
T84	0	2
T85	0	2
T86	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T25
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T25
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1052	0	0
SrcPulseCheck_M	9385728	1052	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1052
T1	52767	2
T2	887365	0
T3	53463	2
T4	611177	0
T8	156811	0
T14	397958	0
T15	128589	0
T16	238278	0
T17	59371	0
T18	430405	0
T25	0	2
T43	0	2
T64	0	6
T82	0	2
T83	0	2
T84	0	2
T85	0	2
T86	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1052
T1	564982	2
T2	21127	0
T3	825	2
T4	25465	0
T8	19601	0
T14	8467	0
T15	494	0
T16	5016	0
T17	457	0
T18	878	0
T25	0	2
T43	0	2
T64	0	6
T82	0	2
T83	0	2
T84	0	2
T85	0	2
T86	0	2

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T11,T64

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T11,T64
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1028	0	0
SrcPulseCheck_M	1249995120	1102	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1028
T1	564982	1
T2	21127	3
T3	825	1
T4	25465	7
T8	19601	1
T11	0	4
T14	8467	0
T15	494	0
T16	5016	0
T17	457	0
T18	878	0
T25	0	1
T36	0	7
T59	0	10
T60	0	7

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1102
T1	52767	1
T2	887365	3
T3	53463	1
T4	611177	7
T8	156811	1
T11	0	4
T14	397958	0
T15	128589	0
T16	238278	0
T17	59371	0
T18	430405	0
T25	0	1
T36	0	7
T59	0	10
T60	0	7

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T15,T26,T27
1	0	Covered	T15,T26,T27
1	1	Covered	T15,T26,T27

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T15,T26,T27
1	0	Covered	T15,T26,T27
1	1	Covered	T15,T26,T27

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	2936	0	0
SrcPulseCheck_M	1249995120	3010	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	2936
T8	19601	0
T15	494	20
T16	5016	0
T17	457	0
T18	878	0
T26	493	20
T27	0	20
T28	506	0
T35	0	20
T43	0	20
T50	5366	0
T61	627	0
T63	0	20
T65	0	40
T66	0	20
T67	0	20
T68	0	20
T69	402	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	3010
T8	156811	0
T15	128589	20
T16	238278	0
T17	59371	0
T18	430405	0
T26	241675	20
T27	0	20
T28	60717	0
T35	0	20
T43	0	20
T50	257551	0
T61	156671	0
T63	0	20
T65	0	40
T66	0	20
T67	0	20
T68	0	20
T69	193287	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T15,T26,T27
1	0	Covered	T15,T26,T27
1	1	Covered	T15,T26,T27

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T15,T26,T27
1	0	Covered	T15,T26,T27
1	1	Covered	T15,T26,T27

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	2999	0	0
SrcPulseCheck_M	9385728	2999	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	2999
T8	156811	0
T15	128589	20
T16	238278	0
T17	59371	0
T18	430405	0
T26	241675	20
T27	0	20
T28	60717	0
T35	0	20
T43	0	20
T50	257551	0
T61	156671	0
T63	0	20
T65	0	40
T66	0	20
T67	0	20
T68	0	20
T69	193287	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	2999
T8	19601	0
T15	494	20
T16	5016	0
T17	457	0
T18	878	0
T26	493	20
T27	0	20
T28	506	0
T35	0	20
T43	0	20
T50	5366	0
T61	627	0
T63	0	20
T65	0	40
T66	0	20
T67	0	20
T68	0	20
T69	402	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T15,T26,T28
1	0	Covered	T15,T26,T28
1	1	Covered	T28,T9,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T15,T26,T28
1	0	Covered	T28,T9,T29
1	1	Covered	T15,T26,T28

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	6352	0	0
SrcPulseCheck_M	1249995120	6423	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	6352
T8	19601	0
T9	0	20
T15	494	1
T16	5016	0
T17	457	0
T18	878	0
T26	493	1
T27	0	1
T28	506	20
T29	0	20
T35	0	41
T50	5366	0
T61	627	0
T62	0	20
T66	0	1
T69	402	0
T70	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	6423
T8	156811	0
T9	0	20
T15	128589	1
T16	238278	0
T17	59371	0
T18	430405	0
T26	241675	1
T27	0	1
T28	60717	20
T29	0	20
T35	0	41
T50	257551	0
T61	156671	0
T62	0	20
T66	0	1
T69	193287	0
T70	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T15,T26,T28
1	0	Covered	T15,T26,T28
1	1	Covered	T28,T9,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T15,T26,T28
1	0	Covered	T28,T9,T29
1	1	Covered	T15,T26,T28

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	6406	0	0
SrcPulseCheck_M	9385728	6408	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	6406
T8	156811	0
T9	0	20
T15	128589	1
T16	238278	0
T17	59371	0
T18	430405	0
T26	241675	1
T27	0	1
T28	60717	20
T29	0	20
T35	0	41
T50	257551	0
T61	156671	0
T62	0	20
T66	0	1
T69	193287	0
T70	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	6408
T8	19601	0
T9	0	20
T15	494	1
T16	5016	0
T17	457	0
T18	878	0
T26	493	1
T27	0	1
T28	506	20
T29	0	20
T35	0	41
T50	5366	0
T61	627	0
T62	0	20
T66	0	1
T69	402	0
T70	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T6,T2,T4
1	1	Covered	T28,T9,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T28,T9,T29
1	1	Covered	T6,T2,T4

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	7473	0	0
SrcPulseCheck_M	1249995120	7551	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	7473
T1	564982	0
T2	21127	6
T3	825	0
T4	25465	12
T6	435	1
T7	437	0
T8	0	7
T14	8467	2
T15	494	1
T16	5016	1
T17	457	0
T18	0	1
T50	0	1
T61	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	7551
T1	52767	0
T2	887365	6
T3	53463	0
T4	611177	12
T6	52316	1
T7	52510	0
T8	0	7
T14	397958	2
T15	128589	1
T16	238278	1
T17	59371	0
T18	0	1
T50	0	1
T61	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T6,T2,T4
1	1	Covered	T28,T9,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T28,T9,T29
1	1	Covered	T6,T2,T4

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	7536	0	0
SrcPulseCheck_M	9385728	7537	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	7536
T1	52767	0
T2	887365	6
T3	53463	0
T4	611177	12
T6	52316	1
T7	52510	0
T8	0	7
T14	397958	2
T15	128589	1
T16	238278	1
T17	59371	0
T18	0	1
T50	0	1
T61	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	7537
T1	564982	0
T2	21127	6
T3	825	0
T4	25465	12
T6	435	1
T7	437	0
T8	0	7
T14	8467	2
T15	494	1
T16	5016	1
T17	457	0
T18	0	1
T50	0	1
T61	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T28,T9,T29
1	0	Covered	T28,T9,T29
1	1	Covered	T28,T9,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T28,T9,T29
1	0	Covered	T28,T9,T29
1	1	Covered	T28,T9,T29

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	6254	0	0
SrcPulseCheck_M	1249995120	6329	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	6254
T9	2955	20
T10	898	0
T11	22238	0
T27	1322	0
T28	506	20
T29	525	20
T35	0	40
T58	691	0
T62	0	20
T69	402	0
T70	0	20
T71	0	20
T72	0	20
T73	0	20
T74	0	20
T75	402	0
T76	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	6329
T9	322046	20
T10	50294	0
T11	111191	0
T27	330836	0
T28	60717	20
T29	62963	20
T35	0	40
T58	200952	0
T62	0	20
T69	193287	0
T70	0	20
T71	0	20
T72	0	20
T73	0	20
T74	0	20
T75	189429	0
T76	101649	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T28,T9,T29
1	0	Covered	T28,T9,T29
1	1	Covered	T28,T9,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T28,T9,T29
1	0	Covered	T28,T9,T29
1	1	Covered	T28,T9,T29

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	6318	0	0
SrcPulseCheck_M	9385728	6319	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	6318
T9	322046	20
T10	50294	0
T11	111191	0
T27	330836	0
T28	60717	20
T29	62963	20
T35	0	40
T58	200952	0
T62	0	20
T69	193287	0
T70	0	20
T71	0	20
T72	0	20
T73	0	20
T74	0	20
T75	189429	0
T76	101649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	6319
T9	2955	20
T10	898	0
T11	22238	0
T27	1322	0
T28	506	20
T29	525	20
T35	0	40
T58	691	0
T62	0	20
T69	402	0
T70	0	20
T71	0	20
T72	0	20
T73	0	20
T74	0	20
T75	402	0
T76	423	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T9,T10,T12
1	0	Covered	T9,T10,T12
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T9,T10,T12
1	0	Covered	T87,T88,T34
1	1	Covered	T9,T10,T12

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	993	0	0
SrcPulseCheck_M	1249995120	1069	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	993
T9	2955	1
T10	898	1
T11	22238	0
T12	1025	1
T13	3601	1
T27	1322	0
T29	525	0
T35	0	1
T40	0	1
T41	0	1
T44	0	1
T47	0	1
T58	691	0
T63	0	1
T70	523	0
T77	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1069
T9	322046	1
T10	50294	1
T11	111191	0
T12	414115	1
T13	247242	1
T27	330836	0
T29	62963	0
T35	0	1
T40	0	1
T41	0	1
T44	0	1
T47	0	1
T58	200952	0
T63	0	1
T70	130717	0
T77	131213	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T9,T10,T12
1	0	Covered	T9,T10,T12
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T9,T10,T12
1	0	Covered	T87,T88,T34
1	1	Covered	T9,T10,T12

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1057	0	0
SrcPulseCheck_M	9385728	1057	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1057
T9	322046	1
T10	50294	1
T11	111191	0
T12	414115	1
T13	247242	1
T27	330836	0
T29	62963	0
T35	0	1
T40	0	1
T41	0	1
T44	0	1
T47	0	1
T58	200952	0
T63	0	1
T70	130717	0
T77	131213	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1057
T9	2955	1
T10	898	1
T11	22238	0
T12	1025	1
T13	3601	1
T27	1322	0
T29	525	0
T35	0	1
T40	0	1
T41	0	1
T44	0	1
T47	0	1
T58	691	0
T63	0	1
T70	523	0
T77	423	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T6,T2,T4
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T87,T88,T34
1	1	Covered	T6,T2,T4

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1928	0	0
SrcPulseCheck_M	1249995120	2000	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1928
T1	564982	0
T2	21127	6
T3	825	0
T4	25465	11
T6	435	1
T7	437	0
T8	0	7
T9	0	2
T10	0	1
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	2000
T1	52767	0
T2	887365	6
T3	53463	0
T4	611177	11
T6	52316	1
T7	52510	0
T8	0	7
T9	0	2
T10	0	1
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T6,T2,T4
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T87,T88,T34
1	1	Covered	T6,T2,T4

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1989	0	0
SrcPulseCheck_M	9385728	1989	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1989
T1	52767	0
T2	887365	6
T3	53463	0
T4	611177	11
T6	52316	1
T7	52510	0
T8	0	7
T9	0	2
T10	0	1
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1989
T1	564982	0
T2	21127	6
T3	825	0
T4	25465	11
T6	435	1
T7	437	0
T8	0	7
T9	0	2
T10	0	1
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T30,T31
1	0	Covered	T5,T30,T31
1	1	Covered	T5,T30,T31

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T30,T31
1	0	Covered	T5,T30,T31
1	1	Covered	T5,T30,T31

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1330	0	0
SrcPulseCheck_M	1249995120	1401	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1330
T1	564982	0
T2	21127	0
T3	825	0
T4	25465	0
T5	738	5
T6	435	0
T7	437	0
T14	8467	0
T15	494	0
T16	5016	0
T30	0	5
T31	0	4
T43	0	4
T52	0	4
T53	0	4
T54	0	4
T55	0	4
T56	0	5
T57	0	25

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1401
T1	52767	0
T2	887365	0
T3	53463	0
T4	611177	0
T5	350873	5
T6	52316	0
T7	52510	0
T14	397958	0
T15	128589	0
T16	238278	0
T30	0	5
T31	0	4
T43	0	4
T52	0	4
T53	0	4
T54	0	4
T55	0	4
T56	0	5
T57	0	25

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T30,T31
1	0	Covered	T5,T30,T31
1	1	Covered	T5,T30,T31

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T30,T31
1	0	Covered	T5,T30,T31
1	1	Covered	T5,T30,T31

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1390	0	0
SrcPulseCheck_M	9385728	1390	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1390
T1	52767	0
T2	887365	0
T3	53463	0
T4	611177	0
T5	350873	5
T6	52316	0
T7	52510	0
T14	397958	0
T15	128589	0
T16	238278	0
T30	0	5
T31	0	4
T43	0	4
T52	0	4
T53	0	4
T54	0	4
T55	0	4
T56	0	5
T57	0	25

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1390
T1	564982	0
T2	21127	0
T3	825	0
T4	25465	0
T5	738	5
T6	435	0
T7	437	0
T14	8467	0
T15	494	0
T16	5016	0
T30	0	5
T31	0	4
T43	0	4
T52	0	4
T53	0	4
T54	0	4
T55	0	4
T56	0	5
T57	0	25

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T30,T31
1	0	Covered	T5,T30,T31
1	1	Covered	T5,T30,T31

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T30,T31
1	0	Covered	T5,T30,T31
1	1	Covered	T5,T30,T31

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1148	0	0
SrcPulseCheck_M	1249995120	1216	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1148
T1	564982	0
T2	21127	0
T3	825	0
T4	25465	0
T5	738	3
T6	435	0
T7	437	0
T14	8467	0
T15	494	0
T16	5016	0
T30	0	3
T31	0	3
T43	0	3
T52	0	3
T53	0	3
T54	0	3
T55	0	3
T56	0	3
T57	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1216
T1	52767	0
T2	887365	0
T3	53463	0
T4	611177	0
T5	350873	3
T6	52316	0
T7	52510	0
T14	397958	0
T15	128589	0
T16	238278	0
T30	0	3
T31	0	3
T43	0	3
T52	0	3
T53	0	3
T54	0	3
T55	0	3
T56	0	3
T57	0	15

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T30,T31
1	0	Covered	T5,T30,T31
1	1	Covered	T5,T30,T31

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T30,T31
1	0	Covered	T5,T30,T31
1	1	Covered	T5,T30,T31

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1205	0	0
SrcPulseCheck_M	9385728	1206	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1205
T1	52767	0
T2	887365	0
T3	53463	0
T4	611177	0
T5	350873	3
T6	52316	0
T7	52510	0
T14	397958	0
T15	128589	0
T16	238278	0
T30	0	3
T31	0	3
T43	0	3
T52	0	3
T53	0	3
T54	0	3
T55	0	3
T56	0	3
T57	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1206
T1	564982	0
T2	21127	0
T3	825	0
T4	25465	0
T5	738	3
T6	435	0
T7	437	0
T14	8467	0
T15	494	0
T16	5016	0
T30	0	3
T31	0	3
T43	0	3
T52	0	3
T53	0	3
T54	0	3
T55	0	3
T56	0	3
T57	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	7077	0	0
SrcPulseCheck_M	1249995120	7157	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	7077
T2	21127	65
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	62
T15	494	0
T16	5016	51
T17	457	0
T18	878	0
T48	0	1
T49	0	83
T50	5366	51
T78	0	51
T79	0	63
T80	0	76
T81	0	69

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	7157
T2	887365	65
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	62
T15	128589	0
T16	238278	51
T17	59371	0
T18	430405	0
T48	0	1
T49	0	84
T50	257551	51
T78	0	51
T79	0	63
T80	0	76
T81	0	69

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	7147	0	0
SrcPulseCheck_M	9385728	7147	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	7147
T2	887365	65
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	62
T15	128589	0
T16	238278	51
T17	59371	0
T18	430405	0
T48	0	1
T49	0	84
T50	257551	51
T78	0	51
T79	0	63
T80	0	76
T81	0	69

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	7147
T2	21127	65
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	62
T15	494	0
T16	5016	51
T17	457	0
T18	878	0
T48	0	1
T49	0	84
T50	5366	51
T78	0	51
T79	0	63
T80	0	76
T81	0	69

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	7046	0	0
SrcPulseCheck_M	1249995120	7124	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	7046
T2	21127	83
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	73
T15	494	0
T16	5016	51
T17	457	0
T18	878	0
T39	0	69
T49	0	79
T50	5366	51
T78	0	51
T79	0	63
T80	0	76
T81	0	90

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	7124
T2	887365	83
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	73
T15	128589	0
T16	238278	51
T17	59371	0
T18	430405	0
T39	0	69
T49	0	79
T50	257551	51
T78	0	51
T79	0	63
T80	0	76
T81	0	90

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	7114	0	0
SrcPulseCheck_M	9385728	7114	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	7114
T2	887365	83
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	73
T15	128589	0
T16	238278	51
T17	59371	0
T18	430405	0
T39	0	69
T49	0	79
T50	257551	51
T78	0	51
T79	0	63
T80	0	76
T81	0	90

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	7114
T2	21127	83
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	73
T15	494	0
T16	5016	51
T17	457	0
T18	878	0
T39	0	69
T49	0	79
T50	5366	51
T78	0	51
T79	0	63
T80	0	76
T81	0	90

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	7080	0	0
SrcPulseCheck_M	1249995120	7158	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	7080
T2	21127	84
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	64
T15	494	0
T16	5016	51
T17	457	0
T18	878	0
T39	0	60
T49	0	71
T50	5366	51
T78	0	51
T79	0	56
T80	0	76
T81	0	67

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	7158
T2	887365	84
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	64
T15	128589	0
T16	238278	51
T17	59371	0
T18	430405	0
T39	0	60
T49	0	72
T50	257551	51
T78	0	51
T79	0	56
T80	0	76
T81	0	67

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	7148	0	0
SrcPulseCheck_M	9385728	7149	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	7148
T2	887365	84
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	64
T15	128589	0
T16	238278	51
T17	59371	0
T18	430405	0
T39	0	60
T49	0	72
T50	257551	51
T78	0	51
T79	0	56
T80	0	76
T81	0	67

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	7149
T2	21127	84
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	64
T15	494	0
T16	5016	51
T17	457	0
T18	878	0
T39	0	60
T49	0	72
T50	5366	51
T78	0	51
T79	0	56
T80	0	76
T81	0	67

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	6999	0	0
SrcPulseCheck_M	1249995120	7080	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	6999
T2	21127	74
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	79
T15	494	0
T16	5016	51
T17	457	0
T18	878	0
T39	0	80
T49	0	60
T50	5366	51
T78	0	51
T79	0	63
T80	0	51
T81	0	79

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	7080
T2	887365	74
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	79
T15	128589	0
T16	238278	51
T17	59371	0
T18	430405	0
T39	0	80
T49	0	61
T50	257551	51
T78	0	51
T79	0	63
T80	0	51
T81	0	79

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	7069	0	0
SrcPulseCheck_M	9385728	7069	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	7069
T2	887365	74
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	79
T15	128589	0
T16	238278	51
T17	59371	0
T18	430405	0
T39	0	80
T49	0	61
T50	257551	51
T78	0	51
T79	0	63
T80	0	51
T81	0	79

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	7069
T2	21127	74
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	79
T15	494	0
T16	5016	51
T17	457	0
T18	878	0
T39	0	80
T49	0	61
T50	5366	51
T78	0	51
T79	0	63
T80	0	51
T81	0	79

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1209	0	0
SrcPulseCheck_M	1249995120	1285	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1209
T2	21127	6
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T48	0	1
T49	0	11
T50	5366	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1285
T2	887365	6
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T48	0	1
T49	0	11
T50	257551	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1273	0	0
SrcPulseCheck_M	9385728	1273	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1273
T2	887365	6
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T48	0	1
T49	0	11
T50	257551	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1273
T2	21127	6
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T48	0	1
T49	0	11
T50	5366	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1230	0	0
SrcPulseCheck_M	1249995120	1300	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1230
T2	21127	6
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T39	0	3
T49	0	11
T50	5366	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1300
T2	887365	6
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T39	0	3
T49	0	11
T50	257551	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1289	0	0
SrcPulseCheck_M	9385728	1289	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1289
T2	887365	6
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T39	0	3
T49	0	11
T50	257551	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1289
T2	21127	6
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T39	0	3
T49	0	11
T50	5366	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1202	0	0
SrcPulseCheck_M	1249995120	1275	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1202
T2	21127	6
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T39	0	3
T49	0	11
T50	5366	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1275
T2	887365	6
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T39	0	3
T49	0	11
T50	257551	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1265	0	0
SrcPulseCheck_M	9385728	1265	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1265
T2	887365	6
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T39	0	3
T49	0	11
T50	257551	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1265
T2	21127	6
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T39	0	3
T49	0	11
T50	5366	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1232	0	0
SrcPulseCheck_M	1249995120	1304	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1232
T2	21127	6
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T39	0	3
T49	0	11
T50	5366	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1304
T2	887365	6
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T39	0	3
T49	0	11
T50	257551	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T2,T14,T16
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T14,T16
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T14,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1295	0	0
SrcPulseCheck_M	9385728	1295	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1295
T2	887365	6
T3	53463	0
T4	611177	0
T8	156811	0
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T39	0	3
T49	0	11
T50	257551	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1295
T2	21127	6
T3	825	0
T4	25465	0
T8	19601	0
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T39	0	3
T49	0	11
T50	5366	1
T78	0	1
T79	0	6
T80	0	1
T81	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T6,T2,T4
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T2,T14,T16
1	1	Covered	T6,T2,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	7678	0	0
SrcPulseCheck_M	1249995120	7757	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	7678
T1	564982	0
T2	21127	65
T3	825	0
T4	25465	11
T6	435	1
T7	437	0
T8	0	7
T9	0	1
T11	0	9
T14	8467	62
T15	494	0
T16	5016	51
T17	457	0
T35	0	1
T50	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	7757
T1	52767	0
T2	887365	65
T3	53463	0
T4	611177	11
T6	52316	1
T7	52510	0
T8	0	7
T9	0	1
T11	0	9
T14	397958	62
T15	128589	0
T16	238278	51
T17	59371	0
T35	0	1
T50	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T6,T2,T4
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T2,T14,T16
1	1	Covered	T6,T2,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	7748	0	0
SrcPulseCheck_M	9385728	7748	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	7748
T1	52767	0
T2	887365	65
T3	53463	0
T4	611177	11
T6	52316	1
T7	52510	0
T8	0	7
T9	0	1
T11	0	9
T14	397958	62
T15	128589	0
T16	238278	51
T17	59371	0
T35	0	1
T50	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	7748
T1	564982	0
T2	21127	65
T3	825	0
T4	25465	11
T6	435	1
T7	437	0
T8	0	7
T9	0	1
T11	0	9
T14	8467	62
T15	494	0
T16	5016	51
T17	457	0
T35	0	1
T50	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	7586	0	0
SrcPulseCheck_M	1249995120	7666	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	7586
T2	21127	83
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	73
T15	494	0
T16	5016	51
T17	457	0
T18	878	0
T36	0	8
T50	5366	51
T51	0	3
T78	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	7666
T2	887365	83
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	73
T15	128589	0
T16	238278	51
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	51
T51	0	3
T78	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	7655	0	0
SrcPulseCheck_M	9385728	7655	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	7655
T2	887365	83
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	73
T15	128589	0
T16	238278	51
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	51
T51	0	3
T78	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	7655
T2	21127	83
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	73
T15	494	0
T16	5016	51
T17	457	0
T18	878	0
T36	0	8
T50	5366	51
T51	0	3
T78	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	7607	0	0
SrcPulseCheck_M	1249995120	7686	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	7607
T2	21127	84
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	64
T15	494	0
T16	5016	51
T17	457	0
T18	878	0
T36	0	8
T50	5366	51
T51	0	3
T78	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	7686
T2	887365	84
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	64
T15	128589	0
T16	238278	51
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	51
T51	0	3
T78	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	7677	0	0
SrcPulseCheck_M	9385728	7677	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	7677
T2	887365	84
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	64
T15	128589	0
T16	238278	51
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	51
T51	0	3
T78	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	7677
T2	21127	84
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	64
T15	494	0
T16	5016	51
T17	457	0
T18	878	0
T36	0	8
T50	5366	51
T51	0	3
T78	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	7546	0	0
SrcPulseCheck_M	1249995120	7626	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	7546
T2	21127	74
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	79
T15	494	0
T16	5016	51
T17	457	0
T18	878	0
T36	0	8
T50	5366	51
T51	0	3
T78	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	7626
T2	887365	74
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	79
T15	128589	0
T16	238278	51
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	51
T51	0	3
T78	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T2,T14,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T14,T16
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	7617	0	0
SrcPulseCheck_M	9385728	7618	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	7617
T2	887365	74
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	79
T15	128589	0
T16	238278	51
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	51
T51	0	3
T78	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	7618
T2	21127	74
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	79
T15	494	0
T16	5016	51
T17	457	0
T18	878	0
T36	0	8
T50	5366	51
T51	0	3
T78	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T6,T2,T4
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T87,T88,T34
1	1	Covered	T6,T2,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1831	0	0
SrcPulseCheck_M	1249995120	1902	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1831
T1	564982	0
T2	21127	6
T3	825	0
T4	25465	11
T6	435	1
T7	437	0
T8	0	7
T9	0	1
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T35	0	1
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1902
T1	52767	0
T2	887365	6
T3	53463	0
T4	611177	11
T6	52316	1
T7	52510	0
T8	0	7
T9	0	1
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T35	0	1
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T6,T2,T4
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T87,T88,T34
1	1	Covered	T6,T2,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1893	0	0
SrcPulseCheck_M	9385728	1893	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1893
T1	52767	0
T2	887365	6
T3	53463	0
T4	611177	11
T6	52316	1
T7	52510	0
T8	0	7
T9	0	1
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T35	0	1
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1893
T1	564982	0
T2	21127	6
T3	825	0
T4	25465	11
T6	435	1
T7	437	0
T8	0	7
T9	0	1
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T35	0	1
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1732	0	0
SrcPulseCheck_M	1249995120	1800	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1732
T2	21127	6
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T36	0	8
T50	5366	1
T51	0	3
T78	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1800
T2	887365	6
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	1
T51	0	3
T78	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1789	0	0
SrcPulseCheck_M	9385728	1789	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1789
T2	887365	6
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	1
T51	0	3
T78	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1789
T2	21127	6
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T36	0	8
T50	5366	1
T51	0	3
T78	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1757	0	0
SrcPulseCheck_M	1249995120	1826	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1757
T2	21127	6
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T36	0	8
T50	5366	1
T51	0	3
T78	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1826
T2	887365	6
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	1
T51	0	3
T78	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1814	0	0
SrcPulseCheck_M	9385728	1814	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1814
T2	887365	6
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	1
T51	0	3
T78	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1814
T2	21127	6
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T36	0	8
T50	5366	1
T51	0	3
T78	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1724	0	0
SrcPulseCheck_M	1249995120	1793	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1724
T2	21127	6
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T36	0	8
T50	5366	1
T51	0	3
T78	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1793
T2	887365	6
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	1
T51	0	3
T78	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1784	0	0
SrcPulseCheck_M	9385728	1784	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1784
T2	887365	6
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	1
T51	0	3
T78	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1784
T2	21127	6
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T36	0	8
T50	5366	1
T51	0	3
T78	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T6,T2,T4
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T87,T88,T34
1	1	Covered	T6,T2,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1839	0	0
SrcPulseCheck_M	1249995120	1910	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1839
T1	564982	0
T2	21127	6
T3	825	0
T4	25465	11
T6	435	1
T7	437	0
T8	0	7
T9	0	1
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T35	0	1
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1910
T1	52767	0
T2	887365	6
T3	53463	0
T4	611177	11
T6	52316	1
T7	52510	0
T8	0	7
T9	0	1
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T35	0	1
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T6,T2,T4
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6,T2,T4
1	0	Covered	T87,T88,T34
1	1	Covered	T6,T2,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1902	0	0
SrcPulseCheck_M	9385728	1902	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1902
T1	52767	0
T2	887365	6
T3	53463	0
T4	611177	11
T6	52316	1
T7	52510	0
T8	0	7
T9	0	1
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T35	0	1
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1902
T1	564982	0
T2	21127	6
T3	825	0
T4	25465	11
T6	435	1
T7	437	0
T8	0	7
T9	0	1
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T35	0	1
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1760	0	0
SrcPulseCheck_M	1249995120	1831	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1760
T2	21127	6
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T36	0	8
T50	5366	1
T51	0	3
T78	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1831
T2	887365	6
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	1
T51	0	3
T78	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1821	0	0
SrcPulseCheck_M	9385728	1821	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1821
T2	887365	6
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	1
T51	0	3
T78	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1821
T2	21127	6
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T36	0	8
T50	5366	1
T51	0	3
T78	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1751	0	0
SrcPulseCheck_M	1249995120	1820	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1751
T2	21127	6
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T36	0	8
T50	5366	1
T51	0	3
T78	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1820
T2	887365	6
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	1
T51	0	3
T78	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1809	0	0
SrcPulseCheck_M	9385728	1810	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1809
T2	887365	6
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	1
T51	0	3
T78	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1810
T2	21127	6
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T36	0	8
T50	5366	1
T51	0	3
T78	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9385728	1739	0	0
SrcPulseCheck_M	1249995120	1811	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9385728	1739
T2	21127	6
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T36	0	8
T50	5366	1
T51	0	3
T78	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1249995120	1811
T2	887365	6
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	1
T51	0	3
T78	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14
1	1	Covered	T87,T88,T34

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T14
1	0	Covered	T87,T88,T34
1	1	Covered	T2,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1249995120	1800	0	0
SrcPulseCheck_M	9385728	1800	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1249995120	1800
T2	887365	6
T3	53463	0
T4	611177	10
T8	156811	7
T11	0	9
T14	397958	2
T15	128589	0
T16	238278	1
T17	59371	0
T18	430405	0
T36	0	8
T50	257551	1
T51	0	3
T78	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9385728	1800
T2	21127	6
T3	825	0
T4	25465	10
T8	19601	7
T11	0	9
T14	8467	2
T15	494	0
T16	5016	1
T17	457	0
T18	878	0
T36	0	8
T50	5366	1
T51	0	3
T78	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc