Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
89.02	89.02	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	89.02	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.02	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	9	53	85.48

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	9	22	70.97	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1934

1

T2

6

T3

4

T6

21

auto[1]

639

1

T2

16

T6

3

T7

7

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2024

1

T2

17

T3

3

T6

15

auto[1]

549

1

T2

5

T3

1

T6

9

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1942

1

T2

14

T3

4

T6

12

auto[1]

631

1

T2

8

T6

12

T7

12

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1940

1

T2

11

T3

3

T6

15

auto[1]

633

1

T2

11

T3

1

T6

9

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2408

1

T2

22

T3

4

T6

18

auto[1]

165

1

T6

6

T42

4

T75

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2297

1

T2

22

T3

4

T6

18

auto[1]

276

1

T6

6

T12

2

T42

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2396

1

T2

22

T3

4

T6

21

auto[1]

177

1

T6

3

T7

2

T12

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2334

1

T2

22

T3

4

T6

24

auto[1]

239

1

T7

7

T75

2

T77

7

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2372

1

T2

22

T3

3

T6

24

auto[1]

201

1

T3

1

T7

7

T42

4

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1948

1

T2

8

T3

4

T6

15

auto[1]

625

1

T2

14

T6

9

T8

21

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	9	22	70.97	9
Automatically Generated Cross Bins	31	9	22	70.97	9
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	840	1			T2	22		T8	24		T83	17
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	39	1			T6	6		T42	4		T75	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	63	1			T3	1		T7	5		T42	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	20	1			T378	2		T220	8		T86	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	78	1			T7	7		T75	2		T77	7
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	32	1			T243	2		T89	4		T381	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	10	1			T258	4		T382	3		T383	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	3	1			T220	3		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	41	1			T6	3		T41	9		T259	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	21	1			T258	4		T384	4		T160	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	26	1			T7	2		T257	6		T385	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	21	1			T257	6		T378	1		T386	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	4	1			T387	3		T236	1		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	8	1			T379	1		T380	7		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	116	1			T6	6		T42	2		T98	4
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	12	1			T86	2		T388	3		T389	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	36	1			T280	6		T390	2		T391	4
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	46	1			T97	7		T381	2		T388	3
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	1	1			T160	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	30	1			T12	2		T97	7		T392	7
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	2	1			T77	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	2	1			T220	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

127

1

T7

2

T42

4

T97

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

126

1

T8

13

T42

2

T257

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

79

1

T2

11

T75

2

T77

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

90

1

T84

9

T243

4

T376

12

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

54

1

T260

2

T257

6

T372

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

62

1

T8

6

T12

2

T41

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

31

1

T373

5

T393

3

T259

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

114

1

T7

7

T83

9

T351

18

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

50

1

T7

5

T271

6

T284

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

37

1

T6

6

T103

2

T348

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

37

1

T393

1

T282

1

T375

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

100

1

T2

6

T84

5

T271

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

29

1

T8

3

T285

8

T394

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21

1

T93

1

T373

1

T395

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T271

2

T376

4

T277

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

75

1

T83

8

T35

2

T258

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T268

1

T84

8

T121

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

70

1

T55

2

T243

2

T257

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

37

1

T41

3

T54

3

T84

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T3

1

T258

4

T104

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T41

3

T372

1

T151

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

22

1

T42

4

T253

2

T374

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T2

3

T6

3

T259

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

36

1

T268

1

T91

1

T253

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

32

1

T258

4

T223

3

T375

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T8

2

T75

1

T373

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T396

1

T210

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

24

1

T6

6

T54

2

T84

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T2

2

T253

1

T223

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

12

1

T223

2

T396

2

T395

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T108

2

T397

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded