Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T4

11

T1

11

T5

13

auto[1]

1135

1

T4

9

T1

9

T5

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

527

1

T4

3

T1

4

T5

6

from_0to1

522

1

T4

3

T1

4

T5

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1077

1

T4

12

T1

13

T5

10

auto[1]

1168

1

T4

8

T1

7

T5

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T4

10

T1

10

T5

10

auto[1]

1124

1

T4

10

T1

10

T5

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T4

1

T5

2

T11

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T1

1

T5

2

T68

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T4

1

T1

1

T5

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T4

1

T1

1

T5

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T4

1

T1

1

T5

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T4

1

T5

1

T11

2

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T5

1

T11

4

T67

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T4

1

T11

3

T67

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T1

1

T11

2

T68

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T11

2

T47

1

T37

2

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T11

1

T67

2

T60

2

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T11

5

T67

1

T68

2

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T5

1

T11

1

T133

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T1

2

T5

1

T70

1

auto[1]

from_0to1

auto[1]

auto[0]

79

1

T1

1

T5

1

T68

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T67

1

T68

1

T47

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T4

11

T1

8

T5

10

auto[1]

1149

1

T4

9

T1

12

T5

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

535

1

T4

5

T1

4

T5

3

from_0to1

540

1

T4

6

T1

5

T5

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T4

9

T1

10

T5

14

auto[1]

1153

1

T4

11

T1

10

T5

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T4

9

T1

14

T5

10

auto[1]

1146

1

T4

11

T1

6

T5

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T4

1

T67

1

T68

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T4

1

T5

2

T11

3

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T11

1

T70

3

T60

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T4

1

T60

1

T133

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T68

2

T70

1

T56

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T4

1

T5

1

T11

3

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T4

1

T11

2

T67

2

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T4

1

T37

1

T35

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T4

1

T5

1

T11

2

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T4

1

T1

1

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T1

1

T11

1

T70

1

auto[1]

from_1to0

auto[1]

auto[1]

80

1

T1

2

T11

2

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T1

3

T67

1

T70

2

auto[1]

from_0to1

auto[0]

auto[1]

50

1

T5

1

T68

1

T70

1

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T4

2

T1

2

T11

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T4

1

T5

2

T11

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1137

1

T4

12

T1

7

T5

9

auto[1]

1108

1

T4

8

T1

13

T5

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T4

4

T1

4

T5

5

from_0to1

540

1

T4

3

T1

4

T5

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1167

1

T4

8

T1

12

T5

12

auto[1]

1078

1

T4

12

T1

8

T5

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T4

10

T1

5

T5

11

auto[1]

1145

1

T4

10

T1

15

T5

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T4

1

T1

2

T5

2

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T1

1

T47

1

T133

3

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T4

2

T5

1

T11

1

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T68

1

T70

1

T133

1

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T5

1

T67

2

T47

1

auto[0]

from_0to1

auto[0]

auto[1]

81

1

T4

1

T5

1

T11

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T4

2

T11

2

T70

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T5

1

T11

2

T68

2

auto[1]

from_1to0

auto[0]

auto[0]

77

1

T11

1

T67

1

T70

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T5

1

T11

1

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T5

1

T11

2

T67

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T4

1

T1

1

T11

2

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T67

2

T68

2

T70

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T1

1

T5

2

T67

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T1

1

T5

1

T11

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T1

2

T11

2

T68

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1135

1

T4

11

T1

10

T5

10

auto[1]

1110

1

T4

9

T1

10

T5

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

541

1

T4

4

T1

5

T5

3

from_0to1

541

1

T4

4

T1

6

T5

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T4

11

T1

7

T5

11

auto[1]

1120

1

T4

9

T1

13

T5

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1168

1

T4

10

T1

7

T5

5

auto[1]

1077

1

T4

10

T1

13

T5

15

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

81

1

T4

1

T1

1

T11

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T11

2

T60

2

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T4

1

T11

2

T68

1

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T1

2

T5

1

T67

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T67

1

T70

2

T133

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T4

1

T1

1

T11

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T4

1

T1

2

T60

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T4

1

T5

2

T11

3

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T4

1

T68

1

T70

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T1

1

T5

1

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T4

1

T1

1

T11

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T5

1

T11

2

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

81

1

T11

1

T68

1

T60

2

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T1

1

T5

2

T11

2

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T4

1

T1

1

T67

1

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T1

1

T11

2

T67

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1124

1

T4

9

T1

11

T5

11

auto[1]

1121

1

T4

11

T1

9

T5

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

537

1

T4

5

T1

5

T5

4

from_0to1

527

1

T4

5

T1

6

T5

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T4

7

T1

14

T5

10

auto[1]

1149

1

T4

13

T1

6

T5

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1123

1

T4

11

T1

7

T5

7

auto[1]

1122

1

T4

9

T1

13

T5

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T4

1

T1

1

T11

7

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T1

2

T67

1

T60

2

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T4

1

T5

1

T11

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T1

1

T5

1

T11

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T4

1

T1

2

T11

2

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T1

1

T11

1

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T5

1

T11

2

T68

2

auto[0]

from_0to1

auto[1]

auto[1]

84

1

T4

1

T5

1

T11

3

auto[1]

from_1to0

auto[0]

auto[0]

81

1

T4

1

T11

1

T68

2

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T1

1

T5

1

T11

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T4

1

T67

1

T68

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T4

1

T5

1

T70

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T4

1

T1

1

T5

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T4

1

T1

2

T67

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T4

1

T11

2

T60

2

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T5

1

T11

1

T68

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1115

1

T4

9

T1

13

T5

5

auto[1]

1130

1

T4

11

T1

7

T5

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

535

1

T4

5

T1

7

T5

5

from_0to1

516

1

T4

5

T1

7

T5

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1105

1

T4

5

T1

12

T5

10

auto[1]

1140

1

T4

15

T1

8

T5

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1102

1

T4

9

T1

10

T5

14

auto[1]

1143

1

T4

11

T1

10

T5

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T1

1

T68

1

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T1

2

T68

1

T70

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T4

1

T1

1

T5

2

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T4

2

T11

2

T70

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T68

1

T70

1

T60

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T4

1

T1

3

T11

3

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T1

1

T11

1

T67

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T11

1

T67

1

T68

2

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T1

1

T5

1

T11

3

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T1

1

T11

1

T67

3

auto[1]

from_1to0

auto[1]

auto[0]

79

1

T4

2

T5

1

T68

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T1

1

T5

1

T11

2

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T1

1

T5

1

T11

2

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T4

1

T5

1

T11

3

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T4

1

T1

2

T5

2

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T4

2

T5

2

T11

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T4

8

T1

12

T5

7

auto[1]

1112

1

T4

12

T1

8

T5

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

515

1

T4

6

T1

3

T5

4

from_0to1

518

1

T4

5

T1

3

T5

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T4

9

T1

11

T5

7

auto[1]

1116

1

T4

11

T1

9

T5

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1156

1

T4

11

T1

11

T5

10

auto[1]

1089

1

T4

9

T1

9

T5

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T1

1

T11

3

T68

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T4

1

T1

1

T68

2

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T4

1

T11

1

T67

2

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T1

1

T11

2

T133

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T1

2

T5

1

T47

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T4

1

T11

4

T68

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T1

1

T133

2

T37

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T5

1

T67

2

T68

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T5

1

T67

2

T68

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T4

1

T11

1

T70

2

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T4

2

T5

1

T11

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T4

1

T5

2

T11

3

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T4

3

T68

1

T70

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T11

3

T68

2

T70

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T4

1

T11

1

T67

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T5

1

T11

3

T202

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1137

1

T4

13

T1

9

T5

12

auto[1]

1108

1

T4

7

T1

11

T5

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

517

1

T4

5

T1

3

T5

5

from_0to1

520

1

T4

4

T1

2

T5

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1142

1

T4

9

T1

12

T5

8

auto[1]

1103

1

T4

11

T1

8

T5

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T4

13

T1

13

T5

9

auto[1]

1105

1

T4

7

T1

7

T5

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T4

1

T1

1

T11

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T1

1

T5

2

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T4

1

T11

3

T68

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T4

1

T5

2

T67

2

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T4

1

T1

1

T11

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T11

1

T67

1

T68

1

auto[0]

from_0to1

auto[1]

auto[0]

77

1

T4

3

T1

1

T70

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T5

2

T11

1

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T4

1

T11

1

T68

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T4

1

T1

1

T5

1

auto[1]

from_1to0

auto[1]

auto[0]

51

1

T11

3

T67

1

T60

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T67

1

T68

1

T70

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T11

1

T70

1

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T5

1

T11

1

T67

2

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T11

1

T60

1

T47

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T5

1

T11

1

T67

1