Group : sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg
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Group : sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
54.55 54.55 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_wkup_event_cg 54.55 1 100 1 64 64




Group Instance : sysrst_ctrl_wkup_event_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
54.55 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_wkup_event_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 23 15 8 34.78


Variables for Group Instance sysrst_ctrl_wkup_event_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_h2l_pwrb 2 0 2 100.00 100 1 1 2
cp_h_ac_present 2 0 2 100.00 100 1 1 2
cp_interrupt_gen 2 0 2 100.00 100 1 1 2
cp_l2h_lid_open 2 0 2 100.00 100 1 1 2
cp_wakeup_sts 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_wkup_event_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_wkup_sts 23 15 8 34.78 100 1 1 0


Summary for Variable cp_h2l_pwrb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_h2l_pwrb

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 839 1 T4 1 T1 2 T5 2
auto[1] 679 1 T4 1 T1 2 T5 2



Summary for Variable cp_h_ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_h_ac_present

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 963 1 T4 1 T1 1 T5 2
auto[1] 555 1 T4 1 T1 3 T5 2



Summary for Variable cp_interrupt_gen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_interrupt_gen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1517 1 T4 2 T1 4 T5 4
auto[1] 1 1 T30 1 - - - -



Summary for Variable cp_l2h_lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_l2h_lid_open

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 951 1 T4 1 T1 2 T5 2
auto[1] 567 1 T4 1 T1 2 T5 2



Summary for Variable cp_wakeup_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_wakeup_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1452 1 T4 2 T1 4 T5 4
auto[1] 66 1 T23 1 T24 1 T35 1



Summary for Cross cross_wkup_sts

Samples crossed: cp_wakeup_sts cp_h2l_pwrb cp_l2h_lid_open cp_h_ac_present cp_interrupt_gen
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 23 15 8 34.78 15
Automatically Generated Cross Bins 23 15 8 34.78 15
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_wkup_sts

Element holes
cp_wakeup_stscp_h2l_pwrbcp_l2h_lid_opencp_h_ac_presentcp_interrupt_genCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] * * * -- -- 8
[auto[1]] [auto[1]] [auto[0]] [auto[1]] * -- -- 2
[auto[1]] [auto[1]] [auto[1]] * * -- -- 4


Uncovered bins
cp_wakeup_stscp_h2l_pwrbcp_l2h_lid_opencp_h_ac_presentcp_interrupt_genCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_wakeup_stscp_h2l_pwrbcp_l2h_lid_opencp_h_ac_presentcp_interrupt_genCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 369 1 T1 1 T25 1 T11 1
auto[0] auto[0] auto[0] auto[1] auto[0] 151 1 T5 1 T67 1 T68 1
auto[0] auto[0] auto[1] auto[0] auto[0] 171 1 T5 1 T16 1 T25 3
auto[0] auto[0] auto[1] auto[1] auto[0] 147 1 T4 1 T1 1 T16 2
auto[0] auto[1] auto[0] auto[0] auto[0] 221 1 T4 1 T16 1 T11 1
auto[0] auto[1] auto[0] auto[1] auto[0] 143 1 T1 1 T5 1 T16 2
auto[0] auto[1] auto[1] auto[0] auto[0] 135 1 T5 1 T25 1 T67 1
auto[0] auto[1] auto[1] auto[1] auto[0] 114 1 T1 1 T70 1 T65 1


User Defined Cross Bins for cross_wkup_sts

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded

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