Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150542	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113779

1

T4

42

T1

101

T5

49

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136286	1			T4	62		T1	85		T5	62
values[0x0]	63548	1			T4	30		T1	90		T5	39
values[0x1]	64487	1			T4	31		T1	102		T5	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	121560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

142761

1

T4

55

T1

131

T5

63

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	789	1			T5	1		T6	3		T7	8
valid_sources[0x01]	789	1			T13	1		T7	5		T8	2
valid_sources[0x02]	823	1			T6	3		T7	3		T8	4
valid_sources[0x03]	787	1			T7	1		T8	6		T10	1
valid_sources[0x04]	1607	1			T1	4		T2	15		T6	2
valid_sources[0x05]	1052	1			T1	10		T6	3		T7	2
valid_sources[0x06]	708	1			T1	1		T6	3		T8	2
valid_sources[0x07]	839	1			T6	1		T7	8		T8	6
valid_sources[0x08]	897	1			T1	3		T6	2		T29	1
valid_sources[0x09]	891	1			T1	3		T14	1		T6	9
valid_sources[0x0a]	1897	1			T5	6		T6	1		T7	2
valid_sources[0x0b]	915	1			T1	1		T14	1		T6	1
valid_sources[0x0c]	810	1			T1	1		T6	4		T7	4
valid_sources[0x0d]	920	1			T6	9		T7	3		T8	2
valid_sources[0x0e]	915	1			T16	6		T6	3		T25	2
valid_sources[0x0f]	794	1			T5	1		T6	1		T8	1
valid_sources[0x10]	854	1			T5	1		T6	5		T7	5
valid_sources[0x11]	812	1			T6	4		T7	2		T8	1
valid_sources[0x12]	851	1			T14	3		T6	4		T7	2
valid_sources[0x13]	934	1			T6	3		T7	4		T8	1
valid_sources[0x14]	750	1			T1	4		T14	1		T6	6
valid_sources[0x15]	1071	1			T1	1		T6	3		T8	3
valid_sources[0x16]	1763	1			T6	3		T7	6		T8	2
valid_sources[0x17]	1019	1			T5	2		T8	1		T12	9
valid_sources[0x18]	907	1			T6	8		T7	7		T8	3
valid_sources[0x19]	1370	1			T1	2		T2	19		T6	3
valid_sources[0x1a]	870	1			T6	3		T7	5		T8	3
valid_sources[0x1b]	1010	1			T1	6		T6	9		T7	5
valid_sources[0x1c]	928	1			T1	1		T6	3		T7	6
valid_sources[0x1d]	928	1			T6	4		T7	2		T8	6
valid_sources[0x1e]	778	1			T1	2		T5	2		T6	3
valid_sources[0x1f]	1294	1			T5	2		T6	3		T29	1
valid_sources[0x20]	1979	1			T1	2		T6	3		T7	3
valid_sources[0x21]	1267	1			T5	1		T6	2		T7	5
valid_sources[0x22]	830	1			T1	1		T14	1		T6	2
valid_sources[0x23]	751	1			T6	1		T7	6		T8	4
valid_sources[0x24]	1119	1			T1	2		T6	5		T7	8
valid_sources[0x25]	2218	1			T1	3		T2	13		T3	804
valid_sources[0x26]	964	1			T14	1		T6	5		T7	1
valid_sources[0x27]	795	1			T6	7		T7	7		T8	4
valid_sources[0x28]	1237	1			T6	9		T7	2		T8	4
valid_sources[0x29]	913	1			T1	5		T6	4		T7	2
valid_sources[0x2a]	866	1			T1	1		T6	9		T7	2
valid_sources[0x2b]	999	1			T6	7		T7	10		T8	2
valid_sources[0x2c]	1034	1			T6	4		T7	1		T8	4
valid_sources[0x2d]	991	1			T1	1		T5	1		T2	34
valid_sources[0x2e]	1707	1			T1	3		T2	6		T6	2
valid_sources[0x2f]	892	1			T6	4		T7	16		T8	2
valid_sources[0x30]	828	1			T1	1		T6	2		T7	1
valid_sources[0x31]	853	1			T5	1		T6	5		T7	7
valid_sources[0x32]	996	1			T1	1		T6	4		T7	3
valid_sources[0x33]	874	1			T1	1		T6	3		T7	2
valid_sources[0x34]	833	1			T1	1		T6	5		T8	3
valid_sources[0x35]	982	1			T1	2		T6	13		T7	12
valid_sources[0x36]	860	1			T2	1		T6	1		T7	3
valid_sources[0x37]	784	1			T1	1		T5	1		T6	3
valid_sources[0x38]	808	1			T1	1		T6	4		T7	4
valid_sources[0x39]	797	1			T6	8		T7	6		T8	2
valid_sources[0x3a]	800	1			T6	8		T7	8		T12	7
valid_sources[0x3b]	994	1			T1	1		T6	3		T49	2
valid_sources[0x3c]	1075	1			T1	4		T6	4		T7	6
valid_sources[0x3d]	2274	1			T1	2		T6	1		T7	4
valid_sources[0x3e]	896	1			T1	3		T5	2		T6	8
valid_sources[0x3f]	747	1			T1	3		T6	7		T7	1
valid_sources[0x40]	870	1			T5	1		T6	1		T7	10
valid_sources[0x41]	912	1			T5	1		T2	10		T6	10
valid_sources[0x42]	856	1			T6	5		T7	3		T8	2
valid_sources[0x43]	974	1			T1	2		T6	1		T29	1
valid_sources[0x44]	1835	1			T6	1		T7	2		T8	4
valid_sources[0x45]	910	1			T1	2		T6	9		T7	11
valid_sources[0x46]	1037	1			T4	123		T1	5		T2	14
valid_sources[0x47]	875	1			T6	4		T28	3		T7	8
valid_sources[0x48]	939	1			T1	1		T5	1		T7	9
valid_sources[0x49]	947	1			T6	9		T7	8		T8	3
valid_sources[0x4a]	1168	1			T13	1		T2	1		T6	2
valid_sources[0x4b]	1419	1			T1	1		T6	3		T28	1
valid_sources[0x4c]	763	1			T1	2		T6	7		T7	5
valid_sources[0x4d]	774	1			T1	1		T6	6		T28	1
valid_sources[0x4e]	2467	1			T6	4		T7	6		T8	1
valid_sources[0x4f]	755	1			T1	1		T6	5		T29	1
valid_sources[0x50]	944	1			T1	1		T5	3		T2	5
valid_sources[0x51]	1681	1			T1	2		T14	2		T6	2
valid_sources[0x52]	808	1			T2	37		T6	3		T7	6
valid_sources[0x53]	684	1			T1	1		T6	1		T8	3
valid_sources[0x54]	859	1			T1	2		T2	4		T14	2
valid_sources[0x55]	767	1			T6	4		T7	7		T8	2
valid_sources[0x56]	1963	1			T1	4		T5	3		T16	2
valid_sources[0x57]	791	1			T1	1		T6	2		T7	4
valid_sources[0x58]	870	1			T1	2		T2	24		T6	8
valid_sources[0x59]	882	1			T14	1		T6	3		T7	5
valid_sources[0x5a]	1723	1			T1	1		T2	14		T6	1
valid_sources[0x5b]	1429	1			T6	4		T7	4		T8	3
valid_sources[0x5c]	909	1			T1	4		T50	3		T7	4
valid_sources[0x5d]	1697	1			T6	1		T7	5		T8	3
valid_sources[0x5e]	1050	1			T2	6		T25	10		T7	3
valid_sources[0x5f]	1193	1			T1	4		T6	2		T7	5
valid_sources[0x60]	1692	1			T1	1		T5	2		T6	6
valid_sources[0x61]	1039	1			T1	2		T5	1		T6	4
valid_sources[0x62]	978	1			T1	1		T6	2		T7	11
valid_sources[0x63]	867	1			T1	1		T6	6		T7	2
valid_sources[0x64]	875	1			T7	5		T8	4		T68	1
valid_sources[0x65]	869	1			T1	1		T6	1		T29	1
valid_sources[0x66]	946	1			T6	11		T7	5		T8	3
valid_sources[0x67]	1399	1			T1	1		T6	1		T7	5
valid_sources[0x68]	1093	1			T1	1		T6	5		T7	3
valid_sources[0x69]	914	1			T1	2		T6	2		T7	5
valid_sources[0x6a]	814	1			T1	1		T5	6		T6	5
valid_sources[0x6b]	783	1			T1	1		T5	1		T14	1
valid_sources[0x6c]	858	1			T6	6		T7	9		T51	4
valid_sources[0x6d]	772	1			T1	1		T2	25		T6	1
valid_sources[0x6e]	1900	1			T1	1		T6	1		T8	2
valid_sources[0x6f]	732	1			T1	2		T6	5		T7	2
valid_sources[0x70]	980	1			T1	4		T6	2		T7	3
valid_sources[0x71]	1157	1			T6	3		T7	4		T12	1
valid_sources[0x72]	935	1			T6	4		T29	1		T7	2
valid_sources[0x73]	956	1			T1	1		T6	2		T7	10
valid_sources[0x74]	1007	1			T1	2		T6	7		T7	3
valid_sources[0x75]	854	1			T1	1		T5	3		T6	4
valid_sources[0x76]	919	1			T5	1		T2	2		T6	1
valid_sources[0x77]	890	1			T1	1		T6	4		T8	2
valid_sources[0x78]	814	1			T1	1		T6	7		T7	5
valid_sources[0x79]	1303	1			T1	1		T6	6		T7	2
valid_sources[0x7a]	783	1			T5	1		T6	1		T7	7
valid_sources[0x7b]	1028	1			T1	2		T13	1		T6	6
valid_sources[0x7c]	1276	1			T5	1		T6	4		T7	8
valid_sources[0x7d]	837	1			T1	1		T6	9		T7	7
valid_sources[0x7e]	929	1			T16	36		T6	7		T7	3
valid_sources[0x7f]	965	1			T6	8		T7	1		T8	2
valid_sources[0x80]	715	1			T1	3		T6	4		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61445

1

T4

28

T1

48

T5

30

values[0x0]

all_enables

biggest_size

30808

1

T4

13

T1

31

T5

16

values[0x1]

all_enables

biggest_size

21526

1

T4

1

T1

22

T5

3