Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1086762458	9327	0	0
auto_block_debounce_ctl_rd_A	1086762458	2554	0	0
auto_block_out_ctl_rd_A	1086762458	3801	0	0
com_det_ctl_0_rd_A	1086762458	3933	0	0
com_det_ctl_1_rd_A	1086762458	4277	0	0
com_det_ctl_2_rd_A	1086762458	4143	0	0
com_det_ctl_3_rd_A	1086762458	4340	0	0
com_out_ctl_0_rd_A	1086762458	5208	0	0
com_out_ctl_1_rd_A	1086762458	5131	0	0
com_out_ctl_2_rd_A	1086762458	5079	0	0
com_out_ctl_3_rd_A	1086762458	5005	0	0
com_pre_det_ctl_0_rd_A	1086762458	2100	0	0
com_pre_det_ctl_1_rd_A	1086762458	1827	0	0
com_pre_det_ctl_2_rd_A	1086762458	1942	0	0
com_pre_det_ctl_3_rd_A	1086762458	1927	0	0
com_pre_sel_ctl_0_rd_A	1086762458	5151	0	0
com_pre_sel_ctl_1_rd_A	1086762458	5460	0	0
com_pre_sel_ctl_2_rd_A	1086762458	5204	0	0
com_pre_sel_ctl_3_rd_A	1086762458	5424	0	0
com_sel_ctl_0_rd_A	1086762458	5479	0	0
com_sel_ctl_1_rd_A	1086762458	5639	0	0
com_sel_ctl_2_rd_A	1086762458	5556	0	0
com_sel_ctl_3_rd_A	1086762458	4990	0	0
ec_rst_ctl_rd_A	1086762458	2778	0	0
intr_enable_rd_A	1086762458	2727	0	0
key_intr_ctl_rd_A	1086762458	6364	0	0
key_intr_debounce_ctl_rd_A	1086762458	1862	0	0
key_invert_ctl_rd_A	1086762458	6463	0	0
pin_allowed_ctl_rd_A	1086762458	7997	0	0
pin_out_ctl_rd_A	1086762458	5483	0	0
pin_out_value_rd_A	1086762458	5949	0	0
regwen_rd_A	1086762458	1980	0	0
ulp_ac_debounce_ctl_rd_A	1086762458	2081	0	0
ulp_ctl_rd_A	1086762458	2084	0	0
ulp_lid_debounce_ctl_rd_A	1086762458	2075	0	0
ulp_pwrb_debounce_ctl_rd_A	1086762458	2116	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	9327	0	0
T24	0	5	0	0
T35	0	13	0	0
T37	0	10	0	0
T44	763133	4	0	0
T45	101729	0	0	0
T53	0	14	0	0
T55	0	1	0	0
T56	0	19	0	0
T63	223523	0	0	0
T64	61634	0	0	0
T65	246118	0	0	0
T71	42454	0	0	0
T72	75697	0	0	0
T79	0	2	0	0
T91	0	24	0	0
T93	0	12	0	0
T321	205832	0	0	0
T322	28873	0	0	0
T323	162924	0	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	2554	0	0
T24	0	36	0	0
T44	763133	6	0	0
T45	101729	0	0	0
T54	0	7	0	0
T63	223523	0	0	0
T64	61634	0	0	0
T65	246118	0	0	0
T71	42454	0	0	0
T72	75697	0	0	0
T84	0	18	0	0
T87	0	20	0	0
T111	0	5	0	0
T124	0	26	0	0
T226	0	2	0	0
T321	205832	0	0	0
T322	28873	0	0	0
T323	162924	0	0	0
T324	0	2	0	0
T325	0	43	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	3801	0	0
T24	0	48	0	0
T44	763133	20	0	0
T45	101729	0	0	0
T46	0	6	0	0
T54	0	3	0	0
T63	223523	0	0	0
T64	61634	0	0	0
T65	246118	0	0	0
T71	42454	0	0	0
T72	75697	0	0	0
T84	0	18	0	0
T96	0	7	0	0
T111	0	13	0	0
T124	0	16	0	0
T321	205832	0	0	0
T322	28873	0	0	0
T323	162924	0	0	0
T324	0	8	0	0
T325	0	50	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	3933	0	0
T2	305103	53	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	63	0	0
T12	0	37	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	30	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T44	0	20	0	0
T49	25153	0	0	0
T54	0	30	0	0
T75	0	44	0	0
T84	0	121	0	0
T243	0	62	0	0
T268	0	41	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	4277	0	0
T2	305103	46	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	27	0	0
T12	0	44	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	27	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T44	0	14	0	0
T49	25153	0	0	0
T54	0	53	0	0
T75	0	46	0	0
T84	0	130	0	0
T243	0	62	0	0
T268	0	50	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	4143	0	0
T2	305103	66	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	34	0	0
T12	0	51	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	31	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T44	0	4	0	0
T49	25153	0	0	0
T54	0	21	0	0
T75	0	47	0	0
T84	0	146	0	0
T243	0	69	0	0
T268	0	26	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	4340	0	0
T2	305103	79	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	20	0	0
T12	0	45	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	24	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T44	0	9	0	0
T49	25153	0	0	0
T54	0	27	0	0
T75	0	50	0	0
T84	0	130	0	0
T243	0	42	0	0
T268	0	33	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	5208	0	0
T2	305103	88	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	49	0	0
T12	0	34	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	36	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T44	0	5	0	0
T49	25153	0	0	0
T54	0	25	0	0
T75	0	58	0	0
T84	0	131	0	0
T243	0	69	0	0
T268	0	42	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	5131	0	0
T2	305103	64	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	20	0	0
T12	0	35	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	44	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T44	0	6	0	0
T49	25153	0	0	0
T54	0	58	0	0
T75	0	44	0	0
T84	0	103	0	0
T243	0	37	0	0
T268	0	27	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	5079	0	0
T2	305103	77	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	16	0	0
T12	0	49	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	48	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T44	0	12	0	0
T49	25153	0	0	0
T54	0	51	0	0
T75	0	33	0	0
T84	0	164	0	0
T243	0	58	0	0
T268	0	32	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	5005	0	0
T2	305103	93	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	22	0	0
T12	0	29	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	31	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T49	25153	0	0	0
T54	0	31	0	0
T75	0	63	0	0
T84	0	118	0	0
T243	0	55	0	0
T257	0	35	0	0
T268	0	42	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	2100	0	0
T24	0	24	0	0
T44	763133	17	0	0
T45	101729	0	0	0
T63	223523	0	0	0
T64	61634	0	0	0
T65	246118	0	0	0
T71	42454	0	0	0
T72	75697	0	0	0
T87	0	20	0	0
T124	0	13	0	0
T231	0	24	0	0
T321	205832	0	0	0
T322	28873	0	0	0
T323	162924	0	0	0
T325	0	10	0	0
T326	0	11	0	0
T327	0	6	0	0
T328	0	13	0	0
T329	0	10	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	1827	0	0
T24	0	23	0	0
T44	763133	6	0	0
T45	101729	0	0	0
T63	223523	0	0	0
T64	61634	0	0	0
T65	246118	0	0	0
T71	42454	0	0	0
T72	75697	0	0	0
T87	0	10	0	0
T124	0	19	0	0
T231	0	18	0	0
T321	205832	0	0	0
T322	28873	0	0	0
T323	162924	0	0	0
T325	0	28	0	0
T326	0	18	0	0
T327	0	3	0	0
T328	0	12	0	0
T329	0	8	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	1942	0	0
T24	0	15	0	0
T44	763133	10	0	0
T45	101729	0	0	0
T63	223523	0	0	0
T64	61634	0	0	0
T65	246118	0	0	0
T71	42454	0	0	0
T72	75697	0	0	0
T87	0	16	0	0
T124	0	20	0	0
T145	0	32	0	0
T231	0	11	0	0
T321	205832	0	0	0
T322	28873	0	0	0
T323	162924	0	0	0
T325	0	48	0	0
T326	0	17	0	0
T327	0	17	0	0
T328	0	25	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	1927	0	0
T24	0	23	0	0
T44	763133	16	0	0
T45	101729	0	0	0
T63	223523	0	0	0
T64	61634	0	0	0
T65	246118	0	0	0
T71	42454	0	0	0
T72	75697	0	0	0
T87	0	15	0	0
T124	0	12	0	0
T145	0	12	0	0
T231	0	18	0	0
T321	205832	0	0	0
T322	28873	0	0	0
T323	162924	0	0	0
T325	0	14	0	0
T326	0	14	0	0
T327	0	5	0	0
T328	0	23	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	5151	0	0
T2	305103	82	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	30	0	0
T12	0	35	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	44	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T44	0	5	0	0
T49	25153	0	0	0
T54	0	41	0	0
T75	0	50	0	0
T84	0	154	0	0
T243	0	74	0	0
T268	0	36	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	5460	0	0
T2	305103	66	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	33	0	0
T12	0	45	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	46	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T49	25153	0	0	0
T54	0	19	0	0
T75	0	50	0	0
T84	0	138	0	0
T243	0	72	0	0
T257	0	38	0	0
T268	0	41	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	5204	0	0
T2	305103	66	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	31	0	0
T12	0	29	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	39	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T44	0	12	0	0
T49	25153	0	0	0
T54	0	35	0	0
T75	0	60	0	0
T84	0	151	0	0
T243	0	68	0	0
T268	0	35	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	5424	0	0
T2	305103	64	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	48	0	0
T12	0	33	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	30	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T44	0	15	0	0
T49	25153	0	0	0
T54	0	54	0	0
T75	0	46	0	0
T84	0	138	0	0
T243	0	69	0	0
T268	0	52	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	5479	0	0
T2	305103	64	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	61	0	0
T12	0	42	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	38	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T44	0	2	0	0
T49	25153	0	0	0
T54	0	49	0	0
T75	0	56	0	0
T84	0	150	0	0
T243	0	74	0	0
T268	0	33	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	5639	0	0
T2	305103	83	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	51	0	0
T12	0	60	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	29	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T44	0	13	0	0
T49	25153	0	0	0
T54	0	46	0	0
T75	0	33	0	0
T84	0	145	0	0
T243	0	56	0	0
T268	0	54	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	5556	0	0
T2	305103	82	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	30	0	0
T12	0	38	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	30	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T49	25153	0	0	0
T54	0	45	0	0
T75	0	52	0	0
T84	0	124	0	0
T243	0	52	0	0
T257	0	24	0	0
T268	0	25	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	4990	0	0
T2	305103	73	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	23	0	0
T12	0	30	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	45	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T49	25153	0	0	0
T54	0	24	0	0
T75	0	47	0	0
T84	0	140	0	0
T243	0	50	0	0
T257	0	54	0	0
T268	0	29	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	2778	0	0
T2	305103	55	0	0
T3	199825	0	0	0
T6	194330	0	0	0
T7	0	25	0	0
T12	0	8	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	20	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T44	0	5	0	0
T49	25153	1	0	0
T54	0	4	0	0
T75	0	19	0	0
T76	0	5	0	0
T268	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	2727	0	0
T24	0	31	0	0
T44	763133	8	0	0
T45	101729	0	0	0
T54	0	3	0	0
T63	223523	0	0	0
T64	61634	0	0	0
T65	246118	0	0	0
T71	42454	0	0	0
T72	75697	0	0	0
T87	0	23	0	0
T124	0	53	0	0
T245	0	11	0	0
T285	0	5	0	0
T321	205832	0	0	0
T322	28873	0	0	0
T323	162924	0	0	0
T325	0	31	0	0
T326	0	29	0	0
T330	0	8	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	6364	0	0
T24	0	30	0	0
T40	0	1	0	0
T44	763133	11	0	0
T45	101729	0	0	0
T63	223523	0	0	0
T64	61634	0	0	0
T65	246118	0	0	0
T71	42454	0	0	0
T72	75697	0	0	0
T87	0	11	0	0
T124	0	21	0	0
T150	0	3	0	0
T193	0	4	0	0
T321	205832	0	0	0
T322	28873	0	0	0
T323	162924	0	0	0
T325	0	21	0	0
T326	0	18	0	0
T331	0	5	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	1862	0	0
T24	318734	32	0	0
T30	0	11	0	0
T35	203341	0	0	0
T53	308089	0	0	0
T73	141480	0	0	0
T75	268401	0	0	0
T76	215787	0	0	0
T83	898504	0	0	0
T87	0	24	0	0
T96	297147	0	0	0
T124	0	23	0	0
T145	0	7	0	0
T204	303165	0	0	0
T205	247994	0	0	0
T231	0	9	0	0
T325	0	34	0	0
T326	0	15	0	0
T327	0	10	0	0
T328	0	17	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	6463	0	0
T6	194330	0	0	0
T7	941332	0	0	0
T16	42921	63	0	0
T17	60606	0	0	0
T24	0	98	0	0
T25	61790	0	0	0
T26	0	48	0	0
T27	166872	0	0	0
T28	71335	0	0	0
T29	83659	0	0	0
T44	0	11	0	0
T46	0	51	0	0
T49	25153	0	0	0
T50	59419	0	0	0
T82	0	46	0	0
T124	0	221	0	0
T332	0	66	0	0
T333	0	48	0	0
T334	0	65	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	7997	0	0
T1	332965	0	0	0
T2	305103	0	0	0
T3	199825	0	0	0
T4	125980	44	0	0
T5	241077	0	0	0
T13	211086	0	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	39	0	0
T44	0	12	0	0
T87	0	7	0	0
T124	0	69	0	0
T227	0	227	0	0
T319	0	26	0	0
T325	0	162	0	0
T335	0	98	0	0
T336	0	88	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	5483	0	0
T1	332965	0	0	0
T2	305103	0	0	0
T3	199825	0	0	0
T4	125980	64	0	0
T5	241077	0	0	0
T13	211086	0	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	32	0	0
T87	0	13	0	0
T124	0	90	0	0
T227	0	199	0	0
T319	0	40	0	0
T325	0	181	0	0
T335	0	53	0	0
T336	0	61	0	0
T337	0	20	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	5949	0	0
T1	332965	0	0	0
T2	305103	0	0	0
T3	199825	0	0	0
T4	125980	27	0	0
T5	241077	0	0	0
T13	211086	0	0	0
T14	204728	0	0	0
T15	51282	0	0	0
T16	42921	0	0	0
T17	60606	0	0	0
T24	0	19	0	0
T44	0	2	0	0
T87	0	7	0	0
T124	0	101	0	0
T227	0	215	0	0
T319	0	49	0	0
T325	0	173	0	0
T335	0	48	0	0
T336	0	51	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	1980	0	0
T24	0	24	0	0
T44	763133	4	0	0
T45	101729	0	0	0
T63	223523	0	0	0
T64	61634	0	0	0
T65	246118	0	0	0
T71	42454	0	0	0
T72	75697	0	0	0
T87	0	15	0	0
T124	0	26	0	0
T231	0	16	0	0
T321	205832	0	0	0
T322	28873	0	0	0
T323	162924	0	0	0
T325	0	29	0	0
T326	0	24	0	0
T327	0	8	0	0
T328	0	7	0	0
T329	0	4	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	2081	0	0
T24	0	18	0	0
T44	763133	19	0	0
T45	101729	0	0	0
T63	223523	0	0	0
T64	61634	0	0	0
T65	246118	0	0	0
T71	42454	0	0	0
T72	75697	0	0	0
T78	0	9	0	0
T87	0	6	0	0
T95	0	14	0	0
T124	0	25	0	0
T245	0	4	0	0
T321	205832	0	0	0
T322	28873	0	0	0
T323	162924	0	0	0
T325	0	21	0	0
T338	0	4	0	0
T339	0	12	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	2084	0	0
T24	0	27	0	0
T44	763133	20	0	0
T45	101729	0	0	0
T54	0	1	0	0
T63	223523	0	0	0
T64	61634	0	0	0
T65	246118	0	0	0
T71	42454	0	0	0
T72	75697	0	0	0
T78	0	18	0	0
T80	0	7	0	0
T124	0	30	0	0
T245	0	9	0	0
T321	205832	0	0	0
T322	28873	0	0	0
T323	162924	0	0	0
T325	0	17	0	0
T338	0	1	0	0
T339	0	9	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	2075	0	0
T24	318734	41	0	0
T35	203341	0	0	0
T53	308089	0	0	0
T73	141480	0	0	0
T75	268401	0	0	0
T76	215787	0	0	0
T78	0	8	0	0
T80	0	4	0	0
T83	898504	0	0	0
T87	0	17	0	0
T95	0	7	0	0
T96	297147	0	0	0
T124	0	9	0	0
T204	303165	0	0	0
T205	247994	0	0	0
T245	0	10	0	0
T325	0	42	0	0
T338	0	8	0	0
T339	0	9	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086762458	2116	0	0
T24	0	22	0	0
T44	763133	13	0	0
T45	101729	0	0	0
T54	0	2	0	0
T63	223523	0	0	0
T64	61634	0	0	0
T65	246118	0	0	0
T71	42454	0	0	0
T72	75697	0	0	0
T78	0	6	0	0
T80	0	6	0	0
T124	0	14	0	0
T245	0	7	0	0
T321	205832	0	0	0
T322	28873	0	0	0
T323	162924	0	0	0
T325	0	31	0	0
T338	0	6	0	0
T339	0	20	0	0