Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1935

1

T1

7

T2

2

T12

12

auto[1]

694

1

T1

10

T2

2

T8

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1892

1

T1

4

T2

1

T8

4

auto[1]

737

1

T1

13

T2

3

T12

12

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1899

1

T1

17

T2

4

T12

8

auto[1]

730

1

T12

4

T6

10

T39

5

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1946

1

T1

13

T2

2

T6

10

auto[1]

683

1

T1

4

T2

2

T12

12

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2359

1

T1

17

T2

4

T12

12

auto[1]

270

1

T10

22

T38

31

T37

12

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2453

1

T1

17

T2

4

T12

12

auto[1]

176

1

T10

7

T245

4

T248

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2464

1

T1

17

T2

4

T12

12

auto[1]

165

1

T25

3

T37

26

T248

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2425

1

T1

17

T2

4

T12

12

auto[1]

204

1

T8

4

T25

2

T38

18

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2381

1

T1

17

T2

4

T12

12

auto[1]

248

1

T8

2

T10

5

T38

13

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1994

1

T1

6

T12

10

T8

8

auto[1]

635

1

T1

11

T2

4

T12

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	1056	1			T1	17		T2	4		T12	10
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	95	1			T10	10		T38	18		T127	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	63	1			T90	2		T248	4		T358	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	41	1			T10	5		T38	13		T240	6
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	70	1			T8	1		T25	2		T38	18
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	35	1			T37	12		T127	3		T240	6
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	21	1			T8	1		T37	14		T356	4
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	12	1			T245	3		T359	4		T360	5
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	47	1			T352	2		T361	4		T357	14
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	4	1			T356	4		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	35	1			T37	26		T362	5		T251	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	13	1			T261	6		T363	7		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	9	1			T227	9		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	9	1			T351	2		T361	3		T79	4
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T309	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	58	1			T248	5		T364	6		T171	3
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	11	1			T10	7		T365	1		T366	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	25	1			T245	4		T364	6		T367	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	4	1			T368	4		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	15	1			T351	5		T369	7		T187	3
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	2	1			T243	1		T185	1		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	8	1			T363	8		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	16	1			T248	1		T370	6		T369	5
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T309	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	2	1			T360	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

136

1

T263

7

T312

14

T173

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

121

1

T89

10

T239

4

T131

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T27

3

T96

5

T172

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

119

1

T10

5

T249

8

T89

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

48

1

T28

1

T34

2

T364

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

32

1

T86

3

T32

1

T34

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T1

4

T2

1

T249

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

131

1

T10

17

T86

6

T38

18

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

47

1

T37

14

T89

1

T28

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

55

1

T38

18

T127

4

T240

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

30

1

T264

4

T250

2

T252

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

90

1

T38

13

T122

7

T264

11

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

37

1

T32

1

T264

1

T245

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T11

3

T45

7

T81

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

30

1

T11

1

T34

4

T348

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

125

1

T37

13

T32

4

T28

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

66

1

T1

6

T8

2

T37

13

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

96

1

T1

7

T2

2

T37

12

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T39

2

T60

3

T32

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T12

8

T11

4

T86

12

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

39

1

T53

4

T34

7

T371

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

36

1

T53

4

T28

1

T34

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T2

1

T372

1

T373

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

83

1

T39

3

T53

4

T27

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

46

1

T25

2

T34

2

T90

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

23

1

T6

10

T34

1

T122

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T372

3

T348

1

T374

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

27

1

T45

5

T239

3

T372

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T45

3

T248

4

T170

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T12

2

T34

4

T375

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T376

1

T373

2

T166

4

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded