Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T2

8

T50

10

T65

7

auto[1]

1108

1

T2

12

T50

10

T65

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

533

1

T2

4

T50

6

T65

4

from_0to1

536

1

T2

5

T50

6

T65

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1106

1

T2

10

T50

12

T65

8

auto[1]

1047

1

T2

10

T50

8

T65

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068

1

T2

13

T50

10

T65

10

auto[1]

1085

1

T2

7

T50

10

T65

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T66

1

T59

1

T32

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T50

3

T21

2

T59

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T65

1

T44

1

T89

2

auto[0]

from_1to0

auto[1]

auto[1]

48

1

T21

1

T59

3

T27

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T2

1

T66

1

T21

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T65

1

T66

1

T59

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T2

1

T50

1

T65

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T50

1

T66

1

T21

1

auto[1]

from_1to0

auto[0]

auto[0]

80

1

T2

1

T50

1

T65

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T50

1

T65

1

T59

2

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T2

2

T50

1

T65

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T2

1

T21

1

T59

3

auto[1]

from_0to1

auto[0]

auto[0]

85

1

T2

1

T21

1

T59

3

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T2

1

T50

1

T65

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T2

1

T50

2

T65

1

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T50

1

T65

1

T44

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T2

6

T50

6

T65

12

auto[1]

1074

1

T2

14

T50

14

T65

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

533

1

T2

3

T50

6

T65

4

from_0to1

535

1

T2

3

T50

7

T65

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T2

12

T50

9

T65

10

auto[1]

1074

1

T2

8

T50

11

T65

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1106

1

T2

7

T50

6

T65

9

auto[1]

1047

1

T2

13

T50

14

T65

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T59

1

T27

2

T32

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T2

2

T50

1

T65

1

auto[0]

from_1to0

auto[1]

auto[0]

81

1

T50

1

T65

1

T66

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T66

2

T21

1

T32

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T50

1

T65

2

T21

3

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T65

1

T66

1

T59

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T50

1

T27

2

T32

2

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T65

1

T66

1

T21

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T59

2

T32

4

T44

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T2

1

T50

1

T65

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T59

3

T32

2

T44

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T50

3

T65

1

T66

2

auto[1]

from_0to1

auto[0]

auto[0]

82

1

T50

1

T59

1

T32

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T2

2

T50

2

T66

2

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T50

1

T66

1

T59

4

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T2

1

T50

1

T65

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1076

1

T2

13

T50

15

T65

8

auto[1]

1077

1

T2

7

T50

5

T65

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

510

1

T2

4

T50

5

T65

5

from_0to1

507

1

T2

5

T50

6

T65

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T2

10

T50

11

T65

11

auto[1]

1061

1

T2

10

T50

9

T65

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1057

1

T2

8

T50

7

T65

9

auto[1]

1096

1

T2

12

T50

13

T65

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T65

1

T59

1

T27

1

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T2

2

T50

2

T66

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T65

1

T21

1

T59

2

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T2

1

T50

1

T66

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T2

1

T50

1

T59

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T2

2

T50

1

T65

1

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T2

1

T50

1

T65

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T50

2

T21

1

T59

3

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T2

1

T21

1

T59

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T50

1

T65

2

T66

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T65

1

T21

2

T59

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T50

1

T21

1

T59

3

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T21

1

T59

3

T27

1

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T50

1

T66

2

T21

2

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T65

2

T32

1

T44

2

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T2

1

T59

1

T32

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1091

1

T2

8

T50

9

T65

12

auto[1]

1062

1

T2

12

T50

11

T65

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

510

1

T2

5

T50

6

T65

3

from_0to1

513

1

T2

4

T50

5

T65

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T2

9

T50

10

T65

10

auto[1]

1086

1

T2

11

T50

10

T65

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1078

1

T2

8

T50

9

T65

10

auto[1]

1075

1

T2

12

T50

11

T65

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T50

1

T21

2

T59

2

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T2

1

T50

1

T59

4

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T2

1

T65

1

T66

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T2

2

T50

3

T65

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T50

1

T65

1

T21

2

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T65

1

T59

1

T32

2

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T2

1

T50

1

T66

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T59

2

T44

2

T89

1

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T21

1

T59

1

T32

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T50

1

T59

2

T32

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T2

1

T65

1

T66

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T66

1

T21

1

T59

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T2

1

T65

1

T21

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T2

1

T50

2

T59

3

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T2

1

T66

1

T21

2

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T50

1

T65

1

T66

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T2

10

T50

10

T65

9

auto[1]

1100

1

T2

10

T50

10

T65

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

502

1

T2

5

T50

5

T65

5

from_0to1

500

1

T2

5

T50

5

T65

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T2

9

T50

12

T65

10

auto[1]

1078

1

T2

11

T50

8

T65

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T2

9

T50

10

T65

9

auto[1]

1090

1

T2

11

T50

10

T65

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

53

1

T59

2

T27

2

T89

4

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T50

2

T27

1

T44

2

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T50

1

T21

2

T59

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T65

1

T21

2

T59

3

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T2

1

T50

1

T65

2

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T50

1

T66

2

T59

2

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T2

1

T50

1

T65

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T2

2

T66

1

T59

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T2

1

T65

1

T59

4

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T2

2

T50

2

T66

2

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T2

1

T66

2

T59

3

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T2

1

T65

3

T59

2

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T2

1

T21

1

T59

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T50

1

T59

4

T27

1

auto[1]

from_0to1

auto[1]

auto[0]

45

1

T65

2

T66

1

T59

2

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T50

1

T65

1

T59

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T2

8

T50

14

T65

11

auto[1]

1031

1

T2

12

T50

6

T65

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

507

1

T2

3

T50

3

T65

4

from_0to1

507

1

T2

3

T50

4

T65

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1064

1

T2

6

T50

10

T65

6

auto[1]

1089

1

T2

14

T50

10

T65

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T2

11

T50

11

T65

10

auto[1]

1078

1

T2

9

T50

9

T65

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T59

1

T32

2

T89

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T50

1

T21

1

T27

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T50

1

T66

3

T27

1

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T2

1

T66

1

T21

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T50

1

T21

1

T59

4

auto[0]

from_0to1

auto[0]

auto[1]

80

1

T65

1

T66

1

T59

3

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T2

1

T50

1

T21

3

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T2

1

T50

2

T65

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T50

1

T65

1

T21

1

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T21

1

T59

1

T32

3

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T2

1

T65

1

T59

6

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T2

1

T65

2

T66

1

auto[1]

from_0to1

auto[0]

auto[0]

49

1

T59

1

T44

1

T89

3

auto[1]

from_0to1

auto[0]

auto[1]

51

1

T66

1

T59

2

T32

3

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T65

1

T66

1

T59

4

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T2

1

T66

1

T32

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1083

1

T2

13

T50

10

T65

10

auto[1]

1070

1

T2

7

T50

10

T65

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

528

1

T2

4

T50

4

T65

4

from_0to1

523

1

T2

4

T50

4

T65

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T2

12

T50

9

T65

13

auto[1]

1061

1

T2

8

T50

11

T65

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1066

1

T2

10

T50

14

T65

11

auto[1]

1087

1

T2

10

T50

6

T65

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T2

1

T66

1

T21

2

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T2

1

T65

1

T66

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T50

1

T59

3

T32

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T50

1

T59

1

T27

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T2

1

T50

2

T59

2

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T2

1

T50

1

T59

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T2

1

T50

1

T65

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T2

1

T65

1

T59

2

auto[1]

from_1to0

auto[0]

auto[0]

79

1

T65

1

T21

1

T59

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T65

1

T66

1

T21

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T2

1

T50

1

T65

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T2

1

T50

1

T21

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T65

1

T21

1

T59

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T66

3

T21

1

T59

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T66

1

T21

1

T59

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T21

1

T59

3

T27

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1043

1

T2

8

T50

11

T65

9

auto[1]

1110

1

T2

12

T50

9

T65

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

516

1

T2

6

T50

3

T65

5

from_0to1

519

1

T2

5

T50

3

T65

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T2

5

T50

12

T65

12

auto[1]

1113

1

T2

15

T50

8

T65

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1101

1

T2

8

T50

7

T65

9

auto[1]

1052

1

T2

12

T50

13

T65

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T65

1

T21

1

T59

1

auto[0]

from_1to0

auto[0]

auto[1]

50

1

T66

1

T59

2

T32

2

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T50

2

T59

2

T32

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T2

1

T65

1

T21

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T2

1

T59

1

T27

2

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T50

1

T65

1

T21

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T2

2

T59

3

T32

4

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T21

1

T59

4

T257

1

auto[1]

from_1to0

auto[0]

auto[0]

81

1

T2

1

T50

1

T65

2

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T59

3

T32

2

T44

1

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T59

1

T32

3

T44

2

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T2

4

T65

1

T21

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T65

1

T21

1

T59

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T50

2

T65

2

T66

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T66

1

T32

5

T44

2

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T2

2

T65

1

T59

2