Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156838	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

121593

1

T1

300

T4

6

T2

388

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142784	1			T1	408		T4	2		T2	459
values[0x0]	67677	1			T1	100		T4	6		T2	204
values[0x1]	67970	1			T1	102		T4	7		T2	173

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127537	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

150894

1

T1

355

T4

8

T2

484

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1362	1			T1	1		T2	5		T65	2
valid_sources[0x01]	1063	1			T1	1		T2	1		T12	5
valid_sources[0x02]	966	1			T1	2		T2	4		T14	3
valid_sources[0x03]	1400	1			T2	3		T10	1		T11	1
valid_sources[0x04]	897	1			T1	4		T2	3		T12	4
valid_sources[0x05]	874	1			T1	2		T2	7		T12	3
valid_sources[0x06]	1038	1			T1	7		T2	4		T12	3
valid_sources[0x07]	1204	1			T1	2		T2	2		T14	1
valid_sources[0x08]	994	1			T2	2		T13	1		T39	34
valid_sources[0x09]	852	1			T1	1		T2	1		T39	27
valid_sources[0x0a]	880	1			T1	6		T2	5		T12	4
valid_sources[0x0b]	805	1			T2	2		T14	1		T10	5
valid_sources[0x0c]	899	1			T1	2		T4	1		T2	3
valid_sources[0x0d]	1012	1			T1	5		T2	3		T65	1
valid_sources[0x0e]	845	1			T2	1		T12	1		T48	2
valid_sources[0x0f]	777	1			T1	5		T2	4		T12	1
valid_sources[0x10]	904	1			T2	4		T12	2		T10	3
valid_sources[0x11]	1883	1			T1	1		T2	5		T12	1
valid_sources[0x12]	895	1			T1	1		T2	4		T48	1
valid_sources[0x13]	1045	1			T1	3		T2	6		T14	1
valid_sources[0x14]	791	1			T1	1		T2	1		T12	2
valid_sources[0x15]	841	1			T2	3		T12	3		T65	3
valid_sources[0x16]	919	1			T1	2		T2	3		T12	5
valid_sources[0x17]	756	1			T2	5		T14	1		T10	3
valid_sources[0x18]	1668	1			T1	2		T2	3		T12	1
valid_sources[0x19]	906	1			T1	2		T2	4		T12	2
valid_sources[0x1a]	969	1			T1	1		T2	4		T10	5
valid_sources[0x1b]	988	1			T1	5		T2	4		T12	2
valid_sources[0x1c]	909	1			T1	2		T2	3		T12	6
valid_sources[0x1d]	3076	1			T2	4		T12	5		T13	1
valid_sources[0x1e]	922	1			T1	2		T2	3		T12	3
valid_sources[0x1f]	1071	1			T1	2		T2	4		T46	4
valid_sources[0x20]	951	1			T2	10		T12	6		T10	5
valid_sources[0x21]	944	1			T1	1		T2	3		T12	3
valid_sources[0x22]	784	1			T1	11		T2	2		T14	1
valid_sources[0x23]	1938	1			T1	2		T2	2		T12	1
valid_sources[0x24]	803	1			T1	2		T2	5		T12	1
valid_sources[0x25]	1607	1			T1	4		T2	3		T7	1
valid_sources[0x26]	1368	1			T2	4		T3	2		T50	14
valid_sources[0x27]	733	1			T1	1		T2	3		T12	3
valid_sources[0x28]	1510	1			T2	2		T12	2		T10	4
valid_sources[0x29]	997	1			T1	1		T12	3		T46	2
valid_sources[0x2a]	918	1			T2	4		T10	1		T25	1
valid_sources[0x2b]	872	1			T1	1		T2	4		T12	2
valid_sources[0x2c]	1307	1			T1	1		T2	4		T50	1
valid_sources[0x2d]	1619	1			T1	3		T2	11		T12	8
valid_sources[0x2e]	1095	1			T1	6		T2	3		T12	7
valid_sources[0x2f]	1039	1			T1	1		T2	4		T12	2
valid_sources[0x30]	993	1			T2	9		T12	2		T7	1
valid_sources[0x31]	1607	1			T1	3		T2	7		T12	1
valid_sources[0x32]	933	1			T1	1		T2	2		T12	2
valid_sources[0x33]	1006	1			T1	5		T2	1		T10	4
valid_sources[0x34]	928	1			T2	2		T12	3		T65	1
valid_sources[0x35]	1056	1			T2	3		T12	2		T14	1
valid_sources[0x36]	787	1			T1	6		T2	1		T12	4
valid_sources[0x37]	780	1			T1	16		T2	1		T12	2
valid_sources[0x38]	957	1			T1	7		T2	3		T12	3
valid_sources[0x39]	1166	1			T1	7		T2	3		T12	4
valid_sources[0x3a]	979	1			T1	1		T2	3		T12	1
valid_sources[0x3b]	921	1			T1	2		T2	5		T12	2
valid_sources[0x3c]	796	1			T1	1		T2	5		T12	1
valid_sources[0x3d]	1190	1			T1	2		T2	5		T12	4
valid_sources[0x3e]	1061	1			T1	3		T2	1		T12	2
valid_sources[0x3f]	945	1			T2	2		T12	2		T10	1
valid_sources[0x40]	1066	1			T1	1		T2	1		T65	1
valid_sources[0x41]	904	1			T1	9		T2	1		T23	1
valid_sources[0x42]	945	1			T1	3		T4	2		T2	3
valid_sources[0x43]	2200	1			T1	1		T2	1		T51	2
valid_sources[0x44]	991	1			T1	2		T2	4		T12	1
valid_sources[0x45]	925	1			T2	3		T12	2		T13	2
valid_sources[0x46]	1222	1			T1	5		T4	2		T2	5
valid_sources[0x47]	915	1			T2	3		T12	8		T48	2
valid_sources[0x48]	841	1			T2	2		T10	5		T11	1
valid_sources[0x49]	925	1			T1	2		T2	3		T12	1
valid_sources[0x4a]	787	1			T1	2		T2	3		T14	1
valid_sources[0x4b]	755	1			T1	10		T2	3		T65	1
valid_sources[0x4c]	989	1			T1	3		T2	2		T23	2
valid_sources[0x4d]	1199	1			T1	4		T2	6		T12	2
valid_sources[0x4e]	827	1			T2	1		T12	1		T14	2
valid_sources[0x4f]	833	1			T1	6		T2	1		T12	3
valid_sources[0x50]	1480	1			T1	1		T2	9		T12	5
valid_sources[0x51]	1041	1			T1	3		T2	4		T12	3
valid_sources[0x52]	873	1			T2	3		T12	2		T23	1
valid_sources[0x53]	980	1			T2	7		T12	1		T14	1
valid_sources[0x54]	899	1			T1	2		T2	3		T12	3
valid_sources[0x55]	788	1			T1	4		T2	2		T14	2
valid_sources[0x56]	878	1			T1	16		T2	6		T10	3
valid_sources[0x57]	889	1			T1	4		T2	3		T12	4
valid_sources[0x58]	945	1			T1	4		T2	4		T12	2
valid_sources[0x59]	1013	1			T2	3		T12	6		T10	2
valid_sources[0x5a]	722	1			T1	6		T2	3		T12	1
valid_sources[0x5b]	2975	1			T8	865		T10	6		T25	3
valid_sources[0x5c]	1564	1			T2	3		T12	1		T10	3
valid_sources[0x5d]	836	1			T1	3		T12	5		T10	4
valid_sources[0x5e]	1049	1			T1	1		T2	4		T10	8
valid_sources[0x5f]	906	1			T2	2		T5	1		T10	12
valid_sources[0x60]	1301	1			T12	1		T13	1		T65	1
valid_sources[0x61]	880	1			T1	1		T2	1		T12	1
valid_sources[0x62]	776	1			T1	2		T2	6		T12	3
valid_sources[0x63]	757	1			T2	5		T65	1		T10	4
valid_sources[0x64]	751	1			T2	4		T3	2		T48	4
valid_sources[0x65]	1303	1			T1	2		T2	5		T10	3
valid_sources[0x66]	908	1			T1	3		T2	5		T12	1
valid_sources[0x67]	1666	1			T1	9		T2	2		T3	1
valid_sources[0x68]	908	1			T2	5		T23	1		T10	3
valid_sources[0x69]	992	1			T2	2		T12	6		T48	2
valid_sources[0x6a]	946	1			T1	8		T4	1		T2	6
valid_sources[0x6b]	942	1			T2	7		T12	1		T39	14
valid_sources[0x6c]	924	1			T2	2		T12	4		T13	2
valid_sources[0x6d]	974	1			T1	3		T2	2		T12	6
valid_sources[0x6e]	809	1			T1	1		T2	1		T12	6
valid_sources[0x6f]	998	1			T2	4		T14	2		T10	5
valid_sources[0x70]	790	1			T1	2		T2	2		T12	1
valid_sources[0x71]	913	1			T1	1		T2	4		T12	1
valid_sources[0x72]	908	1			T1	2		T2	5		T12	1
valid_sources[0x73]	2267	1			T1	4		T2	5		T12	2
valid_sources[0x74]	1018	1			T1	12		T10	4		T66	1
valid_sources[0x75]	876	1			T2	1		T12	2		T14	1
valid_sources[0x76]	1177	1			T2	3		T10	8		T66	3
valid_sources[0x77]	858	1			T1	2		T2	4		T5	1
valid_sources[0x78]	835	1			T1	1		T2	5		T3	2
valid_sources[0x79]	1248	1			T1	5		T2	3		T12	2
valid_sources[0x7a]	1042	1			T1	16		T2	6		T48	1
valid_sources[0x7b]	1098	1			T1	1		T2	4		T12	1
valid_sources[0x7c]	1440	1			T1	11		T2	8		T14	1
valid_sources[0x7d]	1092	1			T12	5		T65	5		T10	1
valid_sources[0x7e]	1059	1			T1	2		T2	4		T13	2
valid_sources[0x7f]	1025	1			T2	2		T12	4		T14	1
valid_sources[0x80]	1697	1			T1	2		T2	1		T12	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65332

1

T1

207

T4

1

T2

236

values[0x0]

all_enables

biggest_size

33032

1

T1

53

T4

2

T2

94

values[0x1]

all_enables

biggest_size

23229

1

T1

40

T4

3

T2

58