Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl_ulp
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_ulp 100.00 100.00 100.00



Module Instance : tb.dut.u_sysrst_ctrl_ulp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.98 100.00 94.92 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sysrst_ctrl_detect_ac_present 98.67 100.00 93.33 100.00 100.00 100.00
u_sysrst_ctrl_detect_lid_open 98.89 100.00 94.44 100.00 100.00 100.00
u_sysrst_ctrl_detect_pwrb 98.89 100.00 94.44 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl_ulp
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
89 1 1
93 1 1


Cond Coverage for Module : sysrst_ctrl_ulp
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       89
 EXPRESSION (pwrb_det_pulse | lid_open_det_pulse | ac_present_det_pulse)
             -------1------   ---------2--------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T4,T2
001CoveredT19,T20,T21
010CoveredT19,T20,T21
100CoveredT19,T20,T32

 LINE       93
 EXPRESSION (pwrb_det | lid_open_det | ac_present_det)
             ----1---   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT1,T4,T2
001CoveredT20,T32,T57
010CoveredT19,T21,T28
100CoveredT44,T55,T34
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%