Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T30,T31,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T30,T31,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T30,T31,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T30,T31
1	0	Covered	T1,T4,T2
1	1	Covered	T30,T31,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T28
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T28
0	1	Covered	T30,T28,T160
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T28
1	-	Covered	T30,T28,T160

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T30,T31,T28
DetectSt	168	Covered	T30,T31,T28
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T30,T31,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T30,T31,T28
DebounceSt->IdleSt	163	Covered	T158,T129,T74
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T30,T31,T28
IdleSt->DebounceSt	148	Covered	T30,T31,T28
StableSt->IdleSt	206	Covered	T30,T28,T160

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T30,T31,T28
0	1	Covered	T30,T31,T28
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T28
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T30,T31,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T30,T31,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T158,T129
DebounceSt	-	0	0	-	-	-	-	Covered	T30,T31,T28
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T30,T31,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T28,T160
StableSt	-	-	-	-	-	-	0	Covered	T30,T31,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	69	0	0
CntIncr_A	5765374	1652	0	0
CntNoWrap_A	5765374	5139181	0	0
DetectStDropOut_A	5765374	0	0	0
DetectedOut_A	5765374	2317	0	0
DetectedPulseOut_A	5765374	33	0	0
DisabledIdleSt_A	5765374	5124574	0	0
DisabledNoDetection_A	5765374	5126825	0	0
EnterDebounceSt_A	5765374	36	0	0
EnterDetectSt_A	5765374	33	0	0
EnterStableSt_A	5765374	33	0	0
PulseIsPulse_A	5765374	33	0	0
StayInStableSt	5765374	2266	0	0
gen_high_level_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	69	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	4	0	0
T30	770	2	0	0
T31	868	2	0	0
T58	494	0	0	0
T64	498	0	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T129	0	1	0	0
T140	679	0	0	0
T156	0	4	0	0
T157	0	4	0	0
T158	0	1	0	0
T159	0	4	0	0
T160	0	4	0	0
T161	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	1652	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	46	0	0
T30	770	28	0	0
T31	868	79	0	0
T58	494	0	0	0
T64	498	0	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T129	0	24	0	0
T140	679	0	0	0
T156	0	42	0	0
T157	0	70	0	0
T158	0	65	0	0
T159	0	82	0	0
T160	0	156	0	0
T161	0	59	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5139181	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	2317	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	126	0	0
T30	770	39	0	0
T31	868	173	0	0
T58	494	0	0	0
T64	498	0	0	0
T82	0	185	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T156	0	85	0	0
T157	0	83	0	0
T159	0	90	0	0
T160	0	77	0	0
T161	0	38	0	0
T162	0	122	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	33	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	2	0	0
T30	770	1	0	0
T31	868	1	0	0
T58	494	0	0	0
T64	498	0	0	0
T82	0	1	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T156	0	2	0	0
T157	0	2	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	1	0	0
T162	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5124574	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	3	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5126825	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	3	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	36	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	2	0	0
T30	770	1	0	0
T31	868	1	0	0
T58	494	0	0	0
T64	498	0	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T129	0	1	0	0
T140	679	0	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	33	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	2	0	0
T30	770	1	0	0
T31	868	1	0	0
T58	494	0	0	0
T64	498	0	0	0
T82	0	1	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T156	0	2	0	0
T157	0	2	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	1	0	0
T162	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	33	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	2	0	0
T30	770	1	0	0
T31	868	1	0	0
T58	494	0	0	0
T64	498	0	0	0
T82	0	1	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T156	0	2	0	0
T157	0	2	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	1	0	0
T162	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	33	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	2	0	0
T30	770	1	0	0
T31	868	1	0	0
T58	494	0	0	0
T64	498	0	0	0
T82	0	1	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T156	0	2	0	0
T157	0	2	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	1	0	0
T162	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	2266	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	123	0	0
T30	770	38	0	0
T31	868	171	0	0
T58	494	0	0	0
T64	498	0	0	0
T82	0	184	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T156	0	82	0	0
T157	0	80	0	0
T159	0	87	0	0
T160	0	74	0	0
T161	0	36	0	0
T162	0	119	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	14	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	1	0	0
T30	770	1	0	0
T31	868	0	0	0
T58	494	0	0	0
T64	498	0	0	0
T82	0	1	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T136	0	2	0	0
T140	679	0	0	0
T156	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T5,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T3,T5,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T5,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T34
1	0	Covered	T1,T2,T12
1	1	Covered	T3,T5,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T34
0	1	Covered	T5,T34,T144
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T5,T34
1	-	Covered	T5,T34,T144

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T5,T34
DetectSt	168	Covered	T3,T5,T34
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T5,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T5,T34
DebounceSt->IdleSt	163	Covered	T34,T74,T146
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T5,T34
IdleSt->DebounceSt	148	Covered	T3,T5,T34
StableSt->IdleSt	206	Covered	T5,T34,T144

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T5,T34
0	1	Covered	T3,T5,T34
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T34
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T5,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T5,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T146
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T5,T34
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T5,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T34,T144
StableSt	-	-	-	-	-	-	0	Covered	T3,T5,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	98	0	0
CntIncr_A	5765374	2689	0	0
CntNoWrap_A	5765374	5139152	0	0
DetectStDropOut_A	5765374	0	0	0
DetectedOut_A	5765374	3140	0	0
DetectedPulseOut_A	5765374	47	0	0
DisabledIdleSt_A	5765374	5126568	0	0
DisabledNoDetection_A	5765374	5128825	0	0
EnterDebounceSt_A	5765374	51	0	0
EnterDetectSt_A	5765374	47	0	0
EnterStableSt_A	5765374	47	0	0
PulseIsPulse_A	5765374	47	0	0
StayInStableSt	5765374	3077	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5765374	2878	0	0
gen_low_level_sva.LowLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	98	0	0
T3	628	2	0	0
T5	566	4	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T29	0	2	0	0
T34	0	4	0	0
T46	433	0	0	0
T76	0	2	0	0
T107	435	0	0	0
T144	0	2	0	0
T145	0	4	0	0
T160	0	4	0	0
T164	0	2	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	2689	0	0
T3	628	76	0	0
T5	566	32	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T29	0	21	0	0
T34	0	252	0	0
T46	433	0	0	0
T76	0	29	0	0
T107	435	0	0	0
T144	0	81	0	0
T145	0	62	0	0
T160	0	156	0	0
T164	0	92	0	0
T165	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5139152	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	225	0	0
T4	407	6	0	0
T5	566	161	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	3140	0	0
T3	628	44	0	0
T5	566	10	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T29	0	85	0	0
T34	0	80	0	0
T46	433	0	0	0
T76	0	43	0	0
T107	435	0	0	0
T144	0	177	0	0
T145	0	162	0	0
T160	0	13	0	0
T164	0	166	0	0
T165	0	153	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	47	0	0
T3	628	1	0	0
T5	566	2	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T29	0	1	0	0
T34	0	1	0	0
T46	433	0	0	0
T76	0	1	0	0
T107	435	0	0	0
T144	0	1	0	0
T145	0	2	0	0
T160	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5126568	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	3	0	0
T4	407	6	0	0
T5	566	4	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5128825	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	3	0	0
T4	407	7	0	0
T5	566	4	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	51	0	0
T3	628	1	0	0
T5	566	2	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T29	0	1	0	0
T34	0	3	0	0
T46	433	0	0	0
T76	0	1	0	0
T107	435	0	0	0
T144	0	1	0	0
T145	0	2	0	0
T160	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	47	0	0
T3	628	1	0	0
T5	566	2	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T29	0	1	0	0
T34	0	1	0	0
T46	433	0	0	0
T76	0	1	0	0
T107	435	0	0	0
T144	0	1	0	0
T145	0	2	0	0
T160	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	47	0	0
T3	628	1	0	0
T5	566	2	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T29	0	1	0	0
T34	0	1	0	0
T46	433	0	0	0
T76	0	1	0	0
T107	435	0	0	0
T144	0	1	0	0
T145	0	2	0	0
T160	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	47	0	0
T3	628	1	0	0
T5	566	2	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T29	0	1	0	0
T34	0	1	0	0
T46	433	0	0	0
T76	0	1	0	0
T107	435	0	0	0
T144	0	1	0	0
T145	0	2	0	0
T160	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	3077	0	0
T3	628	42	0	0
T5	566	8	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T29	0	83	0	0
T34	0	79	0	0
T46	433	0	0	0
T76	0	41	0	0
T107	435	0	0	0
T144	0	176	0	0
T145	0	159	0	0
T160	0	11	0	0
T164	0	164	0	0
T165	0	152	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	2878	0	0
T2	13420	40	0	0
T3	628	1	0	0
T5	566	2	0	0
T6	15908	0	0	0
T7	550	1	0	0
T12	16327	0	0	0
T13	492	5	0	0
T14	522	6	0	0
T15	527	7	0	0
T46	433	4	0	0
T47	0	1	0	0
T107	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	30	0	0
T5	566	2	0	0
T6	15908	0	0	0
T7	550	0	0	0
T8	12309	0	0	0
T15	527	0	0	0
T23	704	0	0	0
T34	0	1	0	0
T39	17057	0	0	0
T46	433	0	0	0
T47	422	0	0	0
T107	435	0	0	0
T129	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T157	0	2	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	1	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T31,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T3,T31,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T31,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T31,T32
1	0	Covered	T1,T2,T12
1	1	Covered	T3,T31,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T31,T32
0	1	Covered	T83,T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T31,T32
0	1	Covered	T31,T32,T28
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T31,T32
1	-	Covered	T31,T32,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T31,T32
DetectSt	168	Covered	T3,T31,T32
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T31,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T31,T32
DebounceSt->IdleSt	163	Covered	T28,T34,T142
DetectSt->IdleSt	186	Covered	T83,T166
DetectSt->StableSt	191	Covered	T3,T31,T32
IdleSt->DebounceSt	148	Covered	T3,T31,T32
StableSt->IdleSt	206	Covered	T31,T32,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T31,T32
0	1	Covered	T3,T31,T32
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T31,T32
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T31,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T31,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T34,T142
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T31,T32
DetectSt	-	-	-	-	1	-	-	Covered	T83,T166
DetectSt	-	-	-	-	0	1	-	Covered	T3,T31,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T32,T28
StableSt	-	-	-	-	-	-	0	Covered	T3,T31,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	107	0	0
CntIncr_A	5765374	62446	0	0
CntNoWrap_A	5765374	5139143	0	0
DetectStDropOut_A	5765374	2	0	0
DetectedOut_A	5765374	8098	0	0
DetectedPulseOut_A	5765374	48	0	0
DisabledIdleSt_A	5765374	4998408	0	0
DisabledNoDetection_A	5765374	5000652	0	0
EnterDebounceSt_A	5765374	57	0	0
EnterDetectSt_A	5765374	50	0	0
EnterStableSt_A	5765374	48	0	0
PulseIsPulse_A	5765374	48	0	0
StayInStableSt	5765374	8032	0	0
gen_high_level_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	107	0	0
T3	628	2	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	5	0	0
T31	0	2	0	0
T32	0	4	0	0
T34	0	1	0	0
T36	0	2	0	0
T46	433	0	0	0
T107	435	0	0	0
T131	0	2	0	0
T142	0	1	0	0
T144	0	2	0	0
T164	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	62446	0	0
T3	628	76	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	78	0	0
T31	0	79	0	0
T32	0	42	0	0
T34	0	84	0	0
T36	0	12	0	0
T46	433	0	0	0
T107	435	0	0	0
T131	0	97	0	0
T142	0	11	0	0
T144	0	81	0	0
T164	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5139143	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	225	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	2	0	0
T83	2511	1	0	0
T166	0	1	0	0
T167	4404	0	0	0
T168	27590	0	0	0
T169	5266	0	0	0
T170	29305	0	0	0
T171	13243	0	0	0
T172	25161	0	0	0
T173	35007	0	0	0
T174	422	0	0	0
T175	8789	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	8098	0	0
T3	628	142	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	162	0	0
T31	0	260	0	0
T32	0	51	0	0
T36	0	6	0	0
T46	433	0	0	0
T107	435	0	0	0
T131	0	42	0	0
T144	0	42	0	0
T145	0	71	0	0
T160	0	210	0	0
T164	0	35	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	48	0	0
T3	628	1	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T36	0	1	0	0
T46	433	0	0	0
T107	435	0	0	0
T131	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T160	0	1	0	0
T164	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4998408	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	3	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5000652	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	3	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	57	0	0
T3	628	1	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	3	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T36	0	1	0	0
T46	433	0	0	0
T107	435	0	0	0
T131	0	1	0	0
T142	0	1	0	0
T144	0	1	0	0
T164	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	50	0	0
T3	628	1	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T36	0	1	0	0
T46	433	0	0	0
T107	435	0	0	0
T131	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T160	0	1	0	0
T164	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	48	0	0
T3	628	1	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T36	0	1	0	0
T46	433	0	0	0
T107	435	0	0	0
T131	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T160	0	1	0	0
T164	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	48	0	0
T3	628	1	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T36	0	1	0	0
T46	433	0	0	0
T107	435	0	0	0
T131	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T160	0	1	0	0
T164	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	8032	0	0
T3	628	140	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	159	0	0
T31	0	259	0	0
T32	0	48	0	0
T36	0	5	0	0
T46	433	0	0	0
T107	435	0	0	0
T131	0	41	0	0
T144	0	41	0	0
T145	0	69	0	0
T160	0	209	0	0
T164	0	34	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	29	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T21	1979	0	0	0
T28	0	1	0	0
T31	868	1	0	0
T32	0	1	0	0
T36	0	1	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T87	2102	0	0	0
T131	0	1	0	0
T144	0	1	0	0
T158	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T30,T32,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T30,T32,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T30,T32,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T30,T32
1	0	Covered	T1,T2,T12
1	1	Covered	T30,T32,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T30,T32,T28
0	1	Covered	T176
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T32,T28
0	1	Covered	T30,T32,T28
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T32,T28
1	-	Covered	T30,T32,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T30,T32,T28
DetectSt	168	Covered	T30,T32,T28
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T30,T32,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T30,T32,T28
DebounceSt->IdleSt	163	Covered	T163,T74,T177
DetectSt->IdleSt	186	Covered	T176
DetectSt->StableSt	191	Covered	T30,T32,T28
IdleSt->DebounceSt	148	Covered	T30,T32,T28
StableSt->IdleSt	206	Covered	T30,T32,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T30,T32,T28
0	1	Covered	T30,T32,T28
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T32,T28
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T30,T32,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T30,T32,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T163,T177
DebounceSt	-	0	0	-	-	-	-	Covered	T30,T32,T28
DetectSt	-	-	-	-	1	-	-	Covered	T176
DetectSt	-	-	-	-	0	1	-	Covered	T30,T32,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T32,T28
StableSt	-	-	-	-	-	-	0	Covered	T30,T32,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	61	0	0
CntIncr_A	5765374	1424	0	0
CntNoWrap_A	5765374	5139189	0	0
DetectStDropOut_A	5765374	1	0	0
DetectedOut_A	5765374	2863	0	0
DetectedPulseOut_A	5765374	28	0	0
DisabledIdleSt_A	5765374	5125626	0	0
DisabledNoDetection_A	5765374	5127879	0	0
EnterDebounceSt_A	5765374	32	0	0
EnterDetectSt_A	5765374	29	0	0
EnterStableSt_A	5765374	28	0	0
PulseIsPulse_A	5765374	28	0	0
StayInStableSt	5765374	2817	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5765374	6591	0	0
gen_low_level_sva.LowLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	61	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	2	0	0
T29	0	2	0	0
T30	770	4	0	0
T31	868	0	0	0
T32	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T58	494	0	0	0
T64	498	0	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T142	0	2	0	0
T158	0	2	0	0
T161	0	2	0	0
T178	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	1424	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	23	0	0
T29	0	21	0	0
T30	770	56	0	0
T31	868	0	0	0
T32	0	21	0	0
T35	0	13	0	0
T36	0	12	0	0
T58	494	0	0	0
T64	498	0	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T142	0	11	0	0
T158	0	65	0	0
T161	0	59	0	0
T178	0	75	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5139189	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	1	0	0
T176	912	1	0	0
T179	521	0	0	0
T180	27774	0	0	0
T181	427	0	0	0
T182	10166	0	0	0
T183	522	0	0	0
T184	1879	0	0	0
T185	10388	0	0	0
T186	403	0	0	0
T187	28915	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	2863	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	63	0	0
T29	0	42	0	0
T30	770	82	0	0
T31	868	0	0	0
T32	0	75	0	0
T35	0	58	0	0
T36	0	46	0	0
T58	494	0	0	0
T64	498	0	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T142	0	42	0	0
T158	0	312	0	0
T161	0	233	0	0
T178	0	172	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	28	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	770	2	0	0
T31	868	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T58	494	0	0	0
T64	498	0	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T142	0	1	0	0
T158	0	1	0	0
T161	0	1	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5125626	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	3	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5127879	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	3	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	32	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	770	2	0	0
T31	868	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T58	494	0	0	0
T64	498	0	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T142	0	1	0	0
T158	0	1	0	0
T161	0	1	0	0
T178	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	29	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	770	2	0	0
T31	868	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T58	494	0	0	0
T64	498	0	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T142	0	1	0	0
T158	0	1	0	0
T161	0	1	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	28	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	770	2	0	0
T31	868	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T58	494	0	0	0
T64	498	0	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T142	0	1	0	0
T158	0	1	0	0
T161	0	1	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	28	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	770	2	0	0
T31	868	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T58	494	0	0	0
T64	498	0	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T142	0	1	0	0
T158	0	1	0	0
T161	0	1	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	2817	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	62	0	0
T29	0	40	0	0
T30	770	80	0	0
T31	868	0	0	0
T32	0	74	0	0
T35	0	57	0	0
T36	0	44	0	0
T58	494	0	0	0
T64	498	0	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T142	0	40	0	0
T158	0	310	0	0
T161	0	231	0	0
T178	0	170	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	6591	0	0
T1	28795	11	0	0
T2	13420	43	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	1	0	0
T6	15908	14	0	0
T12	16327	10	0	0
T13	492	7	0	0
T14	522	4	0	0
T15	527	6	0	0
T46	0	4	0	0
T107	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	9	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	1	0	0
T30	770	2	0	0
T31	868	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T58	494	0	0	0
T64	498	0	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T140	679	0	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T7,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T5,T7,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T7,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T28
0	1	Covered	T192,T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T28
0	1	Covered	T5,T28,T34
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T7,T28
1	-	Covered	T5,T28,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T7,T28
DetectSt	168	Covered	T5,T7,T28
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T7,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T7,T28
DebounceSt->IdleSt	163	Covered	T188,T74
DetectSt->IdleSt	186	Covered	T192,T166
DetectSt->StableSt	191	Covered	T5,T7,T28
IdleSt->DebounceSt	148	Covered	T5,T7,T28
StableSt->IdleSt	206	Covered	T5,T28,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T7,T28
0	1	Covered	T5,T7,T28
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T28
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T7,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T7,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T188
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T7,T28
DetectSt	-	-	-	-	1	-	-	Covered	T192,T166
DetectSt	-	-	-	-	0	1	-	Covered	T5,T7,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T28,T34
StableSt	-	-	-	-	-	-	0	Covered	T5,T7,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	110	0	0
CntIncr_A	5765374	62092	0	0
CntNoWrap_A	5765374	5139140	0	0
DetectStDropOut_A	5765374	2	0	0
DetectedOut_A	5765374	67736	0	0
DetectedPulseOut_A	5765374	52	0	0
DisabledIdleSt_A	5765374	5003214	0	0
DisabledNoDetection_A	5765374	5005468	0	0
EnterDebounceSt_A	5765374	56	0	0
EnterDetectSt_A	5765374	54	0	0
EnterStableSt_A	5765374	52	0	0
PulseIsPulse_A	5765374	52	0	0
StayInStableSt	5765374	67662	0	0
gen_high_level_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	110	0	0
T5	566	2	0	0
T6	15908	0	0	0
T7	550	2	0	0
T8	12309	0	0	0
T15	527	0	0	0
T23	704	0	0	0
T28	0	6	0	0
T34	0	4	0	0
T39	17057	0	0	0
T46	433	0	0	0
T47	422	0	0	0
T82	0	6	0	0
T107	435	0	0	0
T131	0	2	0	0
T159	0	2	0	0
T162	0	8	0	0
T165	0	2	0	0
T188	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	62092	0	0
T5	566	16	0	0
T6	15908	0	0	0
T7	550	47	0	0
T8	12309	0	0	0
T15	527	0	0	0
T23	704	0	0	0
T28	0	69	0	0
T34	0	168	0	0
T39	17057	0	0	0
T46	433	0	0	0
T47	422	0	0	0
T82	0	147	0	0
T107	435	0	0	0
T131	0	97	0	0
T159	0	41	0	0
T162	0	140	0	0
T165	0	38	0	0
T188	0	158	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5139140	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	163	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	2	0	0
T163	909	0	0	0
T166	0	1	0	0
T192	8211	1	0	0
T193	559	0	0	0
T194	495	0	0	0
T195	2928	0	0	0
T196	489	0	0	0
T197	30936	0	0	0
T198	505	0	0	0
T199	498	0	0	0
T200	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	67736	0	0
T5	566	69	0	0
T6	15908	0	0	0
T7	550	93	0	0
T8	12309	0	0	0
T15	527	0	0	0
T23	704	0	0	0
T28	0	167	0	0
T34	0	271	0	0
T39	17057	0	0	0
T46	433	0	0	0
T47	422	0	0	0
T82	0	558	0	0
T107	435	0	0	0
T131	0	28	0	0
T159	0	85	0	0
T162	0	109	0	0
T165	0	78	0	0
T188	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	52	0	0
T5	566	1	0	0
T6	15908	0	0	0
T7	550	1	0	0
T8	12309	0	0	0
T15	527	0	0	0
T23	704	0	0	0
T28	0	3	0	0
T34	0	2	0	0
T39	17057	0	0	0
T46	433	0	0	0
T47	422	0	0	0
T82	0	3	0	0
T107	435	0	0	0
T131	0	1	0	0
T159	0	1	0	0
T162	0	4	0	0
T165	0	1	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5003214	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	4	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5005468	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	4	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	56	0	0
T5	566	1	0	0
T6	15908	0	0	0
T7	550	1	0	0
T8	12309	0	0	0
T15	527	0	0	0
T23	704	0	0	0
T28	0	3	0	0
T34	0	2	0	0
T39	17057	0	0	0
T46	433	0	0	0
T47	422	0	0	0
T82	0	3	0	0
T107	435	0	0	0
T131	0	1	0	0
T159	0	1	0	0
T162	0	4	0	0
T165	0	1	0	0
T188	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	54	0	0
T5	566	1	0	0
T6	15908	0	0	0
T7	550	1	0	0
T8	12309	0	0	0
T15	527	0	0	0
T23	704	0	0	0
T28	0	3	0	0
T34	0	2	0	0
T39	17057	0	0	0
T46	433	0	0	0
T47	422	0	0	0
T82	0	3	0	0
T107	435	0	0	0
T131	0	1	0	0
T159	0	1	0	0
T162	0	4	0	0
T165	0	1	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	52	0	0
T5	566	1	0	0
T6	15908	0	0	0
T7	550	1	0	0
T8	12309	0	0	0
T15	527	0	0	0
T23	704	0	0	0
T28	0	3	0	0
T34	0	2	0	0
T39	17057	0	0	0
T46	433	0	0	0
T47	422	0	0	0
T82	0	3	0	0
T107	435	0	0	0
T131	0	1	0	0
T159	0	1	0	0
T162	0	4	0	0
T165	0	1	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	52	0	0
T5	566	1	0	0
T6	15908	0	0	0
T7	550	1	0	0
T8	12309	0	0	0
T15	527	0	0	0
T23	704	0	0	0
T28	0	3	0	0
T34	0	2	0	0
T39	17057	0	0	0
T46	433	0	0	0
T47	422	0	0	0
T82	0	3	0	0
T107	435	0	0	0
T131	0	1	0	0
T159	0	1	0	0
T162	0	4	0	0
T165	0	1	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	67662	0	0
T5	566	68	0	0
T6	15908	0	0	0
T7	550	91	0	0
T8	12309	0	0	0
T15	527	0	0	0
T23	704	0	0	0
T28	0	163	0	0
T34	0	268	0	0
T39	17057	0	0	0
T46	433	0	0	0
T47	422	0	0	0
T82	0	553	0	0
T107	435	0	0	0
T131	0	27	0	0
T159	0	84	0	0
T162	0	103	0	0
T165	0	77	0	0
T188	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	29	0	0
T5	566	1	0	0
T6	15908	0	0	0
T7	550	0	0	0
T8	12309	0	0	0
T15	527	0	0	0
T23	704	0	0	0
T28	0	2	0	0
T34	0	1	0	0
T39	17057	0	0	0
T46	433	0	0	0
T47	422	0	0	0
T82	0	1	0	0
T107	435	0	0	0
T131	0	1	0	0
T138	0	2	0	0
T159	0	1	0	0
T162	0	2	0	0
T165	0	1	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T32,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T2,T32,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T32,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T32,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T32,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T32,T33
0	1	Covered	T2,T32,T145
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T32,T33
1	-	Covered	T2,T32,T145

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T32,T33
DetectSt	168	Covered	T2,T32,T33
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T32,T33
DebounceSt->IdleSt	163	Covered	T163,T202,T74
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T32,T33
IdleSt->DebounceSt	148	Covered	T2,T32,T33
StableSt->IdleSt	206	Covered	T2,T32,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T32,T33
0	1	Covered	T2,T32,T33
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T32,T33
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T32,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T32,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T163,T202
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T32,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T32,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T32,T145
StableSt	-	-	-	-	-	-	0	Covered	T2,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	73	0	0
CntIncr_A	5765374	2105	0	0
CntNoWrap_A	5765374	5139177	0	0
DetectStDropOut_A	5765374	0	0	0
DetectedOut_A	5765374	2748	0	0
DetectedPulseOut_A	5765374	35	0	0
DisabledIdleSt_A	5765374	4974415	0	0
DisabledNoDetection_A	5765374	4976659	0	0
EnterDebounceSt_A	5765374	38	0	0
EnterDetectSt_A	5765374	35	0	0
EnterStableSt_A	5765374	35	0	0
PulseIsPulse_A	5765374	35	0	0
StayInStableSt	5765374	2695	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5765374	6261	0	0
gen_low_level_sva.LowLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	73	0	0
T2	13420	4	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T46	433	0	0	0
T129	0	2	0	0
T131	0	2	0	0
T145	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0
T159	0	2	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	2105	0	0
T2	13420	190	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T32	0	21	0	0
T33	0	70	0	0
T46	433	0	0	0
T129	0	24	0	0
T131	0	97	0	0
T145	0	31	0	0
T156	0	21	0	0
T157	0	35	0	0
T159	0	41	0	0
T165	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5139177	0	0
T1	28795	28313	0	0
T2	13420	7380	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	2748	0	0
T2	13420	85	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T32	0	9	0	0
T33	0	251	0	0
T46	433	0	0	0
T129	0	63	0	0
T131	0	41	0	0
T145	0	75	0	0
T156	0	70	0	0
T157	0	42	0	0
T159	0	50	0	0
T165	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	35	0	0
T2	13420	2	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	433	0	0	0
T129	0	1	0	0
T131	0	1	0	0
T145	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4974415	0	0
T1	28795	28313	0	0
T2	13420	6624	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4976659	0	0
T1	28795	28325	0	0
T2	13420	6640	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	38	0	0
T2	13420	2	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	433	0	0	0
T129	0	1	0	0
T131	0	1	0	0
T145	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	35	0	0
T2	13420	2	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	433	0	0	0
T129	0	1	0	0
T131	0	1	0	0
T145	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	35	0	0
T2	13420	2	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	433	0	0	0
T129	0	1	0	0
T131	0	1	0	0
T145	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	35	0	0
T2	13420	2	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	433	0	0	0
T129	0	1	0	0
T131	0	1	0	0
T145	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	2695	0	0
T2	13420	82	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T32	0	8	0	0
T33	0	249	0	0
T46	433	0	0	0
T129	0	61	0	0
T131	0	39	0	0
T145	0	74	0	0
T156	0	68	0	0
T157	0	40	0	0
T159	0	48	0	0
T165	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	6261	0	0
T1	28795	13	0	0
T2	13420	38	0	0
T3	628	1	0	0
T4	407	0	0	0
T5	566	1	0	0
T6	15908	10	0	0
T12	16327	16	0	0
T13	492	8	0	0
T14	522	4	0	0
T15	527	4	0	0
T46	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	16	0	0
T2	13420	1	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T32	0	1	0	0
T46	433	0	0	0
T82	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T138	0	1	0	0
T145	0	1	0	0
T163	0	1	0	0
T188	0	1	0	0
T190	0	1	0	0