Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1068382754	11656	0	0
auto_block_debounce_ctl_rd_A	1068382754	1862	0	0
auto_block_out_ctl_rd_A	1068382754	2488	0	0
com_det_ctl_0_rd_A	1068382754	4002	0	0
com_det_ctl_1_rd_A	1068382754	4148	0	0
com_det_ctl_2_rd_A	1068382754	4166	0	0
com_det_ctl_3_rd_A	1068382754	4043	0	0
com_out_ctl_0_rd_A	1068382754	4567	0	0
com_out_ctl_1_rd_A	1068382754	4576	0	0
com_out_ctl_2_rd_A	1068382754	4378	0	0
com_out_ctl_3_rd_A	1068382754	4695	0	0
com_pre_det_ctl_0_rd_A	1068382754	1526	0	0
com_pre_det_ctl_1_rd_A	1068382754	1525	0	0
com_pre_det_ctl_2_rd_A	1068382754	1671	0	0
com_pre_det_ctl_3_rd_A	1068382754	1567	0	0
com_pre_sel_ctl_0_rd_A	1068382754	4768	0	0
com_pre_sel_ctl_1_rd_A	1068382754	4611	0	0
com_pre_sel_ctl_2_rd_A	1068382754	4730	0	0
com_pre_sel_ctl_3_rd_A	1068382754	4832	0	0
com_sel_ctl_0_rd_A	1068382754	4625	0	0
com_sel_ctl_1_rd_A	1068382754	4799	0	0
com_sel_ctl_2_rd_A	1068382754	4604	0	0
com_sel_ctl_3_rd_A	1068382754	4744	0	0
ec_rst_ctl_rd_A	1068382754	2543	0	0
intr_enable_rd_A	1068382754	2152	0	0
key_intr_ctl_rd_A	1068382754	2944	0	0
key_intr_debounce_ctl_rd_A	1068382754	1634	0	0
key_invert_ctl_rd_A	1068382754	4236	0	0
pin_allowed_ctl_rd_A	1068382754	5200	0	0
pin_out_ctl_rd_A	1068382754	3861	0	0
pin_out_value_rd_A	1068382754	4241	0	0
regwen_rd_A	1068382754	1819	0	0
ulp_ac_debounce_ctl_rd_A	1068382754	1716	0	0
ulp_ctl_rd_A	1068382754	1651	0	0
ulp_lid_debounce_ctl_rd_A	1068382754	1605	0	0
ulp_pwrb_debounce_ctl_rd_A	1068382754	1559	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	11656	0	0
T2	162366	11	0	0
T3	50910	0	0	0
T5	257033	0	0	0
T6	787473	0	0	0
T7	55498	0	0	0
T12	791916	0	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T27	0	11	0	0
T28	0	10	0	0
T32	0	11	0	0
T33	0	1	0	0
T34	0	18	0	0
T44	0	7	0	0
T46	52060	0	0	0
T59	0	4	0	0
T80	0	11	0	0
T89	0	34	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1862	0	0
T8	615440	0	0	0
T9	125081	0	0	0
T22	123342	0	0	0
T23	91519	13	0	0
T32	0	16	0	0
T39	119405	0	0	0
T42	0	16	0	0
T43	0	16	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T106	0	9	0	0
T260	0	5	0	0
T264	0	2	0	0
T297	0	11	0	0
T298	0	18	0	0
T299	0	12	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	2488	0	0
T8	615440	0	0	0
T9	125081	0	0	0
T22	123342	0	0	0
T23	91519	5	0	0
T32	0	19	0	0
T39	119405	0	0	0
T42	0	8	0	0
T43	0	12	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T106	0	6	0	0
T260	0	7	0	0
T264	0	12	0	0
T297	0	3	0	0
T298	0	25	0	0
T299	0	10	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4002	0	0
T5	257033	0	0	0
T6	787473	34	0	0
T7	55498	0	0	0
T8	0	40	0	0
T11	0	39	0	0
T12	791916	51	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	86	0	0
T46	52060	0	0	0
T53	0	47	0	0
T107	106644	0	0	0
T240	0	44	0	0
T244	0	18	0	0
T249	0	67	0	0
T264	0	136	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4148	0	0
T5	257033	0	0	0
T6	787473	58	0	0
T7	55498	0	0	0
T8	0	47	0	0
T11	0	28	0	0
T12	791916	55	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	63	0	0
T46	52060	0	0	0
T53	0	77	0	0
T107	106644	0	0	0
T240	0	54	0	0
T244	0	23	0	0
T249	0	59	0	0
T264	0	160	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4166	0	0
T5	257033	0	0	0
T6	787473	49	0	0
T7	55498	0	0	0
T8	0	55	0	0
T11	0	62	0	0
T12	791916	34	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	73	0	0
T46	52060	0	0	0
T53	0	67	0	0
T107	106644	0	0	0
T240	0	61	0	0
T244	0	41	0	0
T249	0	67	0	0
T264	0	140	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4043	0	0
T5	257033	0	0	0
T6	787473	49	0	0
T7	55498	0	0	0
T8	0	52	0	0
T11	0	31	0	0
T12	791916	43	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	86	0	0
T46	52060	0	0	0
T53	0	90	0	0
T107	106644	0	0	0
T240	0	41	0	0
T244	0	17	0	0
T249	0	84	0	0
T264	0	185	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4567	0	0
T5	257033	0	0	0
T6	787473	34	0	0
T7	55498	0	0	0
T8	0	62	0	0
T11	0	66	0	0
T12	791916	43	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	68	0	0
T46	52060	0	0	0
T53	0	102	0	0
T107	106644	0	0	0
T240	0	40	0	0
T244	0	24	0	0
T249	0	45	0	0
T264	0	146	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4576	0	0
T5	257033	0	0	0
T6	787473	31	0	0
T7	55498	0	0	0
T8	0	36	0	0
T11	0	44	0	0
T12	791916	37	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	64	0	0
T46	52060	0	0	0
T53	0	84	0	0
T107	106644	0	0	0
T240	0	51	0	0
T244	0	38	0	0
T249	0	50	0	0
T264	0	144	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4378	0	0
T5	257033	0	0	0
T6	787473	44	0	0
T7	55498	0	0	0
T8	0	27	0	0
T11	0	46	0	0
T12	791916	34	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	74	0	0
T46	52060	0	0	0
T53	0	80	0	0
T107	106644	0	0	0
T240	0	52	0	0
T244	0	30	0	0
T249	0	56	0	0
T264	0	138	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4695	0	0
T5	257033	0	0	0
T6	787473	43	0	0
T7	55498	0	0	0
T8	0	41	0	0
T11	0	17	0	0
T12	791916	36	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	61	0	0
T46	52060	0	0	0
T53	0	68	0	0
T107	106644	0	0	0
T240	0	71	0	0
T244	0	33	0	0
T249	0	62	0	0
T264	0	128	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1526	0	0
T17	0	16	0	0
T18	0	54	0	0
T32	391715	10	0	0
T41	173119	0	0	0
T42	76031	0	0	0
T68	113146	0	0	0
T102	273395	0	0	0
T103	40398	0	0	0
T104	59769	0	0	0
T105	50996	0	0	0
T114	93854	0	0	0
T115	250694	0	0	0
T146	0	14	0	0
T266	0	12	0	0
T269	0	9	0	0
T277	0	22	0	0
T300	0	3	0	0
T301	0	5	0	0
T302	0	18	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1525	0	0
T17	0	23	0	0
T18	0	26	0	0
T32	391715	7	0	0
T41	173119	0	0	0
T42	76031	0	0	0
T68	113146	0	0	0
T102	273395	0	0	0
T103	40398	0	0	0
T104	59769	0	0	0
T105	50996	0	0	0
T114	93854	0	0	0
T115	250694	0	0	0
T146	0	17	0	0
T266	0	6	0	0
T269	0	21	0	0
T277	0	15	0	0
T301	0	17	0	0
T302	0	15	0	0
T303	0	3	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1671	0	0
T17	0	54	0	0
T18	0	63	0	0
T130	249093	0	0	0
T146	0	12	0	0
T217	122349	0	0	0
T266	0	23	0	0
T269	0	14	0	0
T277	0	21	0	0
T300	165548	6	0	0
T301	0	8	0	0
T302	0	13	0	0
T303	0	8	0	0
T304	135760	0	0	0
T305	105714	0	0	0
T306	248864	0	0	0
T307	112626	0	0	0
T308	83864	0	0	0
T309	807924	0	0	0
T310	38246	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1567	0	0
T17	0	52	0	0
T18	0	58	0	0
T32	391715	13	0	0
T41	173119	0	0	0
T42	76031	0	0	0
T68	113146	0	0	0
T102	273395	0	0	0
T103	40398	0	0	0
T104	59769	0	0	0
T105	50996	0	0	0
T114	93854	0	0	0
T115	250694	0	0	0
T146	0	11	0	0
T266	0	14	0	0
T269	0	10	0	0
T277	0	14	0	0
T300	0	5	0	0
T301	0	6	0	0
T302	0	18	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4768	0	0
T5	257033	0	0	0
T6	787473	38	0	0
T7	55498	0	0	0
T8	0	61	0	0
T11	0	43	0	0
T12	791916	33	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	53	0	0
T46	52060	0	0	0
T53	0	75	0	0
T107	106644	0	0	0
T240	0	55	0	0
T244	0	33	0	0
T249	0	61	0	0
T264	0	159	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4611	0	0
T5	257033	0	0	0
T6	787473	36	0	0
T7	55498	0	0	0
T8	0	63	0	0
T11	0	23	0	0
T12	791916	37	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	102	0	0
T46	52060	0	0	0
T53	0	79	0	0
T107	106644	0	0	0
T240	0	52	0	0
T244	0	32	0	0
T249	0	66	0	0
T264	0	145	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4730	0	0
T5	257033	0	0	0
T6	787473	44	0	0
T7	55498	0	0	0
T8	0	66	0	0
T11	0	41	0	0
T12	791916	24	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	76	0	0
T46	52060	0	0	0
T53	0	72	0	0
T107	106644	0	0	0
T240	0	40	0	0
T244	0	21	0	0
T249	0	83	0	0
T264	0	114	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4832	0	0
T5	257033	0	0	0
T6	787473	51	0	0
T7	55498	0	0	0
T8	0	41	0	0
T11	0	28	0	0
T12	791916	25	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	58	0	0
T46	52060	0	0	0
T53	0	58	0	0
T107	106644	0	0	0
T240	0	55	0	0
T244	0	54	0	0
T249	0	78	0	0
T264	0	150	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4625	0	0
T5	257033	0	0	0
T6	787473	37	0	0
T7	55498	0	0	0
T8	0	49	0	0
T11	0	38	0	0
T12	791916	28	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	72	0	0
T46	52060	0	0	0
T53	0	77	0	0
T107	106644	0	0	0
T240	0	58	0	0
T244	0	32	0	0
T249	0	82	0	0
T264	0	139	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4799	0	0
T5	257033	0	0	0
T6	787473	56	0	0
T7	55498	0	0	0
T8	0	37	0	0
T11	0	37	0	0
T12	791916	45	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	44	0	0
T46	52060	0	0	0
T53	0	94	0	0
T107	106644	0	0	0
T240	0	49	0	0
T244	0	42	0	0
T249	0	86	0	0
T264	0	121	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4604	0	0
T5	257033	0	0	0
T6	787473	58	0	0
T7	55498	0	0	0
T8	0	46	0	0
T11	0	22	0	0
T12	791916	62	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	68	0	0
T46	52060	0	0	0
T53	0	65	0	0
T107	106644	0	0	0
T240	0	51	0	0
T244	0	32	0	0
T249	0	66	0	0
T264	0	154	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4744	0	0
T5	257033	0	0	0
T6	787473	29	0	0
T7	55498	0	0	0
T8	0	54	0	0
T11	0	36	0	0
T12	791916	67	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	92	0	0
T46	52060	0	0	0
T53	0	83	0	0
T107	106644	0	0	0
T240	0	64	0	0
T244	0	24	0	0
T249	0	68	0	0
T264	0	135	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	2543	0	0
T5	257033	0	0	0
T6	787473	5	0	0
T7	55498	0	0	0
T8	0	12	0	0
T11	0	22	0	0
T12	791916	20	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	91519	0	0	0
T32	0	43	0	0
T46	52060	0	0	0
T51	0	1	0	0
T53	0	38	0	0
T102	0	9	0	0
T107	106644	0	0	0
T249	0	37	0	0
T264	0	48	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	2152	0	0
T32	391715	46	0	0
T41	173119	0	0	0
T42	76031	0	0	0
T68	113146	0	0	0
T102	273395	0	0	0
T103	40398	0	0	0
T104	59769	0	0	0
T105	50996	0	0	0
T114	93854	0	0	0
T115	250694	0	0	0
T146	0	18	0	0
T266	0	17	0	0
T300	0	60	0	0
T301	0	28	0	0
T303	0	1	0	0
T311	0	6	0	0
T312	0	9	0	0
T313	0	19	0	0
T314	0	29	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	2944	0	0
T32	391715	21	0	0
T41	173119	0	0	0
T42	76031	0	0	0
T52	0	106	0	0
T68	113146	0	0	0
T102	273395	0	0	0
T103	40398	0	0	0
T104	59769	0	0	0
T105	50996	0	0	0
T114	93854	0	0	0
T115	250694	0	0	0
T136	0	5	0	0
T138	0	6	0	0
T160	0	4	0	0
T220	0	7	0	0
T266	0	16	0	0
T300	0	2	0	0
T315	0	3	0	0
T316	0	5	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1634	0	0
T17	0	1	0	0
T18	0	37	0	0
T32	391715	11	0	0
T41	173119	0	0	0
T42	76031	0	0	0
T68	113146	0	0	0
T102	273395	0	0	0
T103	40398	0	0	0
T104	59769	0	0	0
T105	50996	0	0	0
T114	93854	0	0	0
T115	250694	0	0	0
T146	0	8	0	0
T266	0	14	0	0
T269	0	8	0	0
T277	0	17	0	0
T300	0	3	0	0
T301	0	16	0	0
T303	0	2	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4236	0	0
T11	807260	0	0	0
T21	0	74	0	0
T32	0	42	0	0
T40	131492	0	0	0
T62	245896	79	0	0
T64	0	55	0	0
T66	236331	0	0	0
T67	128195	0	0	0
T104	0	41	0	0
T125	0	38	0	0
T148	0	69	0	0
T235	49524	0	0	0
T236	10580	0	0	0
T237	109817	0	0	0
T238	201183	0	0	0
T246	102868	0	0	0
T317	0	31	0	0
T318	0	67	0	0
T319	0	44	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	5200	0	0
T10	227207	0	0	0
T21	0	84	0	0
T22	123342	0	0	0
T25	614285	0	0	0
T32	0	89	0	0
T50	248528	51	0	0
T51	302790	0	0	0
T61	119339	0	0	0
T62	245896	0	0	0
T65	63368	0	0	0
T66	0	57	0	0
T72	100973	0	0	0
T126	0	66	0	0
T246	102868	0	0	0
T257	0	86	0	0
T292	0	50	0	0
T320	0	56	0	0
T321	0	69	0	0
T322	0	72	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	3861	0	0
T10	227207	0	0	0
T21	0	91	0	0
T22	123342	0	0	0
T25	614285	0	0	0
T32	0	80	0	0
T50	248528	61	0	0
T51	302790	0	0	0
T61	119339	0	0	0
T62	245896	0	0	0
T65	63368	0	0	0
T66	0	69	0	0
T72	100973	0	0	0
T126	0	33	0	0
T246	102868	0	0	0
T257	0	63	0	0
T292	0	49	0	0
T320	0	42	0	0
T321	0	73	0	0
T322	0	65	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	4241	0	0
T10	227207	0	0	0
T21	0	71	0	0
T22	123342	0	0	0
T25	614285	0	0	0
T32	0	84	0	0
T50	248528	71	0	0
T51	302790	0	0	0
T61	119339	0	0	0
T62	245896	0	0	0
T65	63368	0	0	0
T66	0	83	0	0
T72	100973	0	0	0
T126	0	59	0	0
T246	102868	0	0	0
T257	0	52	0	0
T292	0	34	0	0
T320	0	77	0	0
T321	0	69	0	0
T322	0	66	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1819	0	0
T17	0	23	0	0
T18	0	53	0	0
T52	924828	0	0	0
T146	0	18	0	0
T166	457365	0	0	0
T207	217302	0	0	0
T208	38736	0	0	0
T209	61294	0	0	0
T210	159425	0	0	0
T211	101134	0	0	0
T212	19196	0	0	0
T266	108804	13	0	0
T269	0	4	0	0
T277	0	26	0	0
T301	0	21	0	0
T302	0	20	0	0
T303	0	13	0	0
T323	0	2	0	0
T324	206834	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1716	0	0
T21	233211	3	0	0
T27	403731	0	0	0
T32	391715	13	0	0
T37	862695	0	0	0
T38	130062	0	0	0
T53	116084	0	0	0
T54	109999	0	0	0
T56	0	13	0	0
T59	266764	0	0	0
T60	281603	0	0	0
T73	0	6	0	0
T84	0	3	0	0
T101	207690	0	0	0
T116	0	20	0	0
T117	0	8	0	0
T119	0	7	0	0
T300	0	4	0	0
T325	0	7	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1651	0	0
T21	233211	8	0	0
T27	403731	0	0	0
T32	391715	15	0	0
T37	862695	0	0	0
T38	130062	0	0	0
T53	116084	0	0	0
T54	109999	0	0	0
T59	266764	0	0	0
T60	281603	0	0	0
T73	0	5	0	0
T101	207690	0	0	0
T116	0	10	0	0
T117	0	7	0	0
T119	0	4	0	0
T300	0	10	0	0
T325	0	7	0	0
T326	0	3	0	0
T327	0	4	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1605	0	0
T21	233211	3	0	0
T27	403731	0	0	0
T32	391715	2	0	0
T37	862695	0	0	0
T38	130062	0	0	0
T53	116084	0	0	0
T54	109999	6	0	0
T56	0	4	0	0
T59	266764	0	0	0
T60	281603	0	0	0
T73	0	5	0	0
T84	0	11	0	0
T85	0	13	0	0
T101	207690	0	0	0
T116	0	6	0	0
T117	0	2	0	0
T327	0	3	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1559	0	0
T21	233211	1	0	0
T27	403731	0	0	0
T32	391715	16	0	0
T37	862695	0	0	0
T38	130062	0	0	0
T53	116084	0	0	0
T54	109999	9	0	0
T56	0	7	0	0
T59	266764	0	0	0
T60	281603	0	0	0
T73	0	1	0	0
T84	0	3	0	0
T85	0	3	0	0
T101	207690	0	0	0
T116	0	13	0	0
T117	0	8	0	0
T326	0	8	0	0