Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T21
1	-	Covered	T1,T2,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	108130366	0	0
DstReqKnown_A	204641308	177045344	0	0
SrcAckBusyChk_A	2147483647	117452	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	108130366	0	0
T1	1117288	149441	0	0
T2	1623660	12102	0	0
T3	509100	0	0	0
T4	391408	0	0	0
T5	2570330	0	0	0
T6	7874730	79762	0	0
T7	110996	0	0	0
T8	615440	29597	0	0
T9	125081	1517	0	0
T10	0	21565	0	0
T11	0	60395	0	0
T12	7919160	69534	0	0
T13	2461030	0	0	0
T14	2507640	0	0	0
T15	659480	0	0	0
T22	123342	0	0	0
T23	0	2923	0	0
T24	0	2751	0	0
T25	0	18915	0	0
T27	0	16560	0	0
T32	0	3025	0	0
T38	0	16043	0	0
T39	119405	11064	0	0
T40	0	8134	0	0
T41	0	5095	0	0
T42	0	3526	0	0
T43	0	3546	0	0
T44	0	3816	0	0
T45	0	5048	0	0
T46	104120	0	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204641308	177045344	0	0
T1	979030	963050	0	0
T2	456280	251634	0	0
T3	21352	7752	0	0
T4	13838	238	0	0
T5	19244	5644	0	0
T6	540872	526422	0	0
T12	555118	513570	0	0
T13	16728	3128	0	0
T14	17748	4148	0	0
T15	17918	4318	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117452	0	0
T1	1117288	96	0	0
T2	1623660	32	0	0
T3	509100	0	0	0
T4	391408	0	0	0
T5	2570330	0	0	0
T6	7874730	48	0	0
T7	110996	0	0	0
T8	615440	18	0	0
T9	125081	2	0	0
T10	0	81	0	0
T11	0	36	0	0
T12	7919160	42	0	0
T13	2461030	0	0	0
T14	2507640	0	0	0
T15	659480	0	0	0
T22	123342	0	0	0
T23	0	7	0	0
T24	0	7	0	0
T25	0	27	0	0
T27	0	23	0	0
T32	0	8	0	0
T38	0	10	0	0
T39	119405	48	0	0
T40	0	9	0	0
T41	0	6	0	0
T42	0	9	0	0
T43	0	8	0	0
T44	0	15	0	0
T45	0	12	0	0
T46	104120	0	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4748474	4736914	0	0
T2	5520444	5508476	0	0
T3	1730940	1727880	0	0
T4	1663484	1660424	0	0
T5	8739122	8735824	0	0
T6	26774082	26731650	0	0
T12	26925144	26888254	0	0
T13	8367502	8364340	0	0
T14	8525976	8524038	0	0
T15	2242232	2238866	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T52,T26,T16
1	-	Covered	T1,T2,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T6
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T6
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1051016	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1177	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1051016	0	0
T1	139661	10525	0	0
T2	162366	742	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	8812	0	0
T8	0	1463	0	0
T10	0	2305	0	0
T11	0	8376	0	0
T12	791916	0	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T19	0	1049	0	0
T20	0	1178	0	0
T21	0	457	0	0
T53	0	7167	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1177	0	0
T1	139661	7	0	0
T2	162366	2	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	5	0	0
T8	0	1	0	0
T10	0	8	0	0
T11	0	5	0	0
T12	791916	0	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T19	0	3	0	0
T20	0	3	0	0
T21	0	1	0	0
T53	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1827877	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	2051	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1827877	0	0
T1	139661	18293	0	0
T2	162366	1443	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	9746	0	0
T8	0	3064	0	0
T9	0	741	0	0
T10	0	2242	0	0
T12	791916	9517	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	2041	0	0
T39	0	1329	0	0
T51	0	1408	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	2051	0	0
T1	139661	12	0	0
T2	162366	4	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	6	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	9	0	0
T12	791916	6	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	3	0	0
T39	0	6	0	0
T51	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1027249	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1023	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1027249	0	0
T19	69396	1080	0	0
T20	66305	1191	0	0
T21	233211	487	0	0
T27	403731	0	0	0
T28	0	312	0	0
T32	0	738	0	0
T37	862695	0	0	0
T38	130062	0	0	0
T44	0	237	0	0
T53	116084	0	0	0
T54	0	1995	0	0
T55	0	1458	0	0
T56	0	915	0	0
T57	0	998	0	0
T58	59408	0	0	0
T59	266764	0	0	0
T60	281603	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1023	0	0
T19	69396	3	0	0
T20	66305	3	0	0
T21	233211	1	0	0
T27	403731	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T37	862695	0	0	0
T38	130062	0	0	0
T44	0	1	0	0
T53	116084	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	59408	0	0	0
T59	266764	0	0	0
T60	281603	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1021757	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1019	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1021757	0	0
T19	69396	1067	0	0
T20	66305	1185	0	0
T21	233211	473	0	0
T27	403731	0	0	0
T28	0	309	0	0
T32	0	718	0	0
T37	862695	0	0	0
T38	130062	0	0	0
T44	0	235	0	0
T53	116084	0	0	0
T54	0	1985	0	0
T55	0	1448	0	0
T56	0	889	0	0
T57	0	996	0	0
T58	59408	0	0	0
T59	266764	0	0	0
T60	281603	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1019	0	0
T19	69396	3	0	0
T20	66305	3	0	0
T21	233211	1	0	0
T27	403731	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T37	862695	0	0	0
T38	130062	0	0	0
T44	0	1	0	0
T53	116084	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	59408	0	0	0
T59	266764	0	0	0
T60	281603	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1043319	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1027	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1043319	0	0
T19	69396	1050	0	0
T20	66305	1179	0	0
T21	233211	461	0	0
T27	403731	0	0	0
T28	0	304	0	0
T32	0	704	0	0
T37	862695	0	0	0
T38	130062	0	0	0
T44	0	233	0	0
T53	116084	0	0	0
T54	0	1965	0	0
T55	0	1436	0	0
T56	0	872	0	0
T57	0	994	0	0
T58	59408	0	0	0
T59	266764	0	0	0
T60	281603	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1027	0	0
T19	69396	3	0	0
T20	66305	3	0	0
T21	233211	1	0	0
T27	403731	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T37	862695	0	0	0
T38	130062	0	0	0
T44	0	1	0	0
T53	116084	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	59408	0	0	0
T59	266764	0	0	0
T60	281603	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T13,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T13,T22
1	1	Covered	T2,T13,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T13,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T13,T22
1	1	Covered	T2,T13,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T13,T22
0	0	1	Covered	T2,T13,T22
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T13,T22
0	0	1	Covered	T2,T13,T22
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	2753388	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	2948	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	2753388	0	0
T2	162366	17504	0	0
T3	50910	0	0	0
T5	257033	0	0	0
T6	787473	0	0	0
T7	55498	0	0	0
T12	791916	0	0	0
T13	246103	35005	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T21	0	8852	0	0
T22	0	17385	0	0
T46	52060	0	0	0
T58	0	8164	0	0
T59	0	66970	0	0
T61	0	17770	0	0
T62	0	34890	0	0
T63	0	7034	0	0
T64	0	8908	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	2948	0	0
T2	162366	40	0	0
T3	50910	0	0	0
T5	257033	0	0	0
T6	787473	0	0	0
T7	55498	0	0	0
T12	791916	0	0	0
T13	246103	20	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T21	0	20	0	0
T22	0	20	0	0
T46	52060	0	0	0
T58	0	20	0	0
T59	0	40	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T13,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T13,T14
1	1	Covered	T2,T13,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T13,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T13,T14
1	1	Covered	T2,T13,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T13,T14
0	0	1	Covered	T2,T13,T14
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T13,T14
0	0	1	Covered	T2,T13,T14
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	5172592	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	6169	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	5172592	0	0
T2	162366	32302	0	0
T3	50910	0	0	0
T5	257033	0	0	0
T6	787473	0	0	0
T7	55498	0	0	0
T12	791916	0	0	0
T13	246103	1497	0	0
T14	250764	35184	0	0
T15	65948	8476	0	0
T22	0	734	0	0
T46	52060	0	0	0
T48	0	8324	0	0
T50	0	34173	0	0
T61	0	717	0	0
T62	0	1984	0	0
T65	0	8679	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	6169	0	0
T2	162366	75	0	0
T3	50910	0	0	0
T5	257033	0	0	0
T6	787473	0	0	0
T7	55498	0	0	0
T12	791916	0	0	0
T13	246103	1	0	0
T14	250764	20	0	0
T15	65948	20	0	0
T22	0	1	0	0
T46	52060	0	0	0
T48	0	20	0	0
T50	0	20	0	0
T61	0	1	0	0
T62	0	1	0	0
T65	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	6220743	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	7371	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	6220743	0	0
T1	139661	19220	0	0
T2	162366	34594	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	10318	0	0
T8	0	3449	0	0
T12	791916	10040	0	0
T13	246103	1499	0	0
T14	250764	35441	0	0
T15	65948	8782	0	0
T39	0	1439	0	0
T48	0	8404	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	7371	0	0
T1	139661	12	0	0
T2	162366	79	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	6	0	0
T8	0	2	0	0
T12	791916	6	0	0
T13	246103	1	0	0
T14	250764	20	0	0
T15	65948	20	0	0
T39	0	6	0	0
T48	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T14,T15

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T14,T15
1	1	Covered	T2,T14,T15

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T14,T15

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T14,T15
1	1	Covered	T2,T14,T15

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T14,T15
0	0	1	Covered	T2,T14,T15
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T14,T15
0	0	1	Covered	T2,T14,T15
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	5113657	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	6080	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	5113657	0	0
T2	162366	31460	0	0
T3	50910	0	0	0
T5	257033	0	0	0
T6	787473	0	0	0
T7	55498	0	0	0
T12	791916	0	0	0
T13	246103	0	0	0
T14	250764	35322	0	0
T15	65948	8630	0	0
T21	0	8672	0	0
T46	52060	0	0	0
T48	0	8364	0	0
T50	0	34353	0	0
T53	0	34632	0	0
T65	0	8719	0	0
T66	0	33953	0	0
T67	0	16933	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	6080	0	0
T2	162366	73	0	0
T3	50910	0	0	0
T5	257033	0	0	0
T6	787473	0	0	0
T7	55498	0	0	0
T12	791916	0	0	0
T13	246103	0	0	0
T14	250764	20	0	0
T15	65948	20	0	0
T21	0	20	0	0
T46	52060	0	0	0
T48	0	20	0	0
T50	0	20	0	0
T53	0	20	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T3,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T3,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1070118	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1035	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1070118	0	0
T2	162366	371	0	0
T3	50910	344	0	0
T5	257033	1995	0	0
T6	787473	0	0	0
T7	55498	369	0	0
T12	791916	0	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T28	0	738	0	0
T30	0	1940	0	0
T31	0	716	0	0
T32	0	317	0	0
T33	0	1906	0	0
T34	0	253	0	0
T46	52060	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1035	0	0
T2	162366	1	0	0
T3	50910	1	0	0
T5	257033	1	0	0
T6	787473	0	0	0
T7	55498	1	0	0
T12	791916	0	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T46	52060	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1846109	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	2053	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1846109	0	0
T1	139661	18214	0	0
T2	162366	1067	0	0
T3	50910	342	0	0
T4	48926	0	0	0
T5	257033	1993	0	0
T6	787473	9678	0	0
T7	0	361	0	0
T8	0	3046	0	0
T9	0	725	0	0
T12	791916	9463	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T39	0	1317	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	2053	0	0
T1	139661	12	0	0
T2	162366	3	0	0
T3	50910	1	0	0
T4	48926	0	0	0
T5	257033	1	0	0
T6	787473	6	0	0
T7	0	1	0	0
T8	0	2	0	0
T9	0	1	0	0
T12	791916	6	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T39	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T23,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T23,T24
1	1	Covered	T2,T23,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T23,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T23,T24
1	1	Covered	T2,T23,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T23,T24
0	0	1	Covered	T2,T23,T24
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T23,T24
0	0	1	Covered	T2,T23,T24
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1231739	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1392	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1231739	0	0
T2	162366	4114	0	0
T3	50910	0	0	0
T5	257033	0	0	0
T6	787473	0	0	0
T7	55498	0	0	0
T12	791916	0	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	0	1670	0	0
T24	0	1558	0	0
T27	0	10935	0	0
T32	0	1961	0	0
T41	0	2562	0	0
T42	0	2365	0	0
T43	0	2138	0	0
T44	0	2314	0	0
T45	0	2530	0	0
T46	52060	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1392	0	0
T2	162366	10	0	0
T3	50910	0	0	0
T5	257033	0	0	0
T6	787473	0	0	0
T7	55498	0	0	0
T12	791916	0	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	0	4	0	0
T24	0	4	0	0
T27	0	15	0	0
T32	0	5	0	0
T41	0	3	0	0
T42	0	6	0	0
T43	0	5	0	0
T44	0	9	0	0
T45	0	6	0	0
T46	52060	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T23,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T23,T24
1	1	Covered	T2,T23,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T23,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T23,T24
1	1	Covered	T2,T23,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T23,T24
0	0	1	Covered	T2,T23,T24
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T23,T24
0	0	1	Covered	T2,T23,T24
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1139894	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1223	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1139894	0	0
T2	162366	2228	0	0
T3	50910	0	0	0
T5	257033	0	0	0
T6	787473	0	0	0
T7	55498	0	0	0
T12	791916	0	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	0	1253	0	0
T24	0	1193	0	0
T27	0	5625	0	0
T32	0	1064	0	0
T41	0	2533	0	0
T42	0	1161	0	0
T43	0	1408	0	0
T44	0	1502	0	0
T45	0	2518	0	0
T46	52060	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1223	0	0
T2	162366	6	0	0
T3	50910	0	0	0
T5	257033	0	0	0
T6	787473	0	0	0
T7	55498	0	0	0
T12	791916	0	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T23	0	3	0	0
T24	0	3	0	0
T27	0	8	0	0
T32	0	3	0	0
T41	0	3	0	0
T42	0	3	0	0
T43	0	3	0	0
T44	0	6	0	0
T45	0	6	0	0
T46	52060	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	7105792	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	7431	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	7105792	0	0
T8	615440	110680	0	0
T9	125081	0	0	0
T10	0	18805	0	0
T22	123342	0	0	0
T25	0	82187	0	0
T37	0	69068	0	0
T38	0	163594	0	0
T39	119405	0	0	0
T40	0	42992	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	3713	0	0
T69	0	44091	0	0
T70	0	67109	0	0
T71	0	22049	0	0
T72	100973	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	7431	0	0
T8	615440	65	0	0
T9	125081	0	0	0
T10	0	59	0	0
T22	123342	0	0	0
T25	0	100	0	0
T37	0	68	0	0
T38	0	98	0	0
T39	119405	0	0	0
T40	0	51	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	51	0	0
T69	0	51	0	0
T70	0	74	0	0
T71	0	51	0	0
T72	100973	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	6956839	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	7323	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	6956839	0	0
T8	615440	123826	0	0
T9	125081	0	0	0
T10	0	26463	0	0
T22	123342	0	0	0
T25	0	64380	0	0
T37	0	68736	0	0
T38	0	135041	0	0
T39	119405	0	0	0
T40	0	42239	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	3826	0	0
T69	0	43881	0	0
T70	0	76739	0	0
T71	0	21839	0	0
T72	100973	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	7323	0	0
T8	615440	74	0	0
T9	125081	0	0	0
T10	0	86	0	0
T22	123342	0	0	0
T25	0	79	0	0
T37	0	68	0	0
T38	0	81	0	0
T39	119405	0	0	0
T40	0	51	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	51	0	0
T69	0	51	0	0
T70	0	85	0	0
T71	0	51	0	0
T72	100973	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	6693675	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	7230	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	6693675	0	0
T8	615440	106307	0	0
T9	125081	0	0	0
T10	0	21106	0	0
T22	123342	0	0	0
T25	0	58887	0	0
T37	0	67020	0	0
T38	0	127653	0	0
T39	119405	0	0	0
T40	0	41504	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	3749	0	0
T69	0	43671	0	0
T70	0	76381	0	0
T71	0	21629	0	0
T72	100973	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	7230	0	0
T8	615440	64	0	0
T9	125081	0	0	0
T10	0	72	0	0
T22	123342	0	0	0
T25	0	73	0	0
T37	0	67	0	0
T38	0	77	0	0
T39	119405	0	0	0
T40	0	51	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	51	0	0
T69	0	51	0	0
T70	0	85	0	0
T71	0	51	0	0
T72	100973	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	6988194	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	7462	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	6988194	0	0
T8	615440	147294	0	0
T9	125081	0	0	0
T10	0	21344	0	0
T22	123342	0	0	0
T25	0	53920	0	0
T37	0	68424	0	0
T38	0	113128	0	0
T39	119405	0	0	0
T40	0	40727	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	3813	0	0
T69	0	43461	0	0
T70	0	51139	0	0
T71	0	21419	0	0
T72	100973	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	7462	0	0
T8	615440	89	0	0
T9	125081	0	0	0
T10	0	73	0	0
T22	123342	0	0	0
T25	0	67	0	0
T37	0	68	0	0
T38	0	69	0	0
T39	119405	0	0	0
T40	0	51	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	51	0	0
T69	0	51	0	0
T70	0	57	0	0
T71	0	51	0	0
T72	100973	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1273751	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1251	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1273751	0	0
T8	615440	3474	0	0
T9	125081	0	0	0
T10	0	2621	0	0
T22	123342	0	0	0
T25	0	2155	0	0
T37	0	10135	0	0
T38	0	16043	0	0
T39	119405	0	0	0
T40	0	968	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	81	0	0
T69	0	718	0	0
T70	0	2801	0	0
T71	0	499	0	0
T72	100973	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1251	0	0
T8	615440	2	0	0
T9	125081	0	0	0
T10	0	9	0	0
T22	123342	0	0	0
T25	0	3	0	0
T37	0	10	0	0
T38	0	10	0	0
T39	119405	0	0	0
T40	0	1	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	3	0	0
T71	0	1	0	0
T72	100973	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1206147	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1212	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1206147	0	0
T8	615440	3367	0	0
T9	125081	0	0	0
T10	0	2268	0	0
T22	123342	0	0	0
T25	0	2125	0	0
T37	0	10035	0	0
T38	0	15671	0	0
T39	119405	0	0	0
T40	0	929	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	100	0	0
T69	0	708	0	0
T70	0	2771	0	0
T71	0	489	0	0
T72	100973	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1212	0	0
T8	615440	2	0	0
T9	125081	0	0	0
T10	0	9	0	0
T22	123342	0	0	0
T25	0	3	0	0
T37	0	10	0	0
T38	0	10	0	0
T39	119405	0	0	0
T40	0	1	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	3	0	0
T71	0	1	0	0
T72	100973	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1263934	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1268	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1263934	0	0
T8	615440	3266	0	0
T9	125081	0	0	0
T10	0	2149	0	0
T22	123342	0	0	0
T25	0	2095	0	0
T37	0	9935	0	0
T38	0	15312	0	0
T39	119405	0	0	0
T40	0	891	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	88	0	0
T69	0	698	0	0
T70	0	2741	0	0
T71	0	479	0	0
T72	100973	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1268	0	0
T8	615440	2	0	0
T9	125081	0	0	0
T10	0	9	0	0
T22	123342	0	0	0
T25	0	3	0	0
T37	0	10	0	0
T38	0	10	0	0
T39	119405	0	0	0
T40	0	1	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	3	0	0
T71	0	1	0	0
T72	100973	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T10,T25
0	0	1	Covered	T8,T10,T25
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1245479	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1254	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1245479	0	0
T8	615440	3168	0	0
T9	125081	0	0	0
T10	0	2499	0	0
T22	123342	0	0	0
T25	0	2065	0	0
T37	0	9835	0	0
T38	0	14940	0	0
T39	119405	0	0	0
T40	0	862	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	89	0	0
T69	0	688	0	0
T70	0	2711	0	0
T71	0	469	0	0
T72	100973	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1254	0	0
T8	615440	2	0	0
T9	125081	0	0	0
T10	0	9	0	0
T22	123342	0	0	0
T25	0	3	0	0
T37	0	10	0	0
T38	0	10	0	0
T39	119405	0	0	0
T40	0	1	0	0
T47	206860	0	0	0
T48	60726	0	0	0
T49	49058	0	0	0
T50	248528	0	0	0
T51	302790	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	3	0	0
T71	0	1	0	0
T72	100973	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	7682119	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	8136	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	7682119	0	0
T1	139661	19345	0	0
T2	162366	750	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	10372	0	0
T8	0	111263	0	0
T9	0	768	0	0
T10	0	18997	0	0
T12	791916	10155	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	82369	0	0
T39	0	1473	0	0
T40	0	43356	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	8136	0	0
T1	139661	12	0	0
T2	162366	2	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	6	0	0
T8	0	65	0	0
T9	0	1	0	0
T10	0	59	0	0
T12	791916	6	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	100	0	0
T39	0	6	0	0
T40	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	7451374	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	7938	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	7451374	0	0
T1	139661	19258	0	0
T2	162366	746	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	10308	0	0
T8	0	124544	0	0
T10	0	26893	0	0
T11	0	10430	0	0
T12	791916	8662	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	64520	0	0
T39	0	1461	0	0
T40	0	42570	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	7938	0	0
T1	139661	12	0	0
T2	162366	2	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	6	0	0
T8	0	74	0	0
T10	0	86	0	0
T11	0	6	0	0
T12	791916	5	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	79	0	0
T39	0	6	0	0
T40	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	7255841	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	7910	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	7255841	0	0
T1	139661	19177	0	0
T2	162366	742	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	10272	0	0
T8	0	106950	0	0
T10	0	21585	0	0
T11	0	10388	0	0
T12	791916	8606	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	59015	0	0
T39	0	1449	0	0
T40	0	41834	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	7910	0	0
T1	139661	12	0	0
T2	162366	2	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	6	0	0
T8	0	64	0	0
T10	0	72	0	0
T11	0	6	0	0
T12	791916	5	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	73	0	0
T39	0	6	0	0
T40	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	7548482	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	8123	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	7548482	0	0
T1	139661	19093	0	0
T2	162366	738	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	10209	0	0
T8	0	148209	0	0
T10	0	21551	0	0
T11	0	10323	0	0
T12	791916	8578	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	54036	0	0
T39	0	1437	0	0
T40	0	41083	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	8123	0	0
T1	139661	12	0	0
T2	162366	2	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	6	0	0
T8	0	89	0	0
T10	0	73	0	0
T11	0	6	0	0
T12	791916	5	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	67	0	0
T39	0	6	0	0
T40	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1773964	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1954	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1773964	0	0
T1	139661	19019	0	0
T2	162366	734	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	10143	0	0
T8	0	3440	0	0
T9	0	761	0	0
T10	0	2462	0	0
T12	791916	9970	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	2143	0	0
T39	0	1425	0	0
T40	0	956	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1954	0	0
T1	139661	12	0	0
T2	162366	2	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	6	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	9	0	0
T12	791916	6	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	3	0	0
T39	0	6	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1730534	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1889	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1730534	0	0
T1	139661	18904	0	0
T2	162366	730	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	10083	0	0
T8	0	3320	0	0
T10	0	2133	0	0
T11	0	10224	0	0
T12	791916	8482	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	2113	0	0
T39	0	1413	0	0
T40	0	916	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1889	0	0
T1	139661	12	0	0
T2	162366	2	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	6	0	0
T8	0	2	0	0
T10	0	9	0	0
T11	0	6	0	0
T12	791916	5	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	3	0	0
T39	0	6	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1708258	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1873	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1708258	0	0
T1	139661	18803	0	0
T2	162366	726	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	10048	0	0
T8	0	3231	0	0
T10	0	2590	0	0
T11	0	10176	0	0
T12	791916	8418	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	2083	0	0
T39	0	1401	0	0
T40	0	881	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1873	0	0
T1	139661	12	0	0
T2	162366	2	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	6	0	0
T8	0	2	0	0
T10	0	9	0	0
T11	0	6	0	0
T12	791916	5	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	3	0	0
T39	0	6	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1735887	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1912	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1735887	0	0
T1	139661	18712	0	0
T2	162366	722	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	9999	0	0
T8	0	3114	0	0
T10	0	2347	0	0
T11	0	10103	0	0
T12	791916	8363	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	2053	0	0
T39	0	1389	0	0
T40	0	844	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1912	0	0
T1	139661	12	0	0
T2	162366	2	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	6	0	0
T8	0	2	0	0
T10	0	9	0	0
T11	0	6	0	0
T12	791916	5	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	3	0	0
T39	0	6	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1768343	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1953	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1768343	0	0
T1	139661	18625	0	0
T2	162366	718	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	9954	0	0
T8	0	3419	0	0
T9	0	756	0	0
T10	0	2417	0	0
T12	791916	9731	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	2137	0	0
T39	0	1377	0	0
T40	0	944	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1953	0	0
T1	139661	12	0	0
T2	162366	2	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	6	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	9	0	0
T12	791916	6	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	3	0	0
T39	0	6	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1734102	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1916	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1734102	0	0
T1	139661	18544	0	0
T2	162366	714	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	9903	0	0
T8	0	3305	0	0
T10	0	2084	0	0
T11	0	10011	0	0
T12	791916	8238	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	2107	0	0
T39	0	1365	0	0
T40	0	907	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1916	0	0
T1	139661	12	0	0
T2	162366	2	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	6	0	0
T8	0	2	0	0
T10	0	9	0	0
T11	0	6	0	0
T12	791916	5	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	3	0	0
T39	0	6	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1695854	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1877	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1695854	0	0
T1	139661	18464	0	0
T2	162366	710	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	9843	0	0
T8	0	3214	0	0
T10	0	2616	0	0
T11	0	9962	0	0
T12	791916	8186	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	2077	0	0
T39	0	1353	0	0
T40	0	878	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1877	0	0
T1	139661	12	0	0
T2	162366	2	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	6	0	0
T8	0	2	0	0
T10	0	9	0	0
T11	0	6	0	0
T12	791916	5	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	3	0	0
T39	0	6	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T12
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1736062	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1909	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1736062	0	0
T1	139661	18370	0	0
T2	162366	706	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	9789	0	0
T8	0	3080	0	0
T10	0	2295	0	0
T11	0	9919	0	0
T12	791916	8146	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	2047	0	0
T39	0	1341	0	0
T40	0	840	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1909	0	0
T1	139661	12	0	0
T2	162366	2	0	0
T3	50910	0	0	0
T4	48926	0	0	0
T5	257033	0	0	0
T6	787473	6	0	0
T8	0	2	0	0
T10	0	9	0	0
T11	0	6	0	0
T12	791916	5	0	0
T13	246103	0	0	0
T14	250764	0	0	0
T15	65948	0	0	0
T25	0	3	0	0
T39	0	6	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T21
1	-	Covered	T19,T20,T21

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1068382754	1056277	0	0
DstReqKnown_A	6018862	5207216	0	0
SrcAckBusyChk_A	1068382754	1063	0	0
SrcBusyKnown_A	1068382754	1066825072	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1056277	0	0
T19	69396	2176	0	0
T20	66305	2501	0	0
T21	233211	964	0	0
T27	403731	0	0	0
T28	0	624	0	0
T32	0	1453	0	0
T34	0	1052	0	0
T37	862695	0	0	0
T38	130062	0	0	0
T44	0	473	0	0
T53	116084	0	0	0
T55	0	3410	0	0
T57	0	1744	0	0
T58	59408	0	0	0
T59	266764	0	0	0
T60	281603	0	0	0
T73	0	507	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6018862	5207216	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1063	0	0
T19	69396	6	0	0
T20	66305	6	0	0
T21	233211	2	0	0
T27	403731	0	0	0
T28	0	2	0	0
T32	0	4	0	0
T34	0	4	0	0
T37	862695	0	0	0
T38	130062	0	0	0
T44	0	2	0	0
T53	116084	0	0	0
T55	0	2	0	0
T57	0	2	0	0
T58	59408	0	0	0
T59	266764	0	0	0
T60	281603	0	0	0
T73	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1068382754	1066825072	0	0
T1	139661	139321	0	0
T2	162366	162014	0	0
T3	50910	50820	0	0
T4	48926	48836	0	0
T5	257033	256936	0	0
T6	787473	786225	0	0
T12	791916	790831	0	0
T13	246103	246010	0	0
T14	250764	250707	0	0
T15	65948	65849	0	0