Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_pin_in_value_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_pin_in_value_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_pin_in_value_cg 100.00 1 100 1 64 64




Group Instance : sysrst_ctrl_pin_in_value_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_pin_in_value_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 0 16 100.00


Variables for Group Instance sysrst_ctrl_pin_in_value_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_ac_present 2 0 2 100.00 100 1 1 2
cp_ec_rst_l 2 0 2 100.00 100 1 1 2
cp_flash_wp_l 2 0 2 100.00 100 1 1 2
cp_key0_in 2 0 2 100.00 100 1 1 2
cp_key1_in 2 0 2 100.00 100 1 1 2
cp_key2_in 2 0 2 100.00 100 1 1 2
cp_lid_open 2 0 2 100.00 100 1 1 2
cp_pwrb_in 2 0 2 100.00 100 1 1 2


Summary for Variable cp_ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1078 1 T20 13 T62 19 T52 2
auto[1] 1086 1 T20 18 T62 26 T52 3



Summary for Variable cp_ec_rst_l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst_l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1084 1 T20 18 T62 22 T52 2
auto[1] 1080 1 T20 13 T62 23 T52 3



Summary for Variable cp_flash_wp_l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_flash_wp_l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1077 1 T20 13 T62 21 T52 4
auto[1] 1087 1 T20 18 T62 24 T52 1



Summary for Variable cp_key0_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1127 1 T20 17 T62 23 T52 1
auto[1] 1037 1 T20 14 T62 22 T52 4



Summary for Variable cp_key1_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1071 1 T20 14 T62 26 T52 2
auto[1] 1093 1 T20 17 T62 19 T52 3



Summary for Variable cp_key2_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1104 1 T20 14 T62 24 T52 3
auto[1] 1060 1 T20 17 T62 21 T52 2



Summary for Variable cp_lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_lid_open

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1070 1 T20 17 T62 15 T52 3
auto[1] 1094 1 T20 14 T62 30 T52 2



Summary for Variable cp_pwrb_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1069 1 T20 17 T62 16 T52 2
auto[1] 1095 1 T20 14 T62 29 T52 3

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