Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1704

1

T1

31

T14

11

T2

6

auto[1]

669

1

T1

5

T14

13

T2

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1828

1

T1

11

T14

21

T2

8

auto[1]

545

1

T1

25

T14

3

T3

7

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1690

1

T1

36

T14

24

T2

8

auto[1]

683

1

T3

5

T7

4

T9

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1701

1

T1

20

T14

18

T2

6

auto[1]

672

1

T1

16

T14

6

T2

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2231

1

T1

32

T14

24

T2

8

auto[1]

142

1

T1

4

T12

3

T13

5

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2192

1

T1

36

T14

14

T2

6

auto[1]

181

1

T14

10

T2

2

T9

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2225

1

T1

16

T14

24

T2

6

auto[1]

148

1

T1

20

T2

2

T13

5

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2262

1

T1

27

T14

21

T2

8

auto[1]

111

1

T1

9

T14

3

T9

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2216

1

T1

31

T14

17

T2

8

auto[1]

157

1

T1

5

T14

7

T12

3

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1789

1

T1

32

T14

24

T2

8

auto[1]

584

1

T1

4

T3

5

T7

6

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1077

1

T3

7

T7

7

T10

8

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

53

1

T12

3

T74

2

T122

22

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

48

1

T74

8

T350

5

T139

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

13

1

T121

1

T259

4

T354

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

23

1

T259

6

T357

6

T358

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T357

2

T359

2

T246

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

11

1

T1

5

T14

3

T12

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T183

3

T360

4

T361

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

74

1

T1

16

T74

3

T121

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T86

2

T177

2

T362

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12

1

T121

3

T122

2

T363

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

11

1

T360

2

T362

4

T248

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T1

4

T361

2

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T13

5

T261

2

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

72

1

T14

6

T9

1

T73

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T364

3

T365

2

T366

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

23

1

T14

4

T113

2

T367

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T13

5

T367

1

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

13

1

T12

3

T259

3

T351

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T97

5

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

7

1

T2

2

T270

2

T326

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T358

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

5

1

T270

2

T267

3

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T351

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

130

1

T14

4

T13

5

T34

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

110

1

T39

1

T122

11

T259

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

37

1

T122

9

T302

7

T116

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

137

1

T9

1

T12

3

T13

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

68

1

T14

6

T2

2

T81

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

47

1

T270

4

T349

7

T142

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

32

1

T271

5

T102

1

T103

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

142

1

T73

3

T74

2

T97

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

86

1

T12

3

T81

5

T302

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

54

1

T124

3

T259

3

T36

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

34

1

T34

5

T271

5

T149

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

54

1

T263

4

T350

5

T364

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T273

4

T276

5

T368

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T34

3

T347

5

T100

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

27

1

T10

2

T34

2

T271

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

78

1

T39

2

T122

2

T261

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

35

1

T1

5

T14

3

T121

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T1

4

T124

4

T262

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T302

4

T347

2

T36

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

63

1

T1

16

T266

5

T177

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

49

1

T74

7

T349

3

T357

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

22

1

T7

3

T369

1

T86

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T3

2

T105

2

T89

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T121

1

T259

11

T103

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T12

1

T36

2

T126

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

19

1

T3

3

T357

2

T370

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T7

2

T10

3

T39

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

31

1

T3

2

T10

3

T81

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T7

1

T39

1

T264

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T7

1

T303

1

T116

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T353

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded