Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1176

1

T5

11

T22

14

T16

11

auto[1]

1144

1

T5

9

T22

6

T16

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

552

1

T5

6

T22

5

T16

3

from_0to1

549

1

T5

6

T22

5

T16

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1151

1

T5

8

T22

7

T16

9

auto[1]

1169

1

T5

12

T22

13

T16

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1158

1

T5

11

T22

8

T16

8

auto[1]

1162

1

T5

9

T22

12

T16

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T5

4

T22

1

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T22

1

T16

1

T60

1

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T5

1

T22

2

T16

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T5

1

T63

1

T131

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T70

1

T131

1

T133

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T16

1

T60

1

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T5

2

T16

1

T60

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T22

1

T63

1

T133

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T61

1

T63

1

T133

2

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T22

1

T60

1

T61

1

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T60

1

T63

1

T70

1

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T16

1

T110

1

T213

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T22

1

T63

1

T133

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T22

1

T16

1

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T5

3

T61

1

T131

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T5

1

T22

2

T16

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1179

1

T5

12

T22

9

T16

8

auto[1]

1141

1

T5

8

T22

11

T16

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

544

1

T5

7

T22

6

T16

4

from_0to1

539

1

T5

6

T22

6

T16

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1181

1

T5

10

T22

12

T16

13

auto[1]

1139

1

T5

10

T22

8

T16

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1154

1

T5

12

T22

13

T16

13

auto[1]

1166

1

T5

8

T22

7

T16

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T5

2

T22

1

T16

2

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T5

1

T22

1

T16

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T22

1

T133

1

T110

1

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T5

2

T63

1

T131

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T5

1

T22

1

T16

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T16

1

T60

1

T40

2

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T5

1

T22

1

T70

1

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T5

1

T22

1

T63

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T5

1

T22

1

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T5

1

T60

1

T63

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T60

1

T61

1

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T22

2

T16

1

T63

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T5

1

T22

2

T16

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T22

1

T60

1

T63

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T5

1

T16

1

T60

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T5

1

T16

1

T131

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1179

1

T5

9

T22

10

T16

11

auto[1]

1141

1

T5

11

T22

10

T16

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

548

1

T5

7

T22

4

T16

4

from_0to1

559

1

T5

7

T22

5

T16

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1176

1

T5

9

T22

9

T16

10

auto[1]

1144

1

T5

11

T22

11

T16

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1159

1

T5

7

T22

13

T16

10

auto[1]

1161

1

T5

13

T22

7

T16

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T5

2

T22

2

T16

1

auto[0]

from_1to0

auto[0]

auto[1]

81

1

T60

2

T61

1

T63

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T60

1

T61

1

T63

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T5

3

T22

1

T60

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T5

2

T22

1

T16

1

auto[0]

from_0to1

auto[0]

auto[1]

81

1

T5

1

T16

1

T60

2

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T61

1

T63

2

T131

1

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T5

1

T22

1

T16

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T60

1

T133

1

T110

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T63

1

T131

1

T110

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T5

1

T22

1

T16

2

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T5

1

T16

1

T60

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T61

1

T70

1

T133

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T5

2

T16

2

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T22

3

T60

1

T133

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T5

1

T60

1

T61

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1132

1

T5

8

T22

6

T16

10

auto[1]

1188

1

T5

12

T22

14

T16

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

534

1

T5

5

T22

3

T16

5

from_0to1

542

1

T5

5

T22

3

T16

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1197

1

T5

7

T22

11

T16

7

auto[1]

1123

1

T5

13

T22

9

T16

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1161

1

T5

9

T22

10

T16

7

auto[1]

1159

1

T5

11

T22

10

T16

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T22

1

T16

1

T133

3

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T16

1

T70

1

T39

3

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T5

1

T60

2

T61

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T60

1

T63

1

T131

1

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T16

1

T61

1

T63

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T22

1

T131

1

T40

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T5

2

T60

2

T63

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T5

2

T16

2

T61

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T5

1

T22

1

T63

2

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T22

1

T60

1

T61

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T16

3

T70

2

T131

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T5

3

T63

1

T133

2

auto[1]

from_0to1

auto[0]

auto[0]

87

1

T5

1

T22

1

T60

3

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T70

1

T133

1

T110

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T133

1

T40

1

T110

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T22

1

T16

2

T70

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T5

9

T22

10

T16

13

auto[1]

1195

1

T5

11

T22

10

T16

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

566

1

T5

6

T22

6

T16

5

from_0to1

561

1

T5

6

T22

6

T16

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1184

1

T5

8

T22

12

T16

14

auto[1]

1136

1

T5

12

T22

8

T16

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139

1

T5

10

T22

8

T16

10

auto[1]

1181

1

T5

10

T22

12

T16

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T5

1

T16

2

T63

2

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T5

2

T22

2

T16

2

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T5

1

T61

1

T133

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T60

2

T61

1

T70

1

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T22

1

T60

1

T61

1

auto[0]

from_0to1

auto[0]

auto[1]

79

1

T61

2

T63

1

T70

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T5

2

T63

1

T131

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T5

1

T22

3

T16

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T22

1

T60

1

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T5

2

T16

1

T131

2

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T22

1

T61

1

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T22

2

T60

1

T61

2

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T5

2

T60

1

T61

1

auto[1]

from_0to1

auto[0]

auto[1]

85

1

T5

1

T22

1

T16

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T16

2

T60

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

78

1

T22

1

T60

1

T61

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1163

1

T5

7

T22

11

T16

12

auto[1]

1157

1

T5

13

T22

9

T16

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

564

1

T5

6

T22

4

T16

3

from_0to1

565

1

T5

6

T22

5

T16

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T5

11

T22

7

T16

10

auto[1]

1165

1

T5

9

T22

13

T16

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1191

1

T5

10

T22

9

T16

8

auto[1]

1129

1

T5

10

T22

11

T16

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T16

1

T63

1

T131

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T16

1

T63

1

T40

2

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T5

1

T22

1

T16

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T22

2

T61

1

T70

1

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T22

1

T60

1

T61

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T22

1

T60

1

T63

1

auto[0]

from_0to1

auto[1]

auto[0]

80

1

T5

3

T22

1

T61

2

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T16

2

T60

1

T63

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T5

1

T60

2

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

77

1

T5

2

T63

1

T70

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T61

2

T63

1

T131

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T5

2

T22

1

T61

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T5

2

T16

1

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T5

1

T22

1

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

78

1

T22

1

T60

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T16

1

T61

1

T133

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1150

1

T5

13

T22

11

T16

9

auto[1]

1170

1

T5

7

T22

9

T16

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

560

1

T5

4

T22

4

T16

4

from_0to1

562

1

T5

4

T22

5

T16

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T5

11

T22

9

T16

11

auto[1]

1167

1

T5

9

T22

11

T16

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1192

1

T5

12

T22

10

T16

11

auto[1]

1128

1

T5

8

T22

10

T16

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

86

1

T16

1

T60

1

T70

2

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T5

1

T63

1

T70

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T5

1

T63

1

T133

1

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T5

1

T22

1

T60

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T22

1

T16

1

T60

2

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T5

1

T22

1

T16

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T5

1

T22

2

T60

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T131

1

T133

1

T39

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T5

1

T16

2

T60

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T16

1

T60

2

T61

2

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T22

2

T63

1

T70

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T22

1

T60

1

T63

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T5

1

T63

2

T70

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T61

1

T70

1

T131

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T5

1

T22

1

T16

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T60

2

T61

2

T63

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1124

1

T5

5

T22

13

T16

10

auto[1]

1196

1

T5

15

T22

7

T16

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

561

1

T5

6

T22

6

T16

4

from_0to1

560

1

T5

5

T22

5

T16

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1179

1

T5

13

T22

11

T16

11

auto[1]

1141

1

T5

7

T22

9

T16

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1124

1

T5

13

T22

8

T16

11

auto[1]

1196

1

T5

7

T22

12

T16

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T22

1

T16

1

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T5

1

T22

1

T16

1

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T22

2

T61

1

T131

1

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T70

1

T131

2

T40

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T22

1

T60

1

T63

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T5

1

T22

1

T16

2

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T60

1

T61

1

T131

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T22

2

T60

1

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T5

3

T22

1

T60

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T60

1

T70

2

T131

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T5

1

T16

1

T60

2

auto[1]

from_1to0

auto[1]

auto[1]

90

1

T5

1

T22

1

T16

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T16

2

T60

1

T61

1

auto[1]

from_0to1

auto[0]

auto[1]

84

1

T5

1

T60

2

T61

2

auto[1]

from_0to1

auto[1]

auto[0]

79

1

T5

3

T16

1

T61

2

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T22

1

T63

2

T70

1