Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
51.52	51.52	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_wkup_event_cg	51.52	1	100	1	64	64

---

Group Instance : sysrst_ctrl_wkup_event_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
51.52	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_wkup_event_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00
Crosses	23	15	8	34.78

Variables for Group Instance sysrst_ctrl_wkup_event_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_h2l_pwrb	2	0	2	100.00	100	1	1	2
cp_h_ac_present	2	0	2	100.00	100	1	1	2
cp_interrupt_gen	2	1	1	50.00	100	1	1	2
cp_l2h_lid_open	2	0	2	100.00	100	1	1	2
cp_wakeup_sts	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_wkup_event_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_wkup_sts	23	15	8	34.78	100	1	1	0

Summary for Variable cp_h2l_pwrb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_h2l_pwrb

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

871

1

T4

2

T5

2

T3

1

auto[1]

757

1

T5

1

T22

1

T16

1

---

Summary for Variable cp_h_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_h_ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1002

1

T4

1

T5

2

T3

3

auto[1]

626

1

T4

1

T5

1

T22

1

---

Summary for Variable cp_interrupt_gen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_interrupt_gen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1628

1

T4

2

T5

3

T22

1

---

Summary for Variable cp_l2h_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_l2h_lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

958

1

T4

1

T5

1

T22

1

auto[1]

670

1

T4

1

T5

2

T60

2

---

Summary for Variable cp_wakeup_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wakeup_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1570

1

T4

2

T5

3

T22

1

auto[1]

58

1

T3

1

T27

1

T28

1

---

Summary for Cross cross_wkup_sts

Samples crossed: cp_wakeup_sts cp_h2l_pwrb cp_l2h_lid_open cp_h_ac_present cp_interrupt_gen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	23	15	8	34.78	15
Automatically Generated Cross Bins	23	15	8	34.78	15
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_wkup_sts

Element holes

cp_wakeup_sts	cp_h2l_pwrb	cp_l2h_lid_open	cp_h_ac_present	cp_interrupt_gen	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	*	*	--	--	4

Uncovered bins

cp_wakeup_sts	cp_h2l_pwrb	cp_l2h_lid_open	cp_h_ac_present	cp_interrupt_gen	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_wakeup_sts

cp_h2l_pwrb

cp_l2h_lid_open

cp_h_ac_present

cp_interrupt_gen

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

368

1

T4

1

T5

1

T3

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

146

1

T29

1

T30

1

T31

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

177

1

T60

1

T63

1

T29

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

180

1

T4

1

T5

1

T61

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

247

1

T3

1

T60

1

T29

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

139

1

T22

1

T16

1

T70

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

152

1

T5

1

T60

1

T29

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

161

1

T63

1

T29

1

T70

1

User Defined Cross Bins for cross_wkup_sts

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded