Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154018	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117195

1

T4

18

T5

56

T6

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142292	1			T4	2		T5	62		T6	8
values[0x0]	64238	1			T4	31		T5	32		T6	8
values[0x1]	64683	1			T4	29		T5	28		T6	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	124744	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

146469

1

T4

23

T5

66

T6

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	900	1			T1	6		T16	5		T61	1
valid_sources[0x01]	1484	1			T5	3		T22	1		T1	5
valid_sources[0x02]	958	1			T5	6		T1	1		T14	10
valid_sources[0x03]	735	1			T22	1		T14	2		T60	2
valid_sources[0x04]	854	1			T5	1		T1	5		T7	4
valid_sources[0x05]	949	1			T22	1		T1	2		T14	12
valid_sources[0x06]	1026	1			T1	4		T14	1		T7	3
valid_sources[0x07]	886	1			T1	11		T14	4		T60	4
valid_sources[0x08]	1195	1			T22	1		T1	8		T14	1
valid_sources[0x09]	1366	1			T1	4		T14	1		T20	1
valid_sources[0x0a]	845	1			T1	2		T14	1		T16	1
valid_sources[0x0b]	803	1			T5	2		T22	1		T1	3
valid_sources[0x0c]	800	1			T5	1		T1	2		T3	16
valid_sources[0x0d]	950	1			T22	1		T1	2		T14	30
valid_sources[0x0e]	897	1			T1	2		T60	3		T12	4
valid_sources[0x0f]	1201	1			T5	1		T22	2		T1	2
valid_sources[0x10]	910	1			T5	4		T1	3		T3	4
valid_sources[0x11]	1734	1			T5	1		T14	10		T16	1
valid_sources[0x12]	1201	1			T22	1		T1	14		T7	5
valid_sources[0x13]	967	1			T22	1		T1	7		T14	2
valid_sources[0x14]	866	1			T63	1		T9	1		T10	9
valid_sources[0x15]	858	1			T22	1		T1	2		T61	3
valid_sources[0x16]	792	1			T1	3		T7	4		T9	8
valid_sources[0x17]	922	1			T1	2		T61	2		T9	7
valid_sources[0x18]	744	1			T22	1		T15	1		T3	1
valid_sources[0x19]	916	1			T5	1		T1	4		T60	1
valid_sources[0x1a]	904	1			T5	7		T22	1		T1	6
valid_sources[0x1b]	864	1			T6	1		T1	16		T3	6
valid_sources[0x1c]	1389	1			T1	2		T14	1		T15	1
valid_sources[0x1d]	871	1			T1	1		T19	2		T60	1
valid_sources[0x1e]	1567	1			T5	1		T1	4		T2	696
valid_sources[0x1f]	993	1			T1	5		T18	16		T3	4
valid_sources[0x20]	739	1			T22	1		T1	1		T14	8
valid_sources[0x21]	912	1			T1	1		T14	1		T3	1
valid_sources[0x22]	926	1			T5	1		T1	11		T9	9
valid_sources[0x23]	697	1			T5	3		T1	3		T14	3
valid_sources[0x24]	897	1			T22	2		T1	1		T14	2
valid_sources[0x25]	923	1			T1	8		T14	2		T9	2
valid_sources[0x26]	934	1			T1	2		T63	1		T12	5
valid_sources[0x27]	853	1			T1	4		T14	2		T16	5
valid_sources[0x28]	1693	1			T1	1		T7	1		T9	4
valid_sources[0x29]	824	1			T1	1		T14	8		T3	1
valid_sources[0x2a]	851	1			T5	5		T22	2		T1	2
valid_sources[0x2b]	888	1			T5	11		T1	9		T14	4
valid_sources[0x2c]	2263	1			T5	2		T1	6		T14	15
valid_sources[0x2d]	925	1			T1	12		T14	9		T16	1
valid_sources[0x2e]	758	1			T5	2		T1	5		T3	1
valid_sources[0x2f]	921	1			T1	5		T9	4		T12	2
valid_sources[0x30]	859	1			T22	1		T1	4		T14	7
valid_sources[0x31]	1098	1			T5	2		T22	1		T1	5
valid_sources[0x32]	1410	1			T1	6		T14	1		T16	1
valid_sources[0x33]	840	1			T22	1		T1	2		T14	3
valid_sources[0x34]	1055	1			T22	2		T1	2		T3	5
valid_sources[0x35]	803	1			T5	2		T1	3		T61	1
valid_sources[0x36]	905	1			T21	2		T22	1		T1	1
valid_sources[0x37]	890	1			T1	1		T14	31		T3	7
valid_sources[0x38]	1299	1			T22	1		T1	5		T16	2
valid_sources[0x39]	1308	1			T22	1		T1	1		T16	2
valid_sources[0x3a]	731	1			T22	2		T1	3		T63	1
valid_sources[0x3b]	1744	1			T5	2		T1	3		T14	7
valid_sources[0x3c]	991	1			T1	2		T20	1		T9	2
valid_sources[0x3d]	1055	1			T22	1		T1	6		T3	1
valid_sources[0x3e]	1020	1			T1	5		T14	2		T16	3
valid_sources[0x3f]	988	1			T1	4		T14	19		T63	1
valid_sources[0x40]	1578	1			T14	4		T7	8		T63	1
valid_sources[0x41]	989	1			T22	1		T1	4		T3	14
valid_sources[0x42]	910	1			T7	1		T12	3		T13	3
valid_sources[0x43]	1069	1			T1	4		T15	1		T9	3
valid_sources[0x44]	688	1			T22	1		T1	1		T16	2
valid_sources[0x45]	816	1			T6	4		T16	2		T3	6
valid_sources[0x46]	1107	1			T1	4		T14	13		T16	1
valid_sources[0x47]	771	1			T1	1		T60	1		T9	4
valid_sources[0x48]	872	1			T1	3		T61	1		T63	1
valid_sources[0x49]	1641	1			T1	6		T14	5		T7	6
valid_sources[0x4a]	1169	1			T22	1		T1	2		T14	1
valid_sources[0x4b]	735	1			T5	1		T1	1		T16	2
valid_sources[0x4c]	897	1			T1	9		T14	10		T3	4
valid_sources[0x4d]	1514	1			T6	1		T21	1		T22	1
valid_sources[0x4e]	918	1			T22	1		T3	3		T9	3
valid_sources[0x4f]	899	1			T1	2		T7	2		T60	2
valid_sources[0x50]	822	1			T22	1		T1	5		T14	9
valid_sources[0x51]	830	1			T1	1		T14	1		T3	3
valid_sources[0x52]	998	1			T9	2		T10	6		T11	2
valid_sources[0x53]	1180	1			T6	1		T16	2		T3	2
valid_sources[0x54]	1593	1			T14	2		T9	1		T12	7
valid_sources[0x55]	798	1			T1	8		T20	1		T7	4
valid_sources[0x56]	916	1			T5	1		T22	2		T1	13
valid_sources[0x57]	1645	1			T1	7		T14	11		T20	1
valid_sources[0x58]	949	1			T1	3		T7	2		T63	1
valid_sources[0x59]	842	1			T5	1		T22	1		T1	1
valid_sources[0x5a]	1559	1			T5	1		T6	1		T21	3
valid_sources[0x5b]	853	1			T22	2		T1	2		T3	3
valid_sources[0x5c]	776	1			T1	6		T63	2		T9	4
valid_sources[0x5d]	880	1			T1	3		T14	5		T3	3
valid_sources[0x5e]	907	1			T1	4		T14	2		T7	20
valid_sources[0x5f]	855	1			T16	1		T3	12		T9	3
valid_sources[0x60]	2842	1			T1	3		T3	16		T63	1
valid_sources[0x61]	944	1			T22	1		T1	2		T3	3
valid_sources[0x62]	1372	1			T5	1		T1	5		T3	6
valid_sources[0x63]	855	1			T5	2		T1	2		T16	2
valid_sources[0x64]	826	1			T5	3		T1	18		T14	13
valid_sources[0x65]	737	1			T5	4		T16	4		T45	1
valid_sources[0x66]	901	1			T22	1		T1	5		T16	3
valid_sources[0x67]	1188	1			T22	2		T9	9		T10	2
valid_sources[0x68]	880	1			T1	10		T16	1		T7	4
valid_sources[0x69]	1042	1			T21	1		T22	2		T1	5
valid_sources[0x6a]	817	1			T22	2		T1	5		T14	5
valid_sources[0x6b]	886	1			T6	1		T22	1		T1	8
valid_sources[0x6c]	934	1			T14	5		T3	9		T7	7
valid_sources[0x6d]	765	1			T1	11		T7	3		T60	2
valid_sources[0x6e]	1151	1			T1	1		T3	1		T60	1
valid_sources[0x6f]	893	1			T5	3		T1	4		T14	2
valid_sources[0x70]	1019	1			T1	3		T14	3		T3	3
valid_sources[0x71]	1388	1			T4	62		T14	2		T3	1
valid_sources[0x72]	970	1			T60	2		T9	3		T10	2
valid_sources[0x73]	1070	1			T3	3		T61	1		T9	3
valid_sources[0x74]	758	1			T6	1		T1	2		T3	10
valid_sources[0x75]	981	1			T5	1		T1	2		T15	1
valid_sources[0x76]	933	1			T22	3		T1	4		T7	4
valid_sources[0x77]	892	1			T22	1		T14	8		T9	3
valid_sources[0x78]	983	1			T22	1		T1	2		T14	11
valid_sources[0x79]	875	1			T22	3		T14	4		T16	2
valid_sources[0x7a]	970	1			T1	9		T14	2		T3	1
valid_sources[0x7b]	1073	1			T1	6		T9	2		T12	6
valid_sources[0x7c]	729	1			T22	1		T1	2		T14	1
valid_sources[0x7d]	877	1			T14	14		T7	6		T12	6
valid_sources[0x7e]	1294	1			T22	2		T9	3		T10	2
valid_sources[0x7f]	837	1			T1	9		T14	3		T63	1
valid_sources[0x80]	1542	1			T22	1		T1	2		T14	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64144

1

T5

33

T6

2

T21

1

values[0x0]

all_enables

biggest_size

31168

1

T4

13

T5

14

T6

5

values[0x1]

all_enables

biggest_size

21883

1

T4

5

T5

9

T21

2