Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T22

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T22
1	1	Covered	T4,T5,T22

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T42,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T32,T42,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T42,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T42,T38
1	0	Covered	T4,T5,T22
1	1	Covered	T32,T42,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T42,T38
0	1	Covered	T39,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32,T42,T38
0	1	Covered	T32,T39,T43
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T32,T42,T38
1	-	Covered	T32,T39,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T42,T38
DetectSt	168	Covered	T32,T42,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T32,T42,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T32,T42,T38
DebounceSt->IdleSt	163	Covered	T41,T36,T208
DetectSt->IdleSt	186	Covered	T39,T88
DetectSt->StableSt	191	Covered	T32,T42,T38
IdleSt->DebounceSt	148	Covered	T32,T42,T38
StableSt->IdleSt	206	Covered	T32,T39,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T42,T38
0	1	Covered	T32,T42,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T32,T42,T38
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T42,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T42,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T36,T208
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T42,T38
DetectSt	-	-	-	-	1	-	-	Covered	T39,T88
DetectSt	-	-	-	-	0	1	-	Covered	T32,T42,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T39,T43
StableSt	-	-	-	-	-	-	0	Covered	T32,T42,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	133	0	0
CntIncr_A	8751421	271777	0	0
CntNoWrap_A	8751421	8084746	0	0
DetectStDropOut_A	8751421	2	0	0
DetectedOut_A	8751421	275706	0	0
DetectedPulseOut_A	8751421	60	0	0
DisabledIdleSt_A	8751421	7357601	0	0
DisabledNoDetection_A	8751421	7359991	0	0
EnterDebounceSt_A	8751421	72	0	0
EnterDetectSt_A	8751421	62	0	0
EnterStableSt_A	8751421	60	0	0
PulseIsPulse_A	8751421	60	0	0
StayInStableSt	8751421	275620	0	0
gen_high_level_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	133	0	0
T32	723	2	0	0
T34	32992	0	0	0
T36	0	8	0	0
T38	0	2	0	0
T39	0	6	0	0
T40	3069	0	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T174	0	2	0	0
T208	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	271777	0	0
T32	723	62	0	0
T34	32992	0	0	0
T36	0	54	0	0
T38	0	16	0	0
T39	0	221	0	0
T40	3069	0	0	0
T41	0	38	0	0
T42	0	61	0	0
T43	0	73	0	0
T44	0	36	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T75	0	25	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T208	0	43445	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8084746	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	2	0	0
T39	28838	1	0	0
T58	566	0	0	0
T81	29616	0	0	0
T88	0	1	0	0
T124	13404	0	0	0
T212	525	0	0	0
T213	506	0	0	0
T214	4403	0	0	0
T215	670	0	0	0
T216	503	0	0	0
T217	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	275706	0	0
T32	723	71	0	0
T34	32992	0	0	0
T36	0	100	0	0
T38	0	133	0	0
T39	0	133	0	0
T40	3069	0	0	0
T41	0	14	0	0
T42	0	100	0	0
T43	0	47	0	0
T44	0	168	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T174	0	115	0	0
T187	0	14	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	60	0	0
T32	723	1	0	0
T34	32992	0	0	0
T36	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	3069	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T174	0	1	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7357601	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7359991	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	72	0	0
T32	723	1	0	0
T34	32992	0	0	0
T36	0	5	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	3069	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T75	0	1	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T208	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	62	0	0
T32	723	1	0	0
T34	32992	0	0	0
T36	0	3	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	3069	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T174	0	1	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	60	0	0
T32	723	1	0	0
T34	32992	0	0	0
T36	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	3069	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T174	0	1	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	60	0	0
T32	723	1	0	0
T34	32992	0	0	0
T36	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	3069	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T174	0	1	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	275620	0	0
T32	723	70	0	0
T34	32992	0	0	0
T36	0	96	0	0
T38	0	131	0	0
T39	0	130	0	0
T40	3069	0	0	0
T41	0	13	0	0
T42	0	98	0	0
T43	0	46	0	0
T44	0	166	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T174	0	113	0	0
T187	0	13	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	34	0	0
T32	723	1	0	0
T34	32992	0	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	3069	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T168	0	1	0	0
T169	0	1	0	0
T186	0	2	0	0
T187	0	1	0	0
T218	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T22
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T32,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T32,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T32,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T32
1	0	Covered	T4,T5,T22
1	1	Covered	T8,T32,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T32,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T32,T40
0	1	Covered	T40,T72,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T32,T40
1	-	Covered	T40,T72,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T32,T40
DetectSt	168	Covered	T8,T32,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T32,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T32,T40
DebounceSt->IdleSt	163	Covered	T39,T36,T82
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T32,T40
IdleSt->DebounceSt	148	Covered	T8,T32,T40
StableSt->IdleSt	206	Covered	T8,T40,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T32,T40
0	1	Covered	T8,T32,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T32,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T32,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T32,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T36,T209
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T32,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T32,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T72,T36
StableSt	-	-	-	-	-	-	0	Covered	T8,T32,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	101	0	0
CntIncr_A	8751421	71577	0	0
CntNoWrap_A	8751421	8084778	0	0
DetectStDropOut_A	8751421	0	0	0
DetectedOut_A	8751421	26533	0	0
DetectedPulseOut_A	8751421	48	0	0
DisabledIdleSt_A	8751421	7828557	0	0
DisabledNoDetection_A	8751421	7830940	0	0
EnterDebounceSt_A	8751421	53	0	0
EnterDetectSt_A	8751421	48	0	0
EnterStableSt_A	8751421	48	0	0
PulseIsPulse_A	8751421	48	0	0
StayInStableSt	8751421	26460	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8751421	6355	0	0
gen_low_level_sva.LowLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	101	0	0
T8	2896	2	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	2	0	0
T36	0	7	0	0
T37	0	4	0	0
T39	0	5	0	0
T40	0	2	0	0
T43	0	2	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	4	0	0
T175	0	2	0	0
T208	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	71577	0	0
T8	2896	73	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	62	0	0
T36	0	42	0	0
T37	0	68	0	0
T39	0	602	0	0
T40	0	82	0	0
T43	0	73	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	188	0	0
T175	0	86	0	0
T208	0	43445	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8084778	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	26533	0	0
T8	2896	226	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	117	0	0
T36	0	133	0	0
T37	0	85	0	0
T39	0	82	0	0
T40	0	62	0	0
T43	0	38	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	178	0	0
T175	0	39	0	0
T208	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	48	0	0
T8	2896	1	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T43	0	1	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	2	0	0
T175	0	1	0	0
T208	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7828557	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7830940	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	53	0	0
T8	2896	1	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	1	0	0
T36	0	4	0	0
T37	0	2	0	0
T39	0	3	0	0
T40	0	1	0	0
T43	0	1	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	2	0	0
T175	0	1	0	0
T208	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	48	0	0
T8	2896	1	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T43	0	1	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	2	0	0
T175	0	1	0	0
T208	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	48	0	0
T8	2896	1	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T43	0	1	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	2	0	0
T175	0	1	0	0
T208	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	48	0	0
T8	2896	1	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T43	0	1	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	2	0	0
T175	0	1	0	0
T208	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	26460	0	0
T8	2896	224	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	115	0	0
T36	0	129	0	0
T37	0	83	0	0
T39	0	78	0	0
T40	0	61	0	0
T43	0	36	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	176	0	0
T175	0	37	0	0
T208	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	6355	0	0
T1	18209	28	0	0
T2	6931	23	0	0
T3	0	10	0	0
T4	524	4	0	0
T5	503	5	0	0
T6	695	0	0	0
T14	19415	37	0	0
T15	968	0	0	0
T16	523	4	0	0
T17	0	28	0	0
T20	0	6	0	0
T21	422	0	0	0
T22	506	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	23	0	0
T34	32992	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	3069	1	0	0
T42	570	0	0	0
T48	5266	0	0	0
T57	912	0	0	0
T65	490	0	0	0
T66	503	0	0	0
T72	0	2	0	0
T73	6308	0	0	0
T80	3888	0	0	0
T89	0	2	0	0
T96	1573	0	0	0
T126	0	1	0	0
T166	0	1	0	0
T170	0	1	0	0
T197	0	1	0	0
T218	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T22

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T22
1	1	Covered	T4,T5,T22

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T32,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T32,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T40,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T32,T40
1	0	Covered	T4,T5,T22
1	1	Covered	T8,T32,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T40,T42
0	1	Covered	T229
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T40,T42
0	1	Covered	T8,T39,T72
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T40,T42
1	-	Covered	T8,T39,T72

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T32,T40
DetectSt	168	Covered	T8,T40,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T40,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T40,T42
DebounceSt->IdleSt	163	Covered	T32,T51,T218
DetectSt->IdleSt	186	Covered	T229
DetectSt->StableSt	191	Covered	T8,T40,T42
IdleSt->DebounceSt	148	Covered	T8,T32,T40
StableSt->IdleSt	206	Covered	T8,T40,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T32,T40
0	1	Covered	T8,T32,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T40,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T32,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T40,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T218,T230
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T32,T40
DetectSt	-	-	-	-	1	-	-	Covered	T229
DetectSt	-	-	-	-	0	1	-	Covered	T8,T40,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T39,T72
StableSt	-	-	-	-	-	-	0	Covered	T8,T40,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	139	0	0
CntIncr_A	8751421	209116	0	0
CntNoWrap_A	8751421	8084740	0	0
DetectStDropOut_A	8751421	1	0	0
DetectedOut_A	8751421	224210	0	0
DetectedPulseOut_A	8751421	66	0	0
DisabledIdleSt_A	8751421	7285696	0	0
DisabledNoDetection_A	8751421	7288081	0	0
EnterDebounceSt_A	8751421	73	0	0
EnterDetectSt_A	8751421	67	0	0
EnterStableSt_A	8751421	66	0	0
PulseIsPulse_A	8751421	66	0	0
StayInStableSt	8751421	224116	0	0
gen_high_level_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	139	0	0
T8	2896	4	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	1	0	0
T36	0	4	0	0
T39	0	4	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	2	0	0
T46	669	0	0	0
T51	0	2	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	4	0	0
T231	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	209116	0	0
T8	2896	146	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	62	0	0
T36	0	22	0	0
T39	0	477	0	0
T40	0	82	0	0
T42	0	61	0	0
T44	0	36	0	0
T46	669	0	0	0
T51	0	28	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	188	0	0
T231	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8084740	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	1	0	0
T164	764	0	0	0
T229	581	1	0	0
T232	408	0	0	0
T233	402	0	0	0
T234	14508	0	0	0
T235	789	0	0	0
T236	768	0	0	0
T237	23680	0	0	0
T238	23732	0	0	0
T239	655	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	224210	0	0
T8	2896	78	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T36	0	124	0	0
T39	0	67	0	0
T40	0	640	0	0
T42	0	99	0	0
T44	0	128	0	0
T46	669	0	0	0
T51	0	70	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	311	0	0
T208	0	41	0	0
T231	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	66	0	0
T8	2896	2	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	669	0	0	0
T51	0	1	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	2	0	0
T208	0	1	0	0
T231	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7285696	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7288081	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	73	0	0
T8	2896	2	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	669	0	0	0
T51	0	2	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	2	0	0
T231	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	67	0	0
T8	2896	2	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	669	0	0	0
T51	0	1	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	2	0	0
T208	0	1	0	0
T231	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	66	0	0
T8	2896	2	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	669	0	0	0
T51	0	1	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	2	0	0
T208	0	1	0	0
T231	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	66	0	0
T8	2896	2	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	669	0	0	0
T51	0	1	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	2	0	0
T208	0	1	0	0
T231	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	224116	0	0
T8	2896	75	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T36	0	121	0	0
T39	0	64	0	0
T40	0	638	0	0
T42	0	97	0	0
T44	0	127	0	0
T46	669	0	0	0
T51	0	68	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	308	0	0
T208	0	39	0	0
T231	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	38	0	0
T8	2896	1	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T44	0	1	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	1	0	0
T102	0	2	0	0
T167	0	1	0	0
T169	0	1	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T22
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T11,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T40,T42
1	0	Covered	T4,T5,T22
1	1	Covered	T11,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T38,T39
0	1	Covered	T240
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T38,T39
0	1	Covered	T126,T218,T88
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T38,T39
1	-	Covered	T126,T218,T88

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T38,T39
DetectSt	168	Covered	T11,T38,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T38,T39
DebounceSt->IdleSt	163	Covered	T175,T82,T83
DetectSt->IdleSt	186	Covered	T240
DetectSt->StableSt	191	Covered	T11,T38,T39
IdleSt->DebounceSt	148	Covered	T11,T38,T39
StableSt->IdleSt	206	Covered	T39,T126,T218

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T38,T39
0	1	Covered	T11,T38,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T38,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T175
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T38,T39
DetectSt	-	-	-	-	1	-	-	Covered	T240
DetectSt	-	-	-	-	0	1	-	Covered	T11,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T126,T218,T88
StableSt	-	-	-	-	-	-	0	Covered	T11,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	65	0	0
CntIncr_A	8751421	29261	0	0
CntNoWrap_A	8751421	8084814	0	0
DetectStDropOut_A	8751421	1	0	0
DetectedOut_A	8751421	3297	0	0
DetectedPulseOut_A	8751421	30	0	0
DisabledIdleSt_A	8751421	7728238	0	0
DisabledNoDetection_A	8751421	7730631	0	0
EnterDebounceSt_A	8751421	35	0	0
EnterDetectSt_A	8751421	31	0	0
EnterStableSt_A	8751421	30	0	0
PulseIsPulse_A	8751421	30	0	0
StayInStableSt	8751421	3249	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8751421	6291	0	0
gen_low_level_sva.LowLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	65	0	0
T11	621	2	0	0
T12	12771	0	0	0
T13	28419	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T46	669	0	0	0
T47	649	0	0	0
T70	502	0	0	0
T71	526	0	0	0
T88	0	2	0	0
T126	0	2	0	0
T167	0	2	0	0
T169	0	2	0	0
T170	0	2	0	0
T175	0	1	0	0
T218	0	4	0	0
T220	130472	0	0	0
T221	402	0	0	0
T222	408	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	29261	0	0
T11	621	80	0	0
T12	12771	0	0	0
T13	28419	0	0	0
T38	0	16	0	0
T39	0	446	0	0
T46	669	0	0	0
T47	649	0	0	0
T70	502	0	0	0
T71	526	0	0	0
T88	0	59	0	0
T126	0	14	0	0
T167	0	89	0	0
T169	0	47	0	0
T170	0	24965	0	0
T175	0	86	0	0
T218	0	64	0	0
T220	130472	0	0	0
T221	402	0	0	0
T222	408	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8084814	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	1	0	0
T240	794	1	0	0
T241	548	0	0	0
T242	425	0	0	0
T243	10634	0	0	0
T244	6812	0	0	0
T245	2967	0	0	0
T246	18732	0	0	0
T247	15316	0	0	0
T248	17290	0	0	0
T249	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	3297	0	0
T11	621	38	0	0
T12	12771	0	0	0
T13	28419	0	0	0
T38	0	73	0	0
T39	0	1321	0	0
T46	669	0	0	0
T47	649	0	0	0
T70	502	0	0	0
T71	526	0	0	0
T88	0	108	0	0
T126	0	8	0	0
T167	0	129	0	0
T169	0	110	0	0
T170	0	44	0	0
T196	0	43	0	0
T218	0	89	0	0
T220	130472	0	0	0
T221	402	0	0	0
T222	408	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	30	0	0
T11	621	1	0	0
T12	12771	0	0	0
T13	28419	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T46	669	0	0	0
T47	649	0	0	0
T70	502	0	0	0
T71	526	0	0	0
T88	0	1	0	0
T126	0	1	0	0
T167	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T196	0	1	0	0
T218	0	2	0	0
T220	130472	0	0	0
T221	402	0	0	0
T222	408	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7728238	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7730631	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	35	0	0
T11	621	1	0	0
T12	12771	0	0	0
T13	28419	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T46	669	0	0	0
T47	649	0	0	0
T70	502	0	0	0
T71	526	0	0	0
T88	0	1	0	0
T126	0	1	0	0
T167	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T175	0	1	0	0
T218	0	2	0	0
T220	130472	0	0	0
T221	402	0	0	0
T222	408	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	31	0	0
T11	621	1	0	0
T12	12771	0	0	0
T13	28419	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T46	669	0	0	0
T47	649	0	0	0
T70	502	0	0	0
T71	526	0	0	0
T88	0	1	0	0
T126	0	1	0	0
T167	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T196	0	1	0	0
T218	0	2	0	0
T220	130472	0	0	0
T221	402	0	0	0
T222	408	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	30	0	0
T11	621	1	0	0
T12	12771	0	0	0
T13	28419	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T46	669	0	0	0
T47	649	0	0	0
T70	502	0	0	0
T71	526	0	0	0
T88	0	1	0	0
T126	0	1	0	0
T167	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T196	0	1	0	0
T218	0	2	0	0
T220	130472	0	0	0
T221	402	0	0	0
T222	408	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	30	0	0
T11	621	1	0	0
T12	12771	0	0	0
T13	28419	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T46	669	0	0	0
T47	649	0	0	0
T70	502	0	0	0
T71	526	0	0	0
T88	0	1	0	0
T126	0	1	0	0
T167	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T196	0	1	0	0
T218	0	2	0	0
T220	130472	0	0	0
T221	402	0	0	0
T222	408	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	3249	0	0
T11	621	36	0	0
T12	12771	0	0	0
T13	28419	0	0	0
T38	0	71	0	0
T39	0	1319	0	0
T46	669	0	0	0
T47	649	0	0	0
T70	502	0	0	0
T71	526	0	0	0
T88	0	107	0	0
T126	0	7	0	0
T167	0	127	0	0
T169	0	108	0	0
T170	0	43	0	0
T196	0	42	0	0
T218	0	86	0	0
T220	130472	0	0	0
T221	402	0	0	0
T222	408	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	6291	0	0
T1	18209	30	0	0
T2	6931	21	0	0
T3	0	12	0	0
T4	524	6	0	0
T5	503	6	0	0
T6	695	0	0	0
T14	19415	21	0	0
T15	968	0	0	0
T16	523	5	0	0
T17	0	21	0	0
T20	0	4	0	0
T21	422	0	0	0
T22	506	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	12	0	0
T88	0	1	0	0
T126	22482	1	0	0
T127	1541	0	0	0
T166	0	1	0	0
T170	0	1	0	0
T186	708	0	0	0
T196	0	1	0	0
T201	598	0	0	0
T202	405	0	0	0
T203	18537	0	0	0
T204	491	0	0	0
T205	422	0	0	0
T206	23050	0	0	0
T207	436	0	0	0
T218	0	1	0	0
T250	0	1	0	0
T251	0	1	0	0
T252	0	1	0	0
T253	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T32,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T32,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T32,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T32,T40
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T32,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T32,T40
0	1	Covered	T89,T199
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T32,T40
0	1	Covered	T8,T40,T72
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T32,T40
1	-	Covered	T8,T40,T72

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T32,T40
DetectSt	168	Covered	T8,T32,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T32,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T32,T40
DebounceSt->IdleSt	163	Covered	T38,T35,T82
DetectSt->IdleSt	186	Covered	T89,T199
DetectSt->StableSt	191	Covered	T8,T32,T40
IdleSt->DebounceSt	148	Covered	T8,T32,T40
StableSt->IdleSt	206	Covered	T8,T40,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T32,T40
0	1	Covered	T8,T32,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T32,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T32,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T32,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T35,T199
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T32,T40
DetectSt	-	-	-	-	1	-	-	Covered	T89,T199
DetectSt	-	-	-	-	0	1	-	Covered	T8,T32,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T40,T72
StableSt	-	-	-	-	-	-	0	Covered	T8,T32,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	134	0	0
CntIncr_A	8751421	180719	0	0
CntNoWrap_A	8751421	8084745	0	0
DetectStDropOut_A	8751421	2	0	0
DetectedOut_A	8751421	29040	0	0
DetectedPulseOut_A	8751421	61	0	0
DisabledIdleSt_A	8751421	7347144	0	0
DisabledNoDetection_A	8751421	7349529	0	0
EnterDebounceSt_A	8751421	73	0	0
EnterDetectSt_A	8751421	63	0	0
EnterStableSt_A	8751421	61	0	0
PulseIsPulse_A	8751421	61	0	0
StayInStableSt	8751421	28954	0	0
gen_high_level_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	134	0	0
T8	2896	2	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T37	0	4	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	4	0	0
T41	0	4	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	2	0	0
T167	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	180719	0	0
T8	2896	73	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	62	0	0
T35	0	32	0	0
T37	0	68	0	0
T38	0	16	0	0
T39	0	31	0	0
T40	0	164	0	0
T41	0	79	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	94	0	0
T167	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8084745	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	2	0	0
T89	24295	1	0	0
T152	29775	0	0	0
T153	4118	0	0	0
T154	1110	0	0	0
T155	8402	0	0	0
T156	981	0	0	0
T157	2340	0	0	0
T158	2442	0	0	0
T159	1565	0	0	0
T160	420	0	0	0
T199	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	29040	0	0
T8	2896	209	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	117	0	0
T37	0	176	0	0
T39	0	66	0	0
T40	0	431	0	0
T41	0	141	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	211	0	0
T102	0	227	0	0
T167	0	130	0	0
T175	0	192	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	61	0	0
T8	2896	1	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	1	0	0
T102	0	4	0	0
T167	0	1	0	0
T175	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7347144	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7349529	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	73	0	0
T8	2896	1	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	1	0	0
T167	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	63	0	0
T8	2896	1	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	1	0	0
T102	0	4	0	0
T167	0	1	0	0
T175	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	61	0	0
T8	2896	1	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	1	0	0
T102	0	4	0	0
T167	0	1	0	0
T175	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	61	0	0
T8	2896	1	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	1	0	0
T102	0	4	0	0
T167	0	1	0	0
T175	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	28954	0	0
T8	2896	208	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T32	0	115	0	0
T37	0	173	0	0
T39	0	64	0	0
T40	0	428	0	0
T41	0	138	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	210	0	0
T102	0	223	0	0
T167	0	128	0	0
T175	0	191	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	36	0	0
T8	2896	1	0	0
T9	8690	0	0	0
T10	17129	0	0	0
T11	621	0	0	0
T12	12771	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T46	669	0	0	0
T52	407	0	0	0
T53	1077	0	0	0
T54	402	0	0	0
T70	502	0	0	0
T72	0	1	0	0
T85	0	1	0	0
T91	0	1	0	0
T102	0	4	0	0
T175	0	1	0	0
T218	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T35,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T32,T42
1	0	Covered	T4,T5,T6
1	1	Covered	T35,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Covered	T36,T37,T102
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T36,T37
1	-	Covered	T36,T37,T102

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T36,T37
DetectSt	168	Covered	T35,T36,T37
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T36,T37
DebounceSt->IdleSt	163	Covered	T82,T228,T83
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T35,T36,T37
IdleSt->DebounceSt	148	Covered	T35,T36,T37
StableSt->IdleSt	206	Covered	T36,T37,T102

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T35,T36,T37
0	1	Covered	T35,T36,T37
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T37
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T36,T37
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T37,T102
StableSt	-	-	-	-	-	-	0	Covered	T35,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	64	0	0
CntIncr_A	8751421	129252	0	0
CntNoWrap_A	8751421	8084815	0	0
DetectStDropOut_A	8751421	0	0	0
DetectedOut_A	8751421	2779	0	0
DetectedPulseOut_A	8751421	31	0	0
DisabledIdleSt_A	8751421	7372307	0	0
DisabledNoDetection_A	8751421	7374701	0	0
EnterDebounceSt_A	8751421	34	0	0
EnterDetectSt_A	8751421	31	0	0
EnterStableSt_A	8751421	31	0	0
PulseIsPulse_A	8751421	31	0	0
StayInStableSt	8751421	2731	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8751421	6972	0	0
gen_low_level_sva.LowLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	64	0	0
T35	502	2	0	0
T36	41110	4	0	0
T37	0	2	0	0
T44	1565	0	0	0
T84	682	0	0	0
T85	0	2	0	0
T91	0	2	0	0
T102	0	4	0	0
T113	26996	0	0	0
T114	6259	0	0	0
T115	509	0	0	0
T116	11074	0	0	0
T117	409	0	0	0
T175	0	2	0	0
T196	0	4	0	0
T218	0	2	0	0
T226	404	0	0	0
T227	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	129252	0	0
T35	502	32	0	0
T36	41110	24	0	0
T37	0	34	0	0
T44	1565	0	0	0
T84	682	0	0	0
T85	0	12	0	0
T91	0	21	0	0
T102	0	48	0	0
T113	26996	0	0	0
T114	6259	0	0	0
T115	509	0	0	0
T116	11074	0	0	0
T117	409	0	0	0
T175	0	86	0	0
T196	0	130	0	0
T218	0	32	0	0
T226	404	0	0	0
T227	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8084815	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	2779	0	0
T35	502	41	0	0
T36	41110	97	0	0
T37	0	62	0	0
T44	1565	0	0	0
T84	682	0	0	0
T85	0	1	0	0
T91	0	39	0	0
T102	0	233	0	0
T113	26996	0	0	0
T114	6259	0	0	0
T115	509	0	0	0
T116	11074	0	0	0
T117	409	0	0	0
T175	0	120	0	0
T196	0	149	0	0
T218	0	51	0	0
T226	404	0	0	0
T227	0	54	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	31	0	0
T35	502	1	0	0
T36	41110	2	0	0
T37	0	1	0	0
T44	1565	0	0	0
T84	682	0	0	0
T85	0	1	0	0
T91	0	1	0	0
T102	0	2	0	0
T113	26996	0	0	0
T114	6259	0	0	0
T115	509	0	0	0
T116	11074	0	0	0
T117	409	0	0	0
T175	0	1	0	0
T196	0	2	0	0
T218	0	1	0	0
T226	404	0	0	0
T227	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7372307	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7374701	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	34	0	0
T35	502	1	0	0
T36	41110	2	0	0
T37	0	1	0	0
T44	1565	0	0	0
T84	682	0	0	0
T85	0	1	0	0
T91	0	1	0	0
T102	0	2	0	0
T113	26996	0	0	0
T114	6259	0	0	0
T115	509	0	0	0
T116	11074	0	0	0
T117	409	0	0	0
T175	0	1	0	0
T196	0	2	0	0
T218	0	1	0	0
T226	404	0	0	0
T227	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	31	0	0
T35	502	1	0	0
T36	41110	2	0	0
T37	0	1	0	0
T44	1565	0	0	0
T84	682	0	0	0
T85	0	1	0	0
T91	0	1	0	0
T102	0	2	0	0
T113	26996	0	0	0
T114	6259	0	0	0
T115	509	0	0	0
T116	11074	0	0	0
T117	409	0	0	0
T175	0	1	0	0
T196	0	2	0	0
T218	0	1	0	0
T226	404	0	0	0
T227	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	31	0	0
T35	502	1	0	0
T36	41110	2	0	0
T37	0	1	0	0
T44	1565	0	0	0
T84	682	0	0	0
T85	0	1	0	0
T91	0	1	0	0
T102	0	2	0	0
T113	26996	0	0	0
T114	6259	0	0	0
T115	509	0	0	0
T116	11074	0	0	0
T117	409	0	0	0
T175	0	1	0	0
T196	0	2	0	0
T218	0	1	0	0
T226	404	0	0	0
T227	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	31	0	0
T35	502	1	0	0
T36	41110	2	0	0
T37	0	1	0	0
T44	1565	0	0	0
T84	682	0	0	0
T85	0	1	0	0
T91	0	1	0	0
T102	0	2	0	0
T113	26996	0	0	0
T114	6259	0	0	0
T115	509	0	0	0
T116	11074	0	0	0
T117	409	0	0	0
T175	0	1	0	0
T196	0	2	0	0
T218	0	1	0	0
T226	404	0	0	0
T227	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	2731	0	0
T35	502	39	0	0
T36	41110	94	0	0
T37	0	61	0	0
T44	1565	0	0	0
T84	682	0	0	0
T91	0	37	0	0
T102	0	230	0	0
T113	26996	0	0	0
T114	6259	0	0	0
T115	509	0	0	0
T116	11074	0	0	0
T117	409	0	0	0
T165	0	145	0	0
T175	0	118	0	0
T196	0	147	0	0
T218	0	50	0	0
T226	404	0	0	0
T227	0	52	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	6972	0	0
T1	18209	29	0	0
T2	6931	27	0	0
T4	524	6	0	0
T5	503	6	0	0
T6	695	3	0	0
T14	19415	32	0	0
T15	968	0	0	0
T16	523	4	0	0
T17	0	26	0	0
T18	0	3	0	0
T21	422	0	0	0
T22	506	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	14	0	0
T36	41110	1	0	0
T37	0	1	0	0
T44	1565	0	0	0
T84	682	0	0	0
T85	0	1	0	0
T102	0	1	0	0
T113	26996	0	0	0
T114	6259	0	0	0
T115	509	0	0	0
T116	11074	0	0	0
T117	409	0	0	0
T118	505	0	0	0
T119	498	0	0	0
T196	0	2	0	0
T199	0	1	0	0
T200	0	1	0	0
T218	0	1	0	0
T224	0	1	0	0
T254	0	1	0	0