Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T2
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T2
0	1	Covered	T2,T17,T48
1	0	Covered	T2,T12,T97

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T9
0	1	Covered	T1,T14,T9
1	0	Covered	T86,T82,T255

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T14,T9
1	-	Covered	T1,T14,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T2
DetectSt	168	Covered	T1,T14,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T14,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T2
DebounceSt->IdleSt	163	Covered	T94,T82,T83
DetectSt->IdleSt	186	Covered	T2,T17,T12
DetectSt->StableSt	191	Covered	T1,T14,T9
IdleSt->DebounceSt	148	Covered	T1,T14,T2
StableSt->IdleSt	206	Covered	T1,T14,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T14,T2
0	1	Covered	T1,T14,T2
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T2
IdleSt	0	-	-	-	-	-	-	Covered	T1,T14,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T82,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T2
DetectSt	-	-	-	-	1	-	-	Covered	T2,T17,T12
DetectSt	-	-	-	-	0	1	-	Covered	T1,T14,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T14,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T14,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	3211	0	0
CntIncr_A	8751421	117673	0	0
CntNoWrap_A	8751421	8081668	0	0
DetectStDropOut_A	8751421	521	0	0
DetectedOut_A	8751421	60423	0	0
DetectedPulseOut_A	8751421	825	0	0
DisabledIdleSt_A	8751421	7648826	0	0
DisabledNoDetection_A	8751421	7651100	0	0
EnterDebounceSt_A	8751421	1613	0	0
EnterDetectSt_A	8751421	1598	0	0
EnterStableSt_A	8751421	825	0	0
PulseIsPulse_A	8751421	825	0	0
StayInStableSt	8751421	59515	0	0
gen_high_event_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_high_level_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	714	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	3211	0	0
T1	18209	54	0	0
T2	6931	30	0	0
T3	173053	0	0	0
T9	0	46	0	0
T12	0	38	0	0
T13	0	12	0	0
T14	19415	24	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	32	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	56	0	0
T73	0	42	0	0
T74	0	60	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	117673	0	0
T1	18209	2214	0	0
T2	6931	949	0	0
T3	173053	0	0	0
T9	0	713	0	0
T12	0	1079	0	0
T13	0	252	0	0
T14	19415	1020	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	808	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	1485	0	0
T73	0	924	0	0
T74	0	2760	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8081668	0	0
T1	18209	17726	0	0
T2	6931	6500	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18959	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	521	0	0
T2	6931	14	0	0
T3	173053	0	0	0
T7	9947	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	16	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	28	0	0
T60	504	0	0	0
T86	0	11	0	0
T97	0	16	0	0
T98	0	5	0	0
T99	0	16	0	0
T256	0	6	0	0
T257	0	8	0	0
T258	0	28	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	60423	0	0
T1	18209	2344	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	1044	0	0
T13	0	1148	0	0
T14	19415	466	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T73	0	1291	0	0
T74	0	1988	0	0
T121	0	2219	0	0
T122	0	1309	0	0
T259	0	1358	0	0
T260	0	2334	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	825	0	0
T1	18209	27	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	23	0	0
T13	0	6	0	0
T14	19415	12	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T73	0	21	0	0
T74	0	30	0	0
T121	0	23	0	0
T122	0	24	0	0
T259	0	18	0	0
T260	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7648826	0	0
T1	18209	10553	0	0
T2	6931	3126	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	12672	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7651100	0	0
T1	18209	10554	0	0
T2	6931	3126	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	12676	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	1613	0	0
T1	18209	27	0	0
T2	6931	15	0	0
T3	173053	0	0	0
T9	0	23	0	0
T12	0	19	0	0
T13	0	6	0	0
T14	19415	12	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	16	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	28	0	0
T73	0	21	0	0
T74	0	30	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	1598	0	0
T1	18209	27	0	0
T2	6931	15	0	0
T3	173053	0	0	0
T9	0	23	0	0
T12	0	19	0	0
T13	0	6	0	0
T14	19415	12	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	16	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	28	0	0
T73	0	21	0	0
T74	0	30	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	825	0	0
T1	18209	27	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	23	0	0
T13	0	6	0	0
T14	19415	12	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T73	0	21	0	0
T74	0	30	0	0
T121	0	23	0	0
T122	0	24	0	0
T259	0	18	0	0
T260	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	825	0	0
T1	18209	27	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	23	0	0
T13	0	6	0	0
T14	19415	12	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T73	0	21	0	0
T74	0	30	0	0
T121	0	23	0	0
T122	0	24	0	0
T259	0	18	0	0
T260	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	59515	0	0
T1	18209	2314	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	1020	0	0
T13	0	1137	0	0
T14	19415	454	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T73	0	1270	0	0
T74	0	1955	0	0
T121	0	2188	0	0
T122	0	1281	0	0
T259	0	1337	0	0
T260	0	2308	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	714	0	0
T1	18209	24	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	22	0	0
T13	0	1	0	0
T14	19415	12	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T73	0	21	0	0
T74	0	27	0	0
T121	0	15	0	0
T122	0	20	0	0
T259	0	15	0	0
T260	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T80,T81,T100
1	0	Covered	T82,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T3,T7
1	0	Covered	T82

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T7
1	-	Covered	T1,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T7
DetectSt	168	Covered	T1,T3,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T7
DebounceSt->IdleSt	163	Covered	T7,T45,T34
DetectSt->IdleSt	186	Covered	T80,T81,T100
DetectSt->StableSt	191	Covered	T1,T3,T7
IdleSt->DebounceSt	148	Covered	T1,T3,T7
StableSt->IdleSt	206	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T7
0	1	Covered	T1,T3,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T45,T34
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T80,T81,T100
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	1098	0	0
CntIncr_A	8751421	54680	0	0
CntNoWrap_A	8751421	8083781	0	0
DetectStDropOut_A	8751421	81	0	0
DetectedOut_A	8751421	16096	0	0
DetectedPulseOut_A	8751421	429	0	0
DisabledIdleSt_A	8751421	7676023	0	0
DisabledNoDetection_A	8751421	7677630	0	0
EnterDebounceSt_A	8751421	586	0	0
EnterDetectSt_A	8751421	515	0	0
EnterStableSt_A	8751421	429	0	0
PulseIsPulse_A	8751421	429	0	0
StayInStableSt	8751421	15638	0	0
gen_high_level_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	397	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	1098	0	0
T1	18209	6	0	0
T2	6931	0	0	0
T3	173053	2	0	0
T7	0	5	0	0
T9	0	2	0	0
T10	0	6	0	0
T13	0	10	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	5	0	0
T45	0	1	0	0
T73	0	6	0	0
T80	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	54680	0	0
T1	18209	180	0	0
T2	6931	0	0	0
T3	173053	122	0	0
T7	0	258	0	0
T9	0	55	0	0
T10	0	474	0	0
T13	0	385	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	347	0	0
T45	0	20	0	0
T73	0	135	0	0
T80	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8083781	0	0
T1	18209	17774	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	81	0	0
T38	565	0	0	0
T42	570	0	0	0
T66	503	0	0	0
T73	6308	0	0	0
T74	16030	0	0	0
T80	3888	1	0	0
T81	0	10	0	0
T91	0	1	0	0
T96	1573	0	0	0
T100	0	3	0	0
T101	0	5	0	0
T102	0	1	0	0
T103	0	14	0	0
T104	0	2	0	0
T105	0	7	0	0
T106	0	5	0	0
T110	502	0	0	0
T111	423	0	0	0
T112	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	16096	0	0
T1	18209	255	0	0
T2	6931	0	0	0
T3	173053	82	0	0
T7	0	14	0	0
T9	0	51	0	0
T10	0	101	0	0
T13	0	236	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	84	0	0
T73	0	180	0	0
T74	0	58	0	0
T121	0	316	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	429	0	0
T1	18209	3	0	0
T2	6931	0	0	0
T3	173053	1	0	0
T7	0	2	0	0
T9	0	1	0	0
T10	0	3	0	0
T13	0	5	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	2	0	0
T73	0	3	0	0
T74	0	1	0	0
T121	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7676023	0	0
T1	18209	15439	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18517	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7677630	0	0
T1	18209	15441	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18522	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	586	0	0
T1	18209	3	0	0
T2	6931	0	0	0
T3	173053	1	0	0
T7	0	3	0	0
T9	0	1	0	0
T10	0	3	0	0
T13	0	5	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	3	0	0
T45	0	1	0	0
T73	0	3	0	0
T80	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	515	0	0
T1	18209	3	0	0
T2	6931	0	0	0
T3	173053	1	0	0
T7	0	2	0	0
T9	0	1	0	0
T10	0	3	0	0
T13	0	5	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	2	0	0
T73	0	3	0	0
T74	0	1	0	0
T80	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	429	0	0
T1	18209	3	0	0
T2	6931	0	0	0
T3	173053	1	0	0
T7	0	2	0	0
T9	0	1	0	0
T10	0	3	0	0
T13	0	5	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	2	0	0
T73	0	3	0	0
T74	0	1	0	0
T121	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	429	0	0
T1	18209	3	0	0
T2	6931	0	0	0
T3	173053	1	0	0
T7	0	2	0	0
T9	0	1	0	0
T10	0	3	0	0
T13	0	5	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	2	0	0
T73	0	3	0	0
T74	0	1	0	0
T121	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	15638	0	0
T1	18209	252	0	0
T2	6931	0	0	0
T3	173053	81	0	0
T7	0	12	0	0
T9	0	50	0	0
T10	0	98	0	0
T13	0	226	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	82	0	0
T73	0	177	0	0
T74	0	57	0	0
T121	0	302	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	397	0	0
T1	18209	3	0	0
T2	6931	0	0	0
T3	173053	1	0	0
T7	0	2	0	0
T9	0	1	0	0
T10	0	3	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	2	0	0
T39	0	5	0	0
T73	0	3	0	0
T74	0	1	0	0
T124	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T2
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T2
0	1	Covered	T2,T17,T13
1	0	Covered	T2,T13,T73

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T9
0	1	Covered	T1,T14,T9
1	0	Covered	T86,T87,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T14,T9
1	-	Covered	T1,T14,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T2
DetectSt	168	Covered	T1,T14,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T14,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T2
DebounceSt->IdleSt	163	Covered	T94,T82,T83
DetectSt->IdleSt	186	Covered	T2,T17,T13
DetectSt->StableSt	191	Covered	T1,T14,T9
IdleSt->DebounceSt	148	Covered	T1,T14,T2
StableSt->IdleSt	206	Covered	T1,T14,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T14,T2
0	1	Covered	T1,T14,T2
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T2
IdleSt	0	-	-	-	-	-	-	Covered	T1,T14,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T82,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T2
DetectSt	-	-	-	-	1	-	-	Covered	T2,T17,T13
DetectSt	-	-	-	-	0	1	-	Covered	T1,T14,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T14,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T14,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	2855	0	0
CntIncr_A	8751421	97038	0	0
CntNoWrap_A	8751421	8082024	0	0
DetectStDropOut_A	8751421	457	0	0
DetectedOut_A	8751421	55493	0	0
DetectedPulseOut_A	8751421	800	0	0
DisabledIdleSt_A	8751421	7654988	0	0
DisabledNoDetection_A	8751421	7657283	0	0
EnterDebounceSt_A	8751421	1436	0	0
EnterDetectSt_A	8751421	1419	0	0
EnterStableSt_A	8751421	800	0	0
PulseIsPulse_A	8751421	800	0	0
StayInStableSt	8751421	54631	0	0
gen_high_event_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_high_level_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	720	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	2855	0	0
T1	18209	12	0	0
T2	6931	18	0	0
T3	173053	0	0	0
T9	0	18	0	0
T12	0	42	0	0
T13	0	30	0	0
T14	19415	24	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	28	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	56	0	0
T73	0	22	0	0
T74	0	60	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	97038	0	0
T1	18209	474	0	0
T2	6931	575	0	0
T3	173053	0	0	0
T9	0	369	0	0
T12	0	1071	0	0
T13	0	923	0	0
T14	19415	1092	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	710	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	1485	0	0
T73	0	545	0	0
T74	0	2430	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8082024	0	0
T1	18209	17768	0	0
T2	6931	6512	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18959	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	457	0	0
T2	6931	6	0	0
T3	173053	0	0	0
T7	9947	0	0	0
T13	0	6	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	14	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	28	0	0
T60	504	0	0	0
T86	0	16	0	0
T97	0	7	0	0
T98	0	12	0	0
T99	0	20	0	0
T256	0	10	0	0
T261	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	55493	0	0
T1	18209	469	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	138	0	0
T12	0	1056	0	0
T14	19415	1479	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T74	0	2318	0	0
T121	0	315	0	0
T122	0	2349	0	0
T259	0	2447	0	0
T260	0	671	0	0
T262	0	3296	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	800	0	0
T1	18209	6	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	9	0	0
T12	0	21	0	0
T14	19415	12	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T74	0	30	0	0
T121	0	11	0	0
T122	0	26	0	0
T259	0	29	0	0
T260	0	8	0	0
T262	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7654988	0	0
T1	18209	12011	0	0
T2	6931	3126	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	11587	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7657283	0	0
T1	18209	12014	0	0
T2	6931	3126	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	11589	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	1436	0	0
T1	18209	6	0	0
T2	6931	9	0	0
T3	173053	0	0	0
T9	0	9	0	0
T12	0	21	0	0
T13	0	15	0	0
T14	19415	12	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	14	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	28	0	0
T73	0	11	0	0
T74	0	30	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	1419	0	0
T1	18209	6	0	0
T2	6931	9	0	0
T3	173053	0	0	0
T9	0	9	0	0
T12	0	21	0	0
T13	0	15	0	0
T14	19415	12	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	14	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	28	0	0
T73	0	11	0	0
T74	0	30	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	800	0	0
T1	18209	6	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	9	0	0
T12	0	21	0	0
T14	19415	12	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T74	0	30	0	0
T121	0	11	0	0
T122	0	26	0	0
T259	0	29	0	0
T260	0	8	0	0
T262	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	800	0	0
T1	18209	6	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	9	0	0
T12	0	21	0	0
T14	19415	12	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T74	0	30	0	0
T121	0	11	0	0
T122	0	26	0	0
T259	0	29	0	0
T260	0	8	0	0
T262	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	54631	0	0
T1	18209	462	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	129	0	0
T12	0	1034	0	0
T14	19415	1465	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T74	0	2285	0	0
T121	0	303	0	0
T122	0	2319	0	0
T259	0	2412	0	0
T260	0	663	0	0
T262	0	3273	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	720	0	0
T1	18209	5	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	9	0	0
T12	0	20	0	0
T14	19415	10	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T74	0	27	0	0
T121	0	10	0	0
T122	0	22	0	0
T259	0	23	0	0
T260	0	8	0	0
T262	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T14,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T3
0	1	Covered	T80,T263,T149
1	0	Covered	T82,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T82

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T14,T3
1	-	Covered	T1,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T3
DetectSt	168	Covered	T1,T14,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T14,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T3
DebounceSt->IdleSt	163	Covered	T7,T34,T80
DetectSt->IdleSt	186	Covered	T80,T263,T149
DetectSt->StableSt	191	Covered	T1,T14,T3
IdleSt->DebounceSt	148	Covered	T1,T14,T3
StableSt->IdleSt	206	Covered	T1,T14,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T14,T3
0	1	Covered	T1,T14,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T34,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T3
DetectSt	-	-	-	-	1	-	-	Covered	T80,T263,T149
DetectSt	-	-	-	-	0	1	-	Covered	T1,T14,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T14,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	904	0	0
CntIncr_A	8751421	47475	0	0
CntNoWrap_A	8751421	8083975	0	0
DetectStDropOut_A	8751421	64	0	0
DetectedOut_A	8751421	14305	0	0
DetectedPulseOut_A	8751421	360	0	0
DisabledIdleSt_A	8751421	7691603	0	0
DisabledNoDetection_A	8751421	7693320	0	0
EnterDebounceSt_A	8751421	477	0	0
EnterDetectSt_A	8751421	430	0	0
EnterStableSt_A	8751421	360	0	0
PulseIsPulse_A	8751421	360	0	0
StayInStableSt	8751421	13928	0	0
gen_high_level_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	342	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	904	0	0
T1	18209	2	0	0
T2	6931	0	0	0
T3	173053	4	0	0
T7	0	7	0	0
T10	0	4	0	0
T12	0	4	0	0
T14	19415	4	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	7	0	0
T74	0	6	0	0
T80	0	3	0	0
T121	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	47475	0	0
T1	18209	73	0	0
T2	6931	0	0	0
T3	173053	368	0	0
T7	0	244	0	0
T10	0	284	0	0
T12	0	114	0	0
T14	19415	166	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	545	0	0
T74	0	195	0	0
T80	0	90	0	0
T121	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8083975	0	0
T1	18209	17778	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18979	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	64	0	0
T38	565	0	0	0
T42	570	0	0	0
T66	503	0	0	0
T73	6308	0	0	0
T74	16030	0	0	0
T80	3888	1	0	0
T96	1573	0	0	0
T100	0	5	0	0
T104	0	2	0	0
T110	502	0	0	0
T111	423	0	0	0
T112	407	0	0	0
T114	0	3	0	0
T126	0	4	0	0
T149	0	13	0	0
T263	0	1	0	0
T264	0	4	0	0
T265	0	4	0	0
T266	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	14305	0	0
T1	18209	73	0	0
T2	6931	0	0	0
T3	173053	40	0	0
T7	0	152	0	0
T10	0	98	0	0
T12	0	54	0	0
T14	19415	191	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	57	0	0
T39	0	52	0	0
T74	0	269	0	0
T121	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	360	0	0
T1	18209	1	0	0
T2	6931	0	0	0
T3	173053	2	0	0
T7	0	3	0	0
T10	0	2	0	0
T12	0	2	0	0
T14	19415	2	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	3	0	0
T39	0	1	0	0
T74	0	3	0	0
T121	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7691603	0	0
T1	18209	17309	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	17506	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7693320	0	0
T1	18209	17313	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	17509	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	477	0	0
T1	18209	1	0	0
T2	6931	0	0	0
T3	173053	2	0	0
T7	0	4	0	0
T10	0	2	0	0
T12	0	2	0	0
T14	19415	2	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	4	0	0
T74	0	3	0	0
T80	0	2	0	0
T121	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	430	0	0
T1	18209	1	0	0
T2	6931	0	0	0
T3	173053	2	0	0
T7	0	3	0	0
T10	0	2	0	0
T12	0	2	0	0
T14	19415	2	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	3	0	0
T74	0	3	0	0
T80	0	1	0	0
T121	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	360	0	0
T1	18209	1	0	0
T2	6931	0	0	0
T3	173053	2	0	0
T7	0	3	0	0
T10	0	2	0	0
T12	0	2	0	0
T14	19415	2	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	3	0	0
T39	0	1	0	0
T74	0	3	0	0
T121	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	360	0	0
T1	18209	1	0	0
T2	6931	0	0	0
T3	173053	2	0	0
T7	0	3	0	0
T10	0	2	0	0
T12	0	2	0	0
T14	19415	2	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	3	0	0
T39	0	1	0	0
T74	0	3	0	0
T121	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	13928	0	0
T1	18209	72	0	0
T2	6931	0	0	0
T3	173053	38	0	0
T7	0	149	0	0
T10	0	96	0	0
T12	0	52	0	0
T14	19415	187	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	54	0	0
T39	0	51	0	0
T74	0	266	0	0
T121	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	342	0	0
T1	18209	1	0	0
T2	6931	0	0	0
T3	173053	2	0	0
T7	0	3	0	0
T10	0	2	0	0
T12	0	2	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	3	0	0
T39	0	1	0	0
T74	0	3	0	0
T81	0	5	0	0
T121	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T2
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T1,T14,T9
1	1	Covered	T1,T14,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T2
0	1	Covered	T17,T48,T99
1	0	Covered	T9,T13,T98

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T2
0	1	Covered	T1,T14,T2
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T14,T2
1	-	Covered	T1,T14,T2

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T2
DetectSt	168	Covered	T1,T14,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T14,T2

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T2
DebounceSt->IdleSt	163	Covered	T94,T82,T83
DetectSt->IdleSt	186	Covered	T17,T9,T13
DetectSt->StableSt	191	Covered	T1,T14,T2
IdleSt->DebounceSt	148	Covered	T1,T14,T2
StableSt->IdleSt	206	Covered	T1,T14,T2

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T14,T2
0	1	Covered	T1,T14,T2
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T2
IdleSt	0	-	-	-	-	-	-	Covered	T1,T14,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T82,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T2
DetectSt	-	-	-	-	1	-	-	Covered	T17,T9,T13
DetectSt	-	-	-	-	0	1	-	Covered	T1,T14,T2
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T14,T2
StableSt	-	-	-	-	-	-	0	Covered	T1,T14,T2
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	2889	0	0
CntIncr_A	8751421	99786	0	0
CntNoWrap_A	8751421	8081990	0	0
DetectStDropOut_A	8751421	404	0	0
DetectedOut_A	8751421	67464	0	0
DetectedPulseOut_A	8751421	857	0	0
DisabledIdleSt_A	8751421	7643611	0	0
DisabledNoDetection_A	8751421	7645891	0	0
EnterDebounceSt_A	8751421	1457	0	0
EnterDetectSt_A	8751421	1433	0	0
EnterStableSt_A	8751421	857	0	0
PulseIsPulse_A	8751421	857	0	0
StayInStableSt	8751421	66531	0	0
gen_high_event_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_high_level_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	780	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	2889	0	0
T1	18209	32	0	0
T2	6931	18	0	0
T3	173053	0	0	0
T9	0	18	0	0
T12	0	38	0	0
T13	0	12	0	0
T14	19415	42	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	12	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	58	0	0
T73	0	10	0	0
T74	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	99786	0	0
T1	18209	1008	0	0
T2	6931	486	0	0
T3	173053	0	0	0
T9	0	493	0	0
T12	0	988	0	0
T13	0	371	0	0
T14	19415	1512	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	300	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	1529	0	0
T73	0	195	0	0
T74	0	1449	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8081990	0	0
T1	18209	17748	0	0
T2	6931	6512	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18941	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	404	0	0
T3	173053	0	0	0
T7	9947	0	0	0
T17	5170	6	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	29	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T99	0	26	0	0
T177	0	7	0	0
T179	0	13	0	0
T256	0	24	0	0
T257	0	29	0	0
T258	0	6	0	0
T261	0	4	0	0
T267	0	20	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	67464	0	0
T1	18209	2216	0	0
T2	6931	1196	0	0
T3	173053	0	0	0
T12	0	292	0	0
T14	19415	3633	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T73	0	608	0	0
T74	0	2553	0	0
T97	0	1534	0	0
T121	0	1308	0	0
T122	0	420	0	0
T259	0	2801	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	857	0	0
T1	18209	16	0	0
T2	6931	9	0	0
T3	173053	0	0	0
T12	0	19	0	0
T14	19415	21	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T73	0	5	0	0
T74	0	23	0	0
T97	0	7	0	0
T121	0	24	0	0
T122	0	4	0	0
T259	0	29	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7643611	0	0
T1	18209	10763	0	0
T2	6931	2015	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	10118	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7645891	0	0
T1	18209	10765	0	0
T2	6931	2015	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	10118	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	1457	0	0
T1	18209	16	0	0
T2	6931	9	0	0
T3	173053	0	0	0
T9	0	9	0	0
T12	0	19	0	0
T13	0	6	0	0
T14	19415	21	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	6	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	29	0	0
T73	0	5	0	0
T74	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	1433	0	0
T1	18209	16	0	0
T2	6931	9	0	0
T3	173053	0	0	0
T9	0	9	0	0
T12	0	19	0	0
T13	0	6	0	0
T14	19415	21	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	6	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	29	0	0
T73	0	5	0	0
T74	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	857	0	0
T1	18209	16	0	0
T2	6931	9	0	0
T3	173053	0	0	0
T12	0	19	0	0
T14	19415	21	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T73	0	5	0	0
T74	0	23	0	0
T97	0	7	0	0
T121	0	24	0	0
T122	0	4	0	0
T259	0	29	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	857	0	0
T1	18209	16	0	0
T2	6931	9	0	0
T3	173053	0	0	0
T12	0	19	0	0
T14	19415	21	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T73	0	5	0	0
T74	0	23	0	0
T97	0	7	0	0
T121	0	24	0	0
T122	0	4	0	0
T259	0	29	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	66531	0	0
T1	18209	2198	0	0
T2	6931	1187	0	0
T3	173053	0	0	0
T12	0	272	0	0
T14	19415	3608	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T73	0	603	0	0
T74	0	2528	0	0
T97	0	1522	0	0
T121	0	1281	0	0
T122	0	415	0	0
T259	0	2767	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	780	0	0
T1	18209	14	0	0
T2	6931	9	0	0
T3	173053	0	0	0
T12	0	18	0	0
T14	19415	17	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T73	0	5	0	0
T74	0	21	0	0
T97	0	2	0	0
T121	0	21	0	0
T122	0	3	0	0
T259	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T14,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T2
0	1	Covered	T80,T39,T263
1	0	Covered	T82,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T82,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T14,T2
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T2
DetectSt	168	Covered	T1,T14,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T14,T2

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T2
DebounceSt->IdleSt	163	Covered	T1,T14,T2
DetectSt->IdleSt	186	Covered	T80,T39,T263
DetectSt->StableSt	191	Covered	T1,T14,T2
IdleSt->DebounceSt	148	Covered	T1,T14,T2
StableSt->IdleSt	206	Covered	T1,T14,T2

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T14,T2
0	1	Covered	T1,T14,T2
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T14,T2
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T2
DetectSt	-	-	-	-	1	-	-	Covered	T80,T39,T263
DetectSt	-	-	-	-	0	1	-	Covered	T1,T14,T2
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T14,T2
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	875	0	0
CntIncr_A	8751421	46683	0	0
CntNoWrap_A	8751421	8084004	0	0
DetectStDropOut_A	8751421	66	0	0
DetectedOut_A	8751421	13963	0	0
DetectedPulseOut_A	8751421	341	0	0
DisabledIdleSt_A	8751421	7673456	0	0
DisabledNoDetection_A	8751421	7675133	0	0
EnterDebounceSt_A	8751421	466	0	0
EnterDetectSt_A	8751421	410	0	0
EnterStableSt_A	8751421	341	0	0
PulseIsPulse_A	8751421	341	0	0
StayInStableSt	8751421	13599	0	0
gen_high_level_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	316	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	875	0	0
T1	18209	5	0	0
T2	6931	5	0	0
T3	173053	6	0	0
T7	0	3	0	0
T10	0	4	0	0
T12	0	4	0	0
T14	19415	7	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	11	0	0
T73	0	6	0	0
T80	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	46683	0	0
T1	18209	222	0	0
T2	6931	168	0	0
T3	173053	504	0	0
T7	0	92	0	0
T10	0	218	0	0
T12	0	82	0	0
T14	19415	347	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	904	0	0
T73	0	159	0	0
T80	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8084004	0	0
T1	18209	17775	0	0
T2	6931	6525	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18976	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	66	0	0
T38	565	0	0	0
T39	0	1	0	0
T42	570	0	0	0
T66	503	0	0	0
T73	6308	0	0	0
T74	16030	0	0	0
T80	3888	1	0	0
T96	1573	0	0	0
T101	0	9	0	0
T106	0	5	0	0
T110	502	0	0	0
T111	423	0	0	0
T112	407	0	0	0
T114	0	3	0	0
T126	0	2	0	0
T149	0	6	0	0
T203	0	1	0	0
T206	0	1	0	0
T263	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	13963	0	0
T1	18209	112	0	0
T2	6931	79	0	0
T3	173053	108	0	0
T7	0	58	0	0
T10	0	164	0	0
T12	0	84	0	0
T14	19415	251	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	40	0	0
T73	0	156	0	0
T74	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	341	0	0
T1	18209	2	0	0
T2	6931	2	0	0
T3	173053	3	0	0
T7	0	1	0	0
T10	0	2	0	0
T12	0	2	0	0
T14	19415	3	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	5	0	0
T73	0	3	0	0
T74	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7673456	0	0
T1	18209	15563	0	0
T2	6931	5334	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	15354	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7675133	0	0
T1	18209	15566	0	0
T2	6931	5335	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	15355	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	466	0	0
T1	18209	3	0	0
T2	6931	3	0	0
T3	173053	3	0	0
T7	0	2	0	0
T10	0	2	0	0
T12	0	2	0	0
T14	19415	4	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	6	0	0
T73	0	3	0	0
T80	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	410	0	0
T1	18209	2	0	0
T2	6931	2	0	0
T3	173053	3	0	0
T7	0	1	0	0
T10	0	2	0	0
T12	0	2	0	0
T14	19415	3	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	5	0	0
T73	0	3	0	0
T80	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	341	0	0
T1	18209	2	0	0
T2	6931	2	0	0
T3	173053	3	0	0
T7	0	1	0	0
T10	0	2	0	0
T12	0	2	0	0
T14	19415	3	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	5	0	0
T73	0	3	0	0
T74	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	341	0	0
T1	18209	2	0	0
T2	6931	2	0	0
T3	173053	3	0	0
T7	0	1	0	0
T10	0	2	0	0
T12	0	2	0	0
T14	19415	3	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	5	0	0
T73	0	3	0	0
T74	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	13599	0	0
T1	18209	110	0	0
T2	6931	77	0	0
T3	173053	105	0	0
T7	0	57	0	0
T10	0	162	0	0
T12	0	81	0	0
T14	19415	245	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	35	0	0
T73	0	153	0	0
T74	0	78	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	316	0	0
T1	18209	2	0	0
T2	6931	2	0	0
T3	173053	3	0	0
T7	0	1	0	0
T10	0	2	0	0
T12	0	1	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	5	0	0
T73	0	3	0	0
T74	0	1	0	0
T121	0	1	0	0