Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T2
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T2
0	1	Covered	T2,T17,T48
1	0	Covered	T2,T73,T97

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T9
0	1	Covered	T1,T14,T9
1	0	Covered	T82,T268,T269

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T14,T9
1	-	Covered	T1,T14,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T2
DetectSt	168	Covered	T1,T14,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T14,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T2
DebounceSt->IdleSt	163	Covered	T94,T82,T83
DetectSt->IdleSt	186	Covered	T2,T17,T48
DetectSt->StableSt	191	Covered	T1,T14,T9
IdleSt->DebounceSt	148	Covered	T1,T14,T2
StableSt->IdleSt	206	Covered	T1,T14,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T14,T2
0	1	Covered	T1,T14,T2
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T2
IdleSt	0	-	-	-	-	-	-	Covered	T1,T14,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T82,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T2
DetectSt	-	-	-	-	1	-	-	Covered	T2,T17,T48
DetectSt	-	-	-	-	0	1	-	Covered	T1,T14,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T14,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T14,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	3281	0	0
CntIncr_A	8751421	115385	0	0
CntNoWrap_A	8751421	8081598	0	0
DetectStDropOut_A	8751421	550	0	0
DetectedOut_A	8751421	69412	0	0
DetectedPulseOut_A	8751421	899	0	0
DisabledIdleSt_A	8751421	7646282	0	0
DisabledNoDetection_A	8751421	7648576	0	0
EnterDebounceSt_A	8751421	1652	0	0
EnterDetectSt_A	8751421	1629	0	0
EnterStableSt_A	8751421	899	0	0
PulseIsPulse_A	8751421	899	0	0
StayInStableSt	8751421	68451	0	0
gen_high_event_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_high_level_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	828	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	3281	0	0
T1	18209	54	0	0
T2	6931	50	0	0
T3	173053	0	0	0
T9	0	50	0	0
T12	0	42	0	0
T13	0	14	0	0
T14	19415	30	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	52	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	56	0	0
T73	0	32	0	0
T74	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	115385	0	0
T1	18209	1998	0	0
T2	6931	1606	0	0
T3	173053	0	0	0
T9	0	975	0	0
T12	0	966	0	0
T13	0	399	0	0
T14	19415	1425	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	1327	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	1485	0	0
T73	0	780	0	0
T74	0	1886	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8081598	0	0
T1	18209	17726	0	0
T2	6931	6480	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18953	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	550	0	0
T2	6931	21	0	0
T3	173053	0	0	0
T7	9947	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	26	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	28	0	0
T60	504	0	0	0
T73	0	11	0	0
T97	0	12	0	0
T99	0	21	0	0
T256	0	23	0	0
T257	0	13	0	0
T261	0	7	0	0
T270	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	69412	0	0
T1	18209	2560	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	1211	0	0
T12	0	859	0	0
T13	0	1499	0	0
T14	19415	793	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T74	0	864	0	0
T98	0	944	0	0
T121	0	757	0	0
T122	0	2293	0	0
T259	0	1001	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	899	0	0
T1	18209	27	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	25	0	0
T12	0	21	0	0
T13	0	7	0	0
T14	19415	15	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T74	0	23	0	0
T98	0	26	0	0
T121	0	14	0	0
T122	0	24	0	0
T259	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7646282	0	0
T1	18209	10569	0	0
T2	6931	3126	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	12302	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7648576	0	0
T1	18209	10570	0	0
T2	6931	3126	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	12305	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	1652	0	0
T1	18209	27	0	0
T2	6931	25	0	0
T3	173053	0	0	0
T9	0	25	0	0
T12	0	21	0	0
T13	0	7	0	0
T14	19415	15	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	26	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	28	0	0
T73	0	16	0	0
T74	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	1629	0	0
T1	18209	27	0	0
T2	6931	25	0	0
T3	173053	0	0	0
T9	0	25	0	0
T12	0	21	0	0
T13	0	7	0	0
T14	19415	15	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	26	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T48	0	28	0	0
T73	0	16	0	0
T74	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	899	0	0
T1	18209	27	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	25	0	0
T12	0	21	0	0
T13	0	7	0	0
T14	19415	15	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T74	0	23	0	0
T98	0	26	0	0
T121	0	14	0	0
T122	0	24	0	0
T259	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	899	0	0
T1	18209	27	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	25	0	0
T12	0	21	0	0
T13	0	7	0	0
T14	19415	15	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T74	0	23	0	0
T98	0	26	0	0
T121	0	14	0	0
T122	0	24	0	0
T259	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	68451	0	0
T1	18209	2530	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	1186	0	0
T12	0	835	0	0
T13	0	1487	0	0
T14	19415	777	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T74	0	841	0	0
T98	0	918	0	0
T121	0	741	0	0
T122	0	2265	0	0
T259	0	986	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	828	0	0
T1	18209	24	0	0
T2	6931	0	0	0
T3	173053	0	0	0
T9	0	25	0	0
T12	0	18	0	0
T13	0	2	0	0
T14	19415	14	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T74	0	23	0	0
T98	0	26	0	0
T121	0	12	0	0
T122	0	20	0	0
T259	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T14,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T3
0	1	Covered	T80,T271,T272
1	0	Covered	T82,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T3
0	1	Covered	T1,T3,T7
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T14,T3
1	-	Covered	T1,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T3
DetectSt	168	Covered	T1,T14,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T14,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T3
DebounceSt->IdleSt	163	Covered	T7,T34,T124
DetectSt->IdleSt	186	Covered	T80,T271,T272
DetectSt->StableSt	191	Covered	T1,T14,T3
IdleSt->DebounceSt	148	Covered	T1,T14,T3
StableSt->IdleSt	206	Covered	T1,T14,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T14,T3
0	1	Covered	T1,T14,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T34,T124
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T3
DetectSt	-	-	-	-	1	-	-	Covered	T80,T271,T272
DetectSt	-	-	-	-	0	1	-	Covered	T1,T14,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T14,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	912	0	0
CntIncr_A	8751421	49426	0	0
CntNoWrap_A	8751421	8083967	0	0
DetectStDropOut_A	8751421	59	0	0
DetectedOut_A	8751421	15775	0	0
DetectedPulseOut_A	8751421	372	0	0
DisabledIdleSt_A	8751421	7674264	0	0
DisabledNoDetection_A	8751421	7675955	0	0
EnterDebounceSt_A	8751421	480	0	0
EnterDetectSt_A	8751421	436	0	0
EnterStableSt_A	8751421	372	0	0
PulseIsPulse_A	8751421	372	0	0
StayInStableSt	8751421	15385	0	0
gen_high_level_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	353	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	912	0	0
T1	18209	6	0	0
T2	6931	0	0	0
T3	173053	2	0	0
T7	0	3	0	0
T9	0	4	0	0
T10	0	6	0	0
T12	0	6	0	0
T13	0	10	0	0
T14	19415	2	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	27	0	0
T80	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	49426	0	0
T1	18209	249	0	0
T2	6931	0	0	0
T3	173053	194	0	0
T7	0	127	0	0
T9	0	80	0	0
T10	0	462	0	0
T12	0	99	0	0
T13	0	315	0	0
T14	19415	89	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	1479	0	0
T80	0	284	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8083967	0	0
T1	18209	17774	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18981	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	59	0	0
T38	565	0	0	0
T42	570	0	0	0
T66	503	0	0	0
T73	6308	0	0	0
T74	16030	0	0	0
T80	3888	6	0	0
T82	0	1	0	0
T93	0	3	0	0
T96	1573	0	0	0
T110	502	0	0	0
T111	423	0	0	0
T112	407	0	0	0
T161	0	8	0	0
T271	0	7	0	0
T272	0	6	0	0
T273	0	4	0	0
T274	0	4	0	0
T275	0	2	0	0
T276	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	15775	0	0
T1	18209	186	0	0
T2	6931	0	0	0
T3	173053	10	0	0
T7	0	23	0	0
T9	0	132	0	0
T10	0	111	0	0
T12	0	148	0	0
T13	0	314	0	0
T14	19415	90	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	855	0	0
T74	0	190	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	372	0	0
T1	18209	3	0	0
T2	6931	0	0	0
T3	173053	1	0	0
T7	0	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	3	0	0
T13	0	5	0	0
T14	19415	1	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	12	0	0
T74	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7674264	0	0
T1	18209	15223	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18191	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7675955	0	0
T1	18209	15225	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18195	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	480	0	0
T1	18209	3	0	0
T2	6931	0	0	0
T3	173053	1	0	0
T7	0	2	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	3	0	0
T13	0	5	0	0
T14	19415	1	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	15	0	0
T80	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	436	0	0
T1	18209	3	0	0
T2	6931	0	0	0
T3	173053	1	0	0
T7	0	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	3	0	0
T13	0	5	0	0
T14	19415	1	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	12	0	0
T80	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	372	0	0
T1	18209	3	0	0
T2	6931	0	0	0
T3	173053	1	0	0
T7	0	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	3	0	0
T13	0	5	0	0
T14	19415	1	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	12	0	0
T74	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	372	0	0
T1	18209	3	0	0
T2	6931	0	0	0
T3	173053	1	0	0
T7	0	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	3	0	0
T13	0	5	0	0
T14	19415	1	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	12	0	0
T74	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	15385	0	0
T1	18209	183	0	0
T2	6931	0	0	0
T3	173053	9	0	0
T7	0	22	0	0
T9	0	130	0	0
T10	0	108	0	0
T12	0	142	0	0
T13	0	309	0	0
T14	19415	88	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	843	0	0
T74	0	188	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	353	0	0
T1	18209	3	0	0
T2	6931	0	0	0
T3	173053	1	0	0
T7	0	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T13	0	5	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	0	0	0
T19	402	0	0	0
T20	438	0	0	0
T34	0	12	0	0
T39	0	1	0	0
T74	0	2	0	0
T124	0	4	0	0