Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1307941163	10199	0	0
auto_block_debounce_ctl_rd_A	1307941163	1996	0	0
auto_block_out_ctl_rd_A	1307941163	3147	0	0
com_det_ctl_0_rd_A	1307941163	3780	0	0
com_det_ctl_1_rd_A	1307941163	4050	0	0
com_det_ctl_2_rd_A	1307941163	3842	0	0
com_det_ctl_3_rd_A	1307941163	3958	0	0
com_out_ctl_0_rd_A	1307941163	4669	0	0
com_out_ctl_1_rd_A	1307941163	4679	0	0
com_out_ctl_2_rd_A	1307941163	4636	0	0
com_out_ctl_3_rd_A	1307941163	4641	0	0
com_pre_det_ctl_0_rd_A	1307941163	1689	0	0
com_pre_det_ctl_1_rd_A	1307941163	1582	0	0
com_pre_det_ctl_2_rd_A	1307941163	1566	0	0
com_pre_det_ctl_3_rd_A	1307941163	1679	0	0
com_pre_sel_ctl_0_rd_A	1307941163	4900	0	0
com_pre_sel_ctl_1_rd_A	1307941163	5181	0	0
com_pre_sel_ctl_2_rd_A	1307941163	5058	0	0
com_pre_sel_ctl_3_rd_A	1307941163	5141	0	0
com_sel_ctl_0_rd_A	1307941163	4942	0	0
com_sel_ctl_1_rd_A	1307941163	4815	0	0
com_sel_ctl_2_rd_A	1307941163	5006	0	0
com_sel_ctl_3_rd_A	1307941163	4792	0	0
ec_rst_ctl_rd_A	1307941163	2457	0	0
intr_enable_rd_A	1307941163	2226	0	0
key_intr_ctl_rd_A	1307941163	4787	0	0
key_intr_debounce_ctl_rd_A	1307941163	1671	0	0
key_invert_ctl_rd_A	1307941163	6288	0	0
pin_allowed_ctl_rd_A	1307941163	6893	0	0
pin_out_ctl_rd_A	1307941163	5299	0	0
pin_out_value_rd_A	1307941163	5131	0	0
regwen_rd_A	1307941163	1986	0	0
ulp_ac_debounce_ctl_rd_A	1307941163	1709	0	0
ulp_ctl_rd_A	1307941163	1720	0	0
ulp_lid_debounce_ctl_rd_A	1307941163	1716	0	0
ulp_pwrb_debounce_ctl_rd_A	1307941163	1732	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	10199	0	0
T28	0	9	0	0
T36	0	17	0	0
T39	313642	13	0	0
T41	0	6	0	0
T51	0	7	0	0
T58	17185	0	0	0
T75	0	8	0	0
T81	207314	0	0	0
T102	0	12	0	0
T124	670206	0	0	0
T126	0	21	0	0
T212	65678	0	0	0
T213	63288	0	0	0
T214	105677	0	0	0
T215	325222	0	0	0
T216	125817	0	0	0
T217	194355	0	0	0
T218	0	19	0	0
T299	0	2	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	1996	0	0
T1	728356	0	0	0
T2	346572	0	0	0
T6	76525	15	0	0
T14	931927	0	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T21	19020	0	0	0
T22	60776	0	0	0
T28	0	38	0	0
T36	0	27	0	0
T41	0	10	0	0
T47	0	6	0	0
T75	0	21	0	0
T123	0	14	0	0
T218	0	36	0	0
T300	0	6	0	0
T301	0	12	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	3147	0	0
T1	728356	0	0	0
T2	346572	0	0	0
T6	76525	8	0	0
T14	931927	0	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T21	19020	0	0	0
T22	60776	0	0	0
T28	0	29	0	0
T36	0	19	0	0
T41	0	9	0	0
T47	0	11	0	0
T75	0	24	0	0
T123	0	10	0	0
T218	0	34	0	0
T300	0	9	0	0
T301	0	12	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	3780	0	0
T1	728356	27	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	46	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	8	0	0
T41	0	10	0	0
T73	0	39	0	0
T121	0	61	0	0
T259	0	53	0	0
T263	0	57	0	0
T302	0	72	0	0
T303	0	16	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	4050	0	0
T1	728356	33	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	64	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	8	0	0
T41	0	6	0	0
T73	0	39	0	0
T121	0	59	0	0
T259	0	47	0	0
T263	0	83	0	0
T302	0	88	0	0
T303	0	46	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	3842	0	0
T1	728356	42	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	61	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	13	0	0
T41	0	3	0	0
T73	0	26	0	0
T121	0	64	0	0
T259	0	37	0	0
T263	0	73	0	0
T302	0	78	0	0
T303	0	36	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	3958	0	0
T1	728356	23	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	65	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	1	0	0
T41	0	4	0	0
T73	0	16	0	0
T121	0	64	0	0
T259	0	25	0	0
T263	0	96	0	0
T302	0	79	0	0
T303	0	31	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	4669	0	0
T1	728356	42	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	47	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	5	0	0
T41	0	9	0	0
T73	0	50	0	0
T121	0	54	0	0
T259	0	37	0	0
T263	0	61	0	0
T302	0	85	0	0
T303	0	56	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	4679	0	0
T1	728356	24	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	68	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	9	0	0
T41	0	8	0	0
T73	0	37	0	0
T121	0	56	0	0
T259	0	21	0	0
T263	0	72	0	0
T302	0	52	0	0
T303	0	45	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	4636	0	0
T1	728356	22	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	76	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	12	0	0
T41	0	4	0	0
T73	0	30	0	0
T121	0	58	0	0
T259	0	27	0	0
T263	0	70	0	0
T302	0	84	0	0
T303	0	40	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	4641	0	0
T1	728356	28	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	57	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	5	0	0
T36	0	51	0	0
T73	0	25	0	0
T121	0	47	0	0
T259	0	52	0	0
T263	0	55	0	0
T302	0	58	0	0
T303	0	32	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	1689	0	0
T28	108560	11	0	0
T36	0	8	0	0
T41	0	9	0	0
T75	0	25	0	0
T218	0	26	0	0
T250	0	21	0	0
T263	736464	0	0	0
T304	0	11	0	0
T305	0	15	0	0
T306	0	10	0	0
T307	0	15	0	0
T308	198382	0	0	0
T309	208222	0	0	0
T310	63320	0	0	0
T311	120942	0	0	0
T312	15335	0	0	0
T313	202818	0	0	0
T314	69244	0	0	0
T315	65562	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	1582	0	0
T23	0	18	0	0
T28	108560	7	0	0
T41	0	6	0	0
T75	0	35	0	0
T218	0	18	0	0
T250	0	13	0	0
T263	736464	0	0	0
T304	0	11	0	0
T305	0	4	0	0
T306	0	21	0	0
T307	0	20	0	0
T308	198382	0	0	0
T309	208222	0	0	0
T310	63320	0	0	0
T311	120942	0	0	0
T312	15335	0	0	0
T313	202818	0	0	0
T314	69244	0	0	0
T315	65562	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	1566	0	0
T28	108560	7	0	0
T36	0	1	0	0
T41	0	6	0	0
T75	0	24	0	0
T218	0	7	0	0
T250	0	36	0	0
T263	736464	0	0	0
T284	0	1	0	0
T305	0	14	0	0
T306	0	18	0	0
T307	0	10	0	0
T308	198382	0	0	0
T309	208222	0	0	0
T310	63320	0	0	0
T311	120942	0	0	0
T312	15335	0	0	0
T313	202818	0	0	0
T314	69244	0	0	0
T315	65562	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	1679	0	0
T28	108560	6	0	0
T36	0	9	0	0
T41	0	12	0	0
T75	0	38	0	0
T218	0	4	0	0
T250	0	28	0	0
T263	736464	0	0	0
T304	0	9	0	0
T305	0	15	0	0
T306	0	18	0	0
T307	0	23	0	0
T308	198382	0	0	0
T309	208222	0	0	0
T310	63320	0	0	0
T311	120942	0	0	0
T312	15335	0	0	0
T313	202818	0	0	0
T314	69244	0	0	0
T315	65562	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	4900	0	0
T1	728356	31	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	69	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	18	0	0
T41	0	2	0	0
T73	0	48	0	0
T121	0	31	0	0
T259	0	29	0	0
T263	0	65	0	0
T302	0	42	0	0
T303	0	52	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	5181	0	0
T1	728356	42	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	58	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	16	0	0
T41	0	11	0	0
T73	0	30	0	0
T121	0	45	0	0
T259	0	57	0	0
T263	0	77	0	0
T302	0	60	0	0
T303	0	64	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	5058	0	0
T1	728356	38	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	71	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	16	0	0
T41	0	14	0	0
T73	0	32	0	0
T121	0	54	0	0
T259	0	32	0	0
T263	0	72	0	0
T302	0	72	0	0
T303	0	27	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	5141	0	0
T1	728356	42	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	45	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	11	0	0
T41	0	11	0	0
T73	0	50	0	0
T121	0	71	0	0
T259	0	23	0	0
T263	0	55	0	0
T302	0	68	0	0
T303	0	53	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	4942	0	0
T1	728356	26	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	80	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	8	0	0
T41	0	11	0	0
T73	0	44	0	0
T121	0	67	0	0
T259	0	28	0	0
T263	0	86	0	0
T302	0	65	0	0
T303	0	45	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	4815	0	0
T1	728356	47	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	58	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	17	0	0
T41	0	12	0	0
T73	0	44	0	0
T121	0	64	0	0
T259	0	42	0	0
T263	0	72	0	0
T302	0	78	0	0
T303	0	46	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	5006	0	0
T1	728356	51	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	57	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	5	0	0
T41	0	13	0	0
T73	0	21	0	0
T121	0	62	0	0
T259	0	63	0	0
T263	0	56	0	0
T302	0	63	0	0
T303	0	50	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	4792	0	0
T1	728356	41	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	62	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T28	0	6	0	0
T41	0	2	0	0
T73	0	27	0	0
T121	0	62	0	0
T259	0	52	0	0
T263	0	66	0	0
T302	0	69	0	0
T303	0	31	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	2457	0	0
T1	728356	14	0	0
T2	346572	0	0	0
T3	222093	0	0	0
T14	931927	10	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T18	354121	0	0	0
T19	193276	0	0	0
T20	43817	0	0	0
T29	0	6	0	0
T48	0	5	0	0
T73	0	8	0	0
T96	0	4	0	0
T121	0	28	0	0
T259	0	11	0	0
T302	0	64	0	0
T316	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	2226	0	0
T28	108560	12	0	0
T36	0	15	0	0
T41	0	12	0	0
T75	0	57	0	0
T107	0	17	0	0
T218	0	58	0	0
T250	0	6	0	0
T263	736464	0	0	0
T274	0	5	0	0
T304	0	5	0	0
T305	0	13	0	0
T308	198382	0	0	0
T309	208222	0	0	0
T310	63320	0	0	0
T311	120942	0	0	0
T312	15335	0	0	0
T313	202818	0	0	0
T314	69244	0	0	0
T315	65562	0	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	4787	0	0
T28	0	15	0	0
T36	0	7	0	0
T38	227150	0	0	0
T39	313642	0	0	0
T41	0	9	0	0
T42	279659	2	0	0
T67	56772	0	0	0
T74	769451	0	0	0
T75	0	29	0	0
T82	0	90	0	0
T85	0	3	0	0
T88	0	3	0	0
T110	251089	0	0	0
T111	91218	0	0	0
T112	46823	0	0	0
T121	296665	0	0	0
T166	0	3	0	0
T211	105776	0	0	0
T218	0	21	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	1671	0	0
T28	108560	13	0	0
T36	0	2	0	0
T41	0	10	0	0
T75	0	44	0	0
T218	0	23	0	0
T250	0	26	0	0
T263	736464	0	0	0
T304	0	10	0	0
T305	0	8	0	0
T306	0	16	0	0
T307	0	13	0	0
T308	198382	0	0	0
T309	208222	0	0	0
T310	63320	0	0	0
T311	120942	0	0	0
T312	15335	0	0	0
T313	202818	0	0	0
T314	69244	0	0	0
T315	65562	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	6288	0	0
T8	902215	0	0	0
T9	104283	0	0	0
T10	822191	0	0	0
T11	301431	0	0	0
T28	0	133	0	0
T29	124194	78	0	0
T36	0	111	0	0
T41	0	9	0	0
T46	160783	0	0	0
T52	195867	0	0	0
T53	64663	0	0	0
T54	196767	0	0	0
T67	0	60	0	0
T68	0	59	0	0
T69	0	59	0	0
T70	240951	0	0	0
T75	0	25	0	0
T119	0	32	0	0
T150	0	33	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	6893	0	0
T1	728356	0	0	0
T2	346572	0	0	0
T5	128418	14	0	0
T6	76525	0	0	0
T14	931927	0	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T21	19020	0	0	0
T22	60776	0	0	0
T28	0	11	0	0
T36	0	38	0	0
T41	0	64	0	0
T61	0	77	0	0
T70	0	63	0	0
T131	0	41	0	0
T213	0	50	0	0
T216	0	64	0	0
T317	0	71	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	5299	0	0
T1	728356	0	0	0
T2	346572	0	0	0
T5	128418	14	0	0
T6	76525	0	0	0
T14	931927	0	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T21	19020	0	0	0
T22	60776	0	0	0
T28	0	8	0	0
T36	0	50	0	0
T41	0	80	0	0
T61	0	80	0	0
T70	0	78	0	0
T131	0	50	0	0
T213	0	75	0	0
T216	0	66	0	0
T317	0	59	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	5131	0	0
T1	728356	0	0	0
T2	346572	0	0	0
T5	128418	43	0	0
T6	76525	0	0	0
T14	931927	0	0	0
T15	449963	0	0	0
T16	18342	0	0	0
T17	413681	0	0	0
T21	19020	0	0	0
T22	60776	0	0	0
T28	0	20	0	0
T36	0	64	0	0
T41	0	99	0	0
T61	0	55	0	0
T70	0	67	0	0
T131	0	39	0	0
T213	0	78	0	0
T216	0	58	0	0
T317	0	84	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	1986	0	0
T28	108560	9	0	0
T36	0	8	0	0
T41	0	6	0	0
T75	0	24	0	0
T218	0	20	0	0
T250	0	15	0	0
T263	736464	0	0	0
T304	0	10	0	0
T305	0	12	0	0
T306	0	26	0	0
T307	0	17	0	0
T308	198382	0	0	0
T309	208222	0	0	0
T310	63320	0	0	0
T311	120942	0	0	0
T312	15335	0	0	0
T313	202818	0	0	0
T314	69244	0	0	0
T315	65562	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	1709	0	0
T28	0	18	0	0
T36	0	13	0	0
T38	227150	0	0	0
T41	0	8	0	0
T42	279659	0	0	0
T57	97616	5	0	0
T66	30229	0	0	0
T73	473123	0	0	0
T75	0	29	0	0
T78	0	1	0	0
T79	0	6	0	0
T80	933239	0	0	0
T96	110126	0	0	0
T110	251089	0	0	0
T111	91218	0	0	0
T112	46823	0	0	0
T157	0	7	0	0
T218	0	19	0	0
T318	0	5	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	1720	0	0
T28	108560	7	0	0
T36	0	23	0	0
T41	0	19	0	0
T75	0	31	0	0
T79	0	14	0	0
T138	0	6	0	0
T157	0	7	0	0
T218	0	42	0	0
T263	736464	0	0	0
T304	0	15	0	0
T308	198382	0	0	0
T309	208222	0	0	0
T310	63320	0	0	0
T311	120942	0	0	0
T312	15335	0	0	0
T313	202818	0	0	0
T314	69244	0	0	0
T315	65562	0	0	0
T318	0	1	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	1716	0	0
T28	0	6	0	0
T36	0	5	0	0
T38	227150	0	0	0
T41	0	13	0	0
T42	279659	0	0	0
T57	97616	6	0	0
T66	30229	0	0	0
T73	473123	0	0	0
T75	0	36	0	0
T79	0	9	0	0
T80	933239	0	0	0
T96	110126	0	0	0
T107	0	2	0	0
T110	251089	0	0	0
T111	91218	0	0	0
T112	46823	0	0	0
T138	0	9	0	0
T218	0	18	0	0
T304	0	7	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1307941163	1732	0	0
T28	108560	21	0	0
T36	0	24	0	0
T41	0	19	0	0
T75	0	28	0	0
T78	0	2	0	0
T79	0	7	0	0
T138	0	6	0	0
T218	0	27	0	0
T263	736464	0	0	0
T304	0	13	0	0
T308	198382	0	0	0
T309	208222	0	0	0
T310	63320	0	0	0
T311	120942	0	0	0
T312	15335	0	0	0
T313	202818	0	0	0
T314	69244	0	0	0
T315	65562	0	0	0
T318	0	7	0	0