Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl_autoblock
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_autoblock 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sysrst_ctrl_autoblock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.89 100.00 94.44 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sysrst_ctrl_detect 98.10 100.00 90.48 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl_autoblock
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
50 1 1
51 1 1
53 1 1
55 1 1


Cond Coverage for Module : sysrst_ctrl_autoblock
TotalCoveredPercent
Conditions1515100.00
Logical1515100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key0_out_sel.q) ? aon_auto_block_out_ctl_i.key0_out_value.q : key0_int_i)
             -----------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T18,T3

 LINE       51
 SUB-EXPRESSION (aon_ab_cond_met & aon_auto_block_out_ctl_i.key0_out_sel.q)
                 -------1-------   -------------------2-------------------
-1--2-StatusTests
01CoveredT6,T18,T3
10CoveredT6,T18,T46
11CoveredT6,T18,T3

 LINE       53
 EXPRESSION ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key1_out_sel.q) ? aon_auto_block_out_ctl_i.key1_out_value.q : key1_int_i)
             -----------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T3,T46

 LINE       53
 SUB-EXPRESSION (aon_ab_cond_met & aon_auto_block_out_ctl_i.key1_out_sel.q)
                 -------1-------   -------------------2-------------------
-1--2-StatusTests
01CoveredT6,T3,T46
10CoveredT6,T18,T39
11CoveredT6,T3,T46

 LINE       55
 EXPRESSION ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key2_out_sel.q) ? aon_auto_block_out_ctl_i.key2_out_value.q : key2_int_i)
             -----------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT46,T39,T49

 LINE       55
 SUB-EXPRESSION (aon_ab_cond_met & aon_auto_block_out_ctl_i.key2_out_sel.q)
                 -------1-------   -------------------2-------------------
-1--2-StatusTests
01CoveredT6,T46,T47
10CoveredT6,T18,T3
11CoveredT46,T39,T49

Branch Coverage for Module : sysrst_ctrl_autoblock
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 51 2 2 100.00
TERNARY 53 2 2 100.00
TERNARY 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key0_out_sel.q)) ?

Branches:
-1-StatusTests
1 Covered T6,T18,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 53 ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key1_out_sel.q)) ?

Branches:
-1-StatusTests
1 Covered T6,T3,T46
0 Covered T4,T5,T6


LineNo. Expression -1-: 55 ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key2_out_sel.q)) ?

Branches:
-1-StatusTests
1 Covered T46,T39,T49
0 Covered T4,T5,T6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%