Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2261

1

T17

16

T3

26

T10

23

auto[1]

677

1

T3

10

T10

1

T35

9

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2074

1

T17

16

T3

29

T10

20

auto[1]

864

1

T3

7

T10

4

T51

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2259

1

T17

16

T3

21

T10

17

auto[1]

679

1

T3

15

T10

7

T51

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2170

1

T17

12

T3

36

T10

18

auto[1]

768

1

T17

4

T10

6

T51

10

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2605

1

T17

12

T3

36

T10

14

auto[1]

333

1

T17

4

T10

10

T38

6

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2689

1

T17

16

T3

34

T10

23

auto[1]

249

1

T3

2

T10

1

T35

9

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2589

1

T17

16

T3

36

T10

24

auto[1]

349

1

T35

3

T38

3

T36

8

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2728

1

T17

16

T3

26

T10

20

auto[1]

210

1

T3

10

T10

4

T38

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2682

1

T17

16

T3

27

T10

23

auto[1]

256

1

T3

9

T10

1

T35

12

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2116

1

T17

12

T3

36

T10

18

auto[1]

822

1

T17

4

T10

6

T35

9

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	1045	1			T51	11		T40	3		T83	4
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	78	1			T17	4		T10	6		T36	6
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	91	1			T3	4		T35	6		T38	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	26	1			T38	2		T382	15		T389	7
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	70	1			T3	6		T390	7		T391	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	16	1			T10	4		T37	8		T268	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	18	1			T82	3		T98	1		T392	4
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T39	1		T86	1		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	124	1			T35	2		T82	3		T267	12
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	101	1			T222	30		T197	5		T393	6
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	29	1			T36	8		T255	4		T394	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	7	1			T39	3		T255	3		T390	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	22	1			T267	4		T255	1		T103	10
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	5	1			T38	2		T37	3		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T391	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	91	1			T35	5		T38	1		T36	7
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	35	1			T277	6		T197	6		T347	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	18	1			T10	1		T395	2		T277	6
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	8	1			T377	2		T343	6		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	20	1			T377	7		T396	3		T352	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	9	1			T37	5		T377	4		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	2	1			T3	1		T267	1		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T37	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	11	1			T227	4		T397	7		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	10	1			T222	10		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	6	1			T398	1		T383	2		T399	3
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T39	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

56

1

T3

1

T39

1

T382

17

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

169

1

T267

14

T160

12

T221

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

74

1

T38

1

T36

7

T83

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

112

1

T51

10

T80

13

T114

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

78

1

T35

2

T152

5

T374

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

70

1

T17

4

T35

5

T80

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T227

2

T395

3

T302

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

120

1

T37

2

T39

1

T158

13

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

84

1

T3

6

T10

1

T267

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T37

5

T276

2

T375

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T276

1

T236

3

T302

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

54

1

T148

5

T157

5

T373

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

38

1

T152

5

T141

3

T400

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

55

1

T10

6

T80

1

T157

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T275

1

T221

2

T121

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

178

1

T10

4

T38

2

T36

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

95

1

T41

3

T69

6

T382

17

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

140

1

T37

3

T74

1

T158

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

38

1

T114

1

T50

2

T148

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

130

1

T35

3

T39

3

T276

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T82

3

T382

17

T89

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

22

1

T36

6

T276

2

T158

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T48

1

T375

2

T374

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

64

1

T3

4

T51

1

T38

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T35

3

T275

2

T285

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

16

1

T40

3

T102

2

T141

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T48

1

T160

6

T374

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

29

1

T36

8

T114

3

T165

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T38

3

T48

2

T380

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T302

3

T401

1

T351

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T375

1

T106

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded