Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T6

11

T27

7

T75

10

auto[1]

1016

1

T6

9

T27

13

T75

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

511

1

T6

5

T27

4

T75

5

from_0to1

498

1

T6

4

T27

3

T75

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T6

13

T27

10

T75

10

auto[1]

1028

1

T6

7

T27

10

T75

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1044

1

T6

13

T27

12

T75

10

auto[1]

1056

1

T6

7

T27

8

T75

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T6

2

T75

1

T76

1

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T75

1

T76

1

T77

2

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T75

1

T76

1

T313

2

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T76

1

T313

1

T41

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T6

2

T76

1

T77

2

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T75

1

T41

1

T117

2

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T77

3

T313

1

T41

3

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T6

1

T77

1

T79

2

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T6

1

T76

1

T77

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T6

1

T27

1

T75

1

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T27

3

T41

4

T139

2

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T6

1

T75

1

T77

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T6

1

T27

1

T76

2

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T27

1

T76

1

T79

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T27

1

T75

3

T313

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T76

1

T79

1

T41

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1052

1

T6

9

T27

11

T75

14

auto[1]

1048

1

T6

11

T27

9

T75

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

487

1

T6

6

T27

6

T75

5

from_0to1

488

1

T6

6

T27

5

T75

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T6

9

T27

15

T75

8

auto[1]

1065

1

T6

11

T27

5

T75

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T6

9

T27

6

T75

14

auto[1]

1070

1

T6

11

T27

14

T75

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T75

1

T76

1

T77

2

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T6

2

T79

2

T41

2

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T6

1

T75

2

T77

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T6

1

T27

2

T76

2

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T27

1

T75

1

T41

2

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T27

2

T75

3

T77

1

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T6

1

T77

1

T50

3

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T27

1

T76

1

T41

5

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T6

1

T27

1

T79

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T27

1

T76

1

T77

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T6

1

T27

2

T75

2

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T77

1

T41

1

T117

1

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T76

1

T77

1

T79

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T6

3

T27

1

T75

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T6

2

T76

2

T79

2

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T75

1

T76

1

T79

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1052

1

T6

10

T27

12

T75

7

auto[1]

1048

1

T6

10

T27

8

T75

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

513

1

T6

6

T27

5

T75

5

from_0to1

516

1

T6

6

T27

6

T75

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1060

1

T6

10

T27

11

T75

11

auto[1]

1040

1

T6

10

T27

9

T75

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1044

1

T6

12

T27

7

T75

8

auto[1]

1056

1

T6

8

T27

13

T75

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T75

1

T76

2

T79

2

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T6

1

T27

1

T75

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T77

1

T313

1

T50

7

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T6

1

T75

2

T76

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T6

2

T27

1

T75

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T27

2

T77

2

T79

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T27

1

T79

2

T313

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T6

1

T27

1

T75

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T6

1

T76

2

T41

5

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T6

1

T27

2

T313

1

auto[1]

from_1to0

auto[1]

auto[0]

76

1

T6

2

T27

1

T75

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T27

1

T77

1

T313

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T75

2

T76

3

T313

1

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T6

2

T27

1

T76

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T6

1

T76

1

T77

1

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T75

2

T77

1

T313

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1023

1

T6

10

T27

9

T75

9

auto[1]

1077

1

T6

10

T27

11

T75

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

490

1

T6

4

T27

3

T75

3

from_0to1

499

1

T6

5

T27

3

T75

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1080

1

T6

11

T27

6

T75

10

auto[1]

1020

1

T6

9

T27

14

T75

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1048

1

T6

9

T27

15

T75

10

auto[1]

1052

1

T6

11

T27

5

T75

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T6

1

T27

1

T75

2

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T76

1

T77

1

T41

2

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T27

1

T77

3

T313

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T6

1

T79

1

T41

2

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T27

1

T75

1

T76

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T6

1

T76

1

T77

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T6

2

T27

1

T76

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T41

1

T140

1

T50

5

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T75

1

T76

1

T79

1

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T313

1

T41

3

T117

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T6

2

T27

1

T76

2

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T79

1

T41

1

T117

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T27

1

T79

1

T313

2

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T6

2

T75

1

T77

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T75

1

T76

1

T77

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T77

3

T313

1

T41

5

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1083

1

T6

13

T27

11

T75

11

auto[1]

1017

1

T6

7

T27

9

T75

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

516

1

T6

6

T27

6

T75

4

from_0to1

520

1

T6

7

T27

6

T75

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1007

1

T6

8

T27

12

T75

10

auto[1]

1093

1

T6

12

T27

8

T75

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T6

10

T27

9

T75

12

auto[1]

1004

1

T6

10

T27

11

T75

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T27

1

T75

1

T76

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T6

1

T27

1

T77

2

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T6

1

T76

1

T41

2

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T6

1

T27

1

T75

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T27

1

T77

2

T313

1

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T6

1

T79

1

T41

4

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T6

3

T27

1

T75

2

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T6

2

T27

1

T76

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T6

1

T27

1

T75

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T6

1

T27

1

T75

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T27

1

T313

1

T117

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T6

1

T77

1

T41

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T75

1

T76

1

T77

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T27

1

T41

3

T117

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T6

1

T77

1

T313

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T27

2

T79

1

T41

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1020

1

T6

11

T27

12

T75

10

auto[1]

1080

1

T6

9

T27

8

T75

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

499

1

T6

6

T27

5

T75

5

from_0to1

504

1

T6

6

T27

4

T75

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T6

12

T27

7

T75

15

auto[1]

1047

1

T6

8

T27

13

T75

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1043

1

T6

11

T27

9

T75

3

auto[1]

1057

1

T6

9

T27

11

T75

17

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T6

2

T75

1

T77

2

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T27

1

T76

1

T77

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T6

1

T27

1

T76

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T27

1

T75

1

T76

1

auto[0]

from_0to1

auto[0]

auto[0]

77

1

T75

1

T77

1

T41

1

auto[0]

from_0to1

auto[0]

auto[1]

47

1

T6

1

T75

2

T41

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T6

1

T77

1

T41

3

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T27

1

T75

2

T76

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T6

3

T313

1

T117

3

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T27

1

T75

3

T79

1

auto[1]

from_1to0

auto[1]

auto[0]

45

1

T76

1

T77

1

T41

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T27

1

T76

1

T79

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T6

1

T79

1

T41

2

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T6

1

T27

1

T313

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T27

2

T76

1

T77

1

auto[1]

from_0to1

auto[1]

auto[1]

77

1

T6

2

T76

2

T79

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T6

10

T27

10

T75

9

auto[1]

1068

1

T6

10

T27

10

T75

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

498

1

T6

6

T27

3

T75

5

from_0to1

493

1

T6

6

T27

2

T75

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041

1

T6

9

T27

7

T75

10

auto[1]

1059

1

T6

11

T27

13

T75

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T6

11

T27

9

T75

12

auto[1]

1049

1

T6

9

T27

11

T75

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T6

2

T76

3

T79

2

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T76

1

T77

1

T79

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T6

1

T75

1

T76

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T6

2

T27

1

T75

1

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T6

1

T27

1

T76

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T6

1

T76

1

T77

2

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T75

2

T313

1

T41

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T79

1

T41

1

T117

1

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T77

1

T313

1

T41

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T6

1

T75

1

T313

2

auto[1]

from_1to0

auto[1]

auto[0]

49

1

T27

1

T75

2

T41

2

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T27

1

T313

1

T41

2

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T6

2

T75

1

T77

2

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T75

1

T76

2

T79

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T6

1

T27

1

T75

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T6

1

T313

1

T41

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1036

1

T6

14

T27

11

T75

13

auto[1]

1064

1

T6

6

T27

9

T75

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

520

1

T6

4

T27

4

T75

4

from_0to1

515

1

T6

3

T27

5

T75

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1082

1

T6

12

T27

12

T75

11

auto[1]

1018

1

T6

8

T27

8

T75

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1078

1

T6

5

T27

10

T75

10

auto[1]

1022

1

T6

15

T27

10

T75

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T75

1

T76

1

T77

2

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T6

2

T27

1

T76

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T6

1

T27

1

T76

1

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T77

1

T117

1

T50

5

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T27

3

T75

2

T76

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T6

1

T27

1

T77

1

auto[0]

from_0to1

auto[1]

auto[0]

75

1

T75

1

T77

1

T313

1

auto[0]

from_0to1

auto[1]

auto[1]

49

1

T6

1

T75

1

T76

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T76

2

T77

1

T41

3

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T75

2

T313

1

T41

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T27

1

T75

1

T77

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T6

1

T27

1

T77

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T77

1

T313

1

T41

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T6

1

T27

1

T75

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T76

1

T313

1

T41

2

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T76

1

T77

2

T79

1