Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151083	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118112

1

T5

23

T6

51

T7

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136136	1			T5	22		T6	62		T7	2
values[0x0]	65967	1			T5	16		T6	35		T1	5
values[0x1]	67092	1			T5	6		T6	26		T7	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	122775	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

146420

1

T5

26

T6

58

T7

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	780	1			T3	4		T10	2		T35	3
valid_sources[0x01]	1352	1			T3	4		T27	6		T10	6
valid_sources[0x02]	1638	1			T18	1		T3	6		T4	1
valid_sources[0x03]	860	1			T6	1		T19	5		T3	2
valid_sources[0x04]	825	1			T6	4		T3	6		T9	2
valid_sources[0x05]	764	1			T3	4		T25	1		T27	1
valid_sources[0x06]	856	1			T6	1		T3	5		T25	1
valid_sources[0x07]	906	1			T6	1		T3	6		T27	1
valid_sources[0x08]	738	1			T3	4		T10	5		T35	8
valid_sources[0x09]	834	1			T3	5		T10	9		T35	4
valid_sources[0x0a]	750	1			T20	1		T3	4		T65	2
valid_sources[0x0b]	906	1			T3	2		T27	1		T10	2
valid_sources[0x0c]	812	1			T3	5		T4	1		T10	5
valid_sources[0x0d]	788	1			T3	4		T27	2		T10	1
valid_sources[0x0e]	1675	1			T3	1		T4	1		T10	2
valid_sources[0x0f]	759	1			T6	2		T3	5		T10	5
valid_sources[0x10]	885	1			T6	1		T3	1		T10	4
valid_sources[0x11]	808	1			T3	5		T4	1		T10	2
valid_sources[0x12]	997	1			T3	11		T10	2		T35	6
valid_sources[0x13]	1775	1			T3	3		T10	7		T35	2
valid_sources[0x14]	729	1			T6	1		T3	10		T25	1
valid_sources[0x15]	1311	1			T3	3		T10	5		T35	7
valid_sources[0x16]	1006	1			T6	1		T3	5		T10	6
valid_sources[0x17]	621	1			T3	4		T10	6		T35	1
valid_sources[0x18]	776	1			T3	4		T10	2		T76	1
valid_sources[0x19]	1366	1			T6	2		T3	6		T10	1
valid_sources[0x1a]	2272	1			T3	5		T9	6		T10	8
valid_sources[0x1b]	1148	1			T6	1		T3	4		T10	3
valid_sources[0x1c]	862	1			T6	1		T3	6		T27	1
valid_sources[0x1d]	859	1			T3	10		T10	6		T61	1
valid_sources[0x1e]	1459	1			T3	3		T10	8		T35	5
valid_sources[0x1f]	968	1			T6	1		T3	4		T9	5
valid_sources[0x20]	671	1			T3	4		T30	16		T10	1
valid_sources[0x21]	761	1			T6	1		T3	4		T35	6
valid_sources[0x22]	839	1			T3	3		T27	2		T10	8
valid_sources[0x23]	857	1			T3	5		T10	1		T76	2
valid_sources[0x24]	931	1			T6	2		T16	2		T3	6
valid_sources[0x25]	1131	1			T3	3		T10	5		T12	1
valid_sources[0x26]	1520	1			T3	3		T27	4		T10	3
valid_sources[0x27]	747	1			T3	4		T10	3		T35	3
valid_sources[0x28]	788	1			T6	2		T3	4		T25	1
valid_sources[0x29]	2535	1			T3	7		T10	2		T31	1
valid_sources[0x2a]	794	1			T3	2		T9	1		T10	3
valid_sources[0x2b]	818	1			T3	4		T10	4		T76	1
valid_sources[0x2c]	824	1			T3	6		T10	1		T35	2
valid_sources[0x2d]	1228	1			T3	9		T27	1		T10	8
valid_sources[0x2e]	1631	1			T3	4		T9	4		T10	3
valid_sources[0x2f]	800	1			T3	5		T10	2		T134	4
valid_sources[0x30]	1623	1			T3	3		T10	1		T35	1
valid_sources[0x31]	1045	1			T3	3		T27	1		T10	3
valid_sources[0x32]	1060	1			T6	1		T3	2		T10	2
valid_sources[0x33]	809	1			T3	7		T10	5		T35	7
valid_sources[0x34]	1831	1			T6	1		T3	6		T10	8
valid_sources[0x35]	872	1			T3	6		T4	1		T10	7
valid_sources[0x36]	710	1			T3	4		T9	4		T10	1
valid_sources[0x37]	972	1			T3	4		T27	1		T10	4
valid_sources[0x38]	827	1			T3	3		T27	1		T10	4
valid_sources[0x39]	1041	1			T3	5		T9	1		T10	1
valid_sources[0x3a]	813	1			T3	7		T10	1		T35	4
valid_sources[0x3b]	2306	1			T3	2		T27	1		T10	6
valid_sources[0x3c]	955	1			T16	1		T18	2		T3	2
valid_sources[0x3d]	3135	1			T18	1		T3	3		T10	10
valid_sources[0x3e]	937	1			T3	2		T10	3		T28	2
valid_sources[0x3f]	1083	1			T3	5		T27	1		T10	4
valid_sources[0x40]	788	1			T3	2		T4	1		T10	5
valid_sources[0x41]	912	1			T6	2		T3	7		T10	2
valid_sources[0x42]	1158	1			T3	2		T27	3		T31	1
valid_sources[0x43]	1323	1			T6	4		T15	1		T3	7
valid_sources[0x44]	3007	1			T17	968		T3	3		T10	10
valid_sources[0x45]	810	1			T3	3		T27	2		T10	4
valid_sources[0x46]	792	1			T3	7		T64	4		T27	1
valid_sources[0x47]	816	1			T6	2		T3	3		T27	1
valid_sources[0x48]	822	1			T3	4		T10	2		T76	2
valid_sources[0x49]	1446	1			T3	6		T10	5		T28	7
valid_sources[0x4a]	767	1			T5	44		T6	1		T3	5
valid_sources[0x4b]	1876	1			T3	1		T27	1		T10	4
valid_sources[0x4c]	738	1			T6	1		T3	8		T10	8
valid_sources[0x4d]	774	1			T6	1		T3	6		T10	3
valid_sources[0x4e]	739	1			T2	23		T3	2		T10	6
valid_sources[0x4f]	1083	1			T6	5		T3	7		T10	4
valid_sources[0x50]	1616	1			T16	1		T3	6		T10	7
valid_sources[0x51]	693	1			T3	3		T10	5		T35	3
valid_sources[0x52]	1842	1			T6	2		T3	3		T27	2
valid_sources[0x53]	803	1			T6	1		T20	1		T3	5
valid_sources[0x54]	939	1			T6	1		T3	5		T10	5
valid_sources[0x55]	767	1			T16	1		T10	7		T32	1
valid_sources[0x56]	1046	1			T6	2		T3	4		T10	3
valid_sources[0x57]	705	1			T6	1		T3	4		T27	1
valid_sources[0x58]	977	1			T3	6		T27	1		T10	5
valid_sources[0x59]	754	1			T6	1		T3	6		T9	8
valid_sources[0x5a]	885	1			T3	3		T27	1		T10	2
valid_sources[0x5b]	1214	1			T3	6		T35	7		T38	2
valid_sources[0x5c]	1109	1			T6	1		T3	2		T10	10
valid_sources[0x5d]	2187	1			T16	1		T3	7		T10	5
valid_sources[0x5e]	1009	1			T6	1		T3	3		T10	3
valid_sources[0x5f]	1019	1			T3	5		T27	2		T10	1
valid_sources[0x60]	1070	1			T3	8		T10	4		T35	3
valid_sources[0x61]	669	1			T3	6		T27	2		T10	3
valid_sources[0x62]	754	1			T6	1		T3	3		T10	5
valid_sources[0x63]	1166	1			T15	2		T3	2		T64	2
valid_sources[0x64]	725	1			T10	3		T35	6		T38	2
valid_sources[0x65]	1987	1			T18	1		T3	2		T10	4
valid_sources[0x66]	722	1			T6	1		T3	2		T10	3
valid_sources[0x67]	936	1			T6	1		T3	2		T10	3
valid_sources[0x68]	881	1			T6	1		T3	6		T9	3
valid_sources[0x69]	829	1			T3	9		T10	7		T134	1
valid_sources[0x6a]	793	1			T6	1		T3	3		T27	3
valid_sources[0x6b]	1814	1			T15	1		T3	9		T10	4
valid_sources[0x6c]	953	1			T6	2		T3	9		T10	5
valid_sources[0x6d]	1939	1			T3	5		T10	2		T72	1
valid_sources[0x6e]	975	1			T6	1		T3	2		T10	3
valid_sources[0x6f]	939	1			T16	1		T3	1		T4	1
valid_sources[0x70]	1003	1			T3	3		T10	5		T12	1
valid_sources[0x71]	685	1			T14	1		T3	2		T10	7
valid_sources[0x72]	1470	1			T6	3		T3	4		T10	10
valid_sources[0x73]	829	1			T18	1		T3	5		T10	4
valid_sources[0x74]	831	1			T6	2		T3	2		T10	3
valid_sources[0x75]	858	1			T3	5		T10	8		T28	4
valid_sources[0x76]	842	1			T3	7		T25	6		T27	1
valid_sources[0x77]	1282	1			T6	2		T3	5		T10	4
valid_sources[0x78]	788	1			T3	3		T25	8		T10	4
valid_sources[0x79]	838	1			T6	1		T3	3		T25	1
valid_sources[0x7a]	929	1			T6	2		T3	3		T27	1
valid_sources[0x7b]	1625	1			T3	3		T10	2		T35	2
valid_sources[0x7c]	855	1			T3	3		T10	1		T76	1
valid_sources[0x7d]	790	1			T3	4		T10	2		T35	4
valid_sources[0x7e]	750	1			T3	4		T27	3		T10	3
valid_sources[0x7f]	694	1			T3	5		T10	2		T35	2
valid_sources[0x80]	1915	1			T3	1		T10	4		T35	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62611

1

T5

11

T6

28

T7

1

values[0x0]

all_enables

biggest_size

32412

1

T5

11

T6

16

T1

1

values[0x1]

all_enables

biggest_size

23089

1

T5

1

T6

7

T7

1