Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1118555906	10405	0	0
auto_block_debounce_ctl_rd_A	1118555906	2304	0	0
auto_block_out_ctl_rd_A	1118555906	2708	0	0
com_det_ctl_0_rd_A	1118555906	4379	0	0
com_det_ctl_1_rd_A	1118555906	4357	0	0
com_det_ctl_2_rd_A	1118555906	4518	0	0
com_det_ctl_3_rd_A	1118555906	4462	0	0
com_out_ctl_0_rd_A	1118555906	4844	0	0
com_out_ctl_1_rd_A	1118555906	4895	0	0
com_out_ctl_2_rd_A	1118555906	4762	0	0
com_out_ctl_3_rd_A	1118555906	4876	0	0
com_pre_det_ctl_0_rd_A	1118555906	1705	0	0
com_pre_det_ctl_1_rd_A	1118555906	1694	0	0
com_pre_det_ctl_2_rd_A	1118555906	1792	0	0
com_pre_det_ctl_3_rd_A	1118555906	1828	0	0
com_pre_sel_ctl_0_rd_A	1118555906	4932	0	0
com_pre_sel_ctl_1_rd_A	1118555906	5031	0	0
com_pre_sel_ctl_2_rd_A	1118555906	4957	0	0
com_pre_sel_ctl_3_rd_A	1118555906	4972	0	0
com_sel_ctl_0_rd_A	1118555906	5011	0	0
com_sel_ctl_1_rd_A	1118555906	5044	0	0
com_sel_ctl_2_rd_A	1118555906	5061	0	0
com_sel_ctl_3_rd_A	1118555906	4871	0	0
ec_rst_ctl_rd_A	1118555906	3238	0	0
intr_enable_rd_A	1118555906	2522	0	0
key_intr_ctl_rd_A	1118555906	3723	0	0
key_intr_debounce_ctl_rd_A	1118555906	1637	0	0
key_invert_ctl_rd_A	1118555906	5020	0	0
pin_allowed_ctl_rd_A	1118555906	5656	0	0
pin_out_ctl_rd_A	1118555906	4571	0	0
pin_out_value_rd_A	1118555906	4736	0	0
regwen_rd_A	1118555906	2116	0	0
ulp_ac_debounce_ctl_rd_A	1118555906	1816	0	0
ulp_ctl_rd_A	1118555906	1930	0	0
ulp_lid_debounce_ctl_rd_A	1118555906	1873	0	0
ulp_pwrb_debounce_ctl_rd_A	1118555906	1961	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	10405	0	0
T41	146515	7	0	0
T50	0	26	0	0
T55	111063	0	0	0
T56	149830	8	0	0
T70	0	9	0	0
T74	0	4	0	0
T84	0	3	0	0
T112	51002	0	0	0
T113	64816	0	0	0
T114	133279	0	0	0
T115	386509	0	0	0
T116	37902	0	0	0
T117	33194	0	0	0
T118	374399	0	0	0
T133	0	7	0	0
T182	0	13	0	0
T192	0	12	0	0
T299	0	2	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	2304	0	0
T12	244583	0	0	0
T13	30756	0	0	0
T26	235775	0	0	0
T31	916943	6	0	0
T32	0	12	0	0
T51	672268	0	0	0
T52	0	9	0	0
T57	0	14	0	0
T74	0	1	0	0
T75	241284	0	0	0
T76	235877	0	0	0
T77	236213	0	0	0
T84	0	18	0	0
T128	97129	0	0	0
T134	58196	0	0	0
T192	0	22	0	0
T300	0	10	0	0
T301	0	18	0	0
T302	0	26	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	2708	0	0
T12	244583	0	0	0
T13	30756	0	0	0
T26	235775	0	0	0
T31	916943	12	0	0
T32	0	6	0	0
T51	672268	0	0	0
T52	0	12	0	0
T57	0	7	0	0
T74	0	3	0	0
T75	241284	0	0	0
T76	235877	0	0	0
T77	236213	0	0	0
T84	0	8	0	0
T128	97129	0	0	0
T134	58196	0	0	0
T192	0	21	0	0
T300	0	20	0	0
T301	0	14	0	0
T302	0	10	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	4379	0	0
T24	56083	0	0	0
T35	589835	13	0	0
T37	0	39	0	0
T38	173301	0	0	0
T40	0	52	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	44	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	23	0	0
T78	250741	0	0	0
T114	0	66	0	0
T158	0	92	0	0
T181	206643	0	0	0
T222	0	104	0	0
T267	0	93	0	0
T276	0	85	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	4357	0	0
T24	56083	0	0	0
T35	589835	36	0	0
T37	0	36	0	0
T38	173301	0	0	0
T40	0	39	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	44	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	18	0	0
T78	250741	0	0	0
T114	0	94	0	0
T158	0	64	0	0
T181	206643	0	0	0
T222	0	120	0	0
T267	0	59	0	0
T276	0	63	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	4518	0	0
T24	56083	0	0	0
T35	589835	26	0	0
T37	0	32	0	0
T38	173301	0	0	0
T40	0	36	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	48	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	13	0	0
T78	250741	0	0	0
T114	0	84	0	0
T158	0	55	0	0
T181	206643	0	0	0
T222	0	104	0	0
T267	0	72	0	0
T276	0	72	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	4462	0	0
T24	56083	0	0	0
T35	589835	43	0	0
T37	0	67	0	0
T38	173301	0	0	0
T40	0	39	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	69	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	14	0	0
T78	250741	0	0	0
T114	0	66	0	0
T158	0	82	0	0
T181	206643	0	0	0
T222	0	130	0	0
T267	0	102	0	0
T276	0	78	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	4844	0	0
T24	56083	0	0	0
T35	589835	30	0	0
T37	0	38	0	0
T38	173301	0	0	0
T40	0	57	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	38	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	16	0	0
T78	250741	0	0	0
T114	0	90	0	0
T158	0	52	0	0
T181	206643	0	0	0
T222	0	119	0	0
T267	0	64	0	0
T276	0	71	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	4895	0	0
T24	56083	0	0	0
T35	589835	12	0	0
T37	0	42	0	0
T38	173301	0	0	0
T40	0	54	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	34	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	18	0	0
T78	250741	0	0	0
T114	0	80	0	0
T158	0	56	0	0
T181	206643	0	0	0
T222	0	112	0	0
T267	0	46	0	0
T276	0	60	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	4762	0	0
T24	56083	0	0	0
T35	589835	17	0	0
T37	0	56	0	0
T38	173301	0	0	0
T40	0	40	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	41	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	17	0	0
T78	250741	0	0	0
T114	0	71	0	0
T158	0	82	0	0
T181	206643	0	0	0
T222	0	108	0	0
T267	0	60	0	0
T276	0	82	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	4876	0	0
T24	56083	0	0	0
T35	589835	17	0	0
T37	0	39	0	0
T38	173301	0	0	0
T40	0	33	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	55	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	13	0	0
T78	250741	0	0	0
T114	0	70	0	0
T158	0	80	0	0
T181	206643	0	0	0
T222	0	116	0	0
T267	0	65	0	0
T276	0	66	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	1705	0	0
T68	18905	0	0	0
T69	174390	0	0	0
T74	152498	6	0	0
T84	0	19	0	0
T148	143433	0	0	0
T149	211340	0	0	0
T150	117023	0	0	0
T151	102301	0	0	0
T152	243332	0	0	0
T153	970147	0	0	0
T155	153563	0	0	0
T192	0	8	0	0
T194	0	8	0	0
T204	0	11	0	0
T261	0	38	0	0
T302	0	2	0	0
T303	0	7	0	0
T304	0	23	0	0
T305	0	29	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	1694	0	0
T68	18905	0	0	0
T69	174390	0	0	0
T74	152498	1	0	0
T84	0	11	0	0
T148	143433	0	0	0
T149	211340	0	0	0
T150	117023	0	0	0
T151	102301	0	0	0
T152	243332	0	0	0
T153	970147	0	0	0
T155	153563	0	0	0
T161	0	4	0	0
T192	0	19	0	0
T194	0	15	0	0
T204	0	11	0	0
T261	0	25	0	0
T302	0	2	0	0
T303	0	11	0	0
T304	0	18	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	1792	0	0
T68	18905	0	0	0
T69	174390	0	0	0
T74	152498	9	0	0
T148	143433	0	0	0
T149	211340	0	0	0
T150	117023	0	0	0
T151	102301	0	0	0
T152	243332	0	0	0
T153	970147	0	0	0
T155	153563	0	0	0
T161	0	5	0	0
T192	0	10	0	0
T194	0	16	0	0
T204	0	9	0	0
T261	0	52	0	0
T302	0	2	0	0
T303	0	8	0	0
T304	0	7	0	0
T305	0	23	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	1828	0	0
T84	236036	2	0	0
T99	554692	0	0	0
T129	240582	0	0	0
T161	0	11	0	0
T192	0	15	0	0
T194	0	17	0	0
T195	143300	0	0	0
T197	371664	0	0	0
T198	52405	0	0	0
T199	210974	0	0	0
T200	297184	0	0	0
T204	0	11	0	0
T255	814806	0	0	0
T256	250856	0	0	0
T261	0	40	0	0
T302	0	7	0	0
T303	0	5	0	0
T304	0	20	0	0
T305	0	18	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	4932	0	0
T24	56083	0	0	0
T35	589835	28	0	0
T37	0	45	0	0
T38	173301	0	0	0
T40	0	22	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	34	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	17	0	0
T78	250741	0	0	0
T114	0	73	0	0
T158	0	57	0	0
T181	206643	0	0	0
T222	0	135	0	0
T267	0	57	0	0
T276	0	63	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	5031	0	0
T24	56083	0	0	0
T35	589835	36	0	0
T37	0	38	0	0
T38	173301	0	0	0
T40	0	33	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	41	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	13	0	0
T78	250741	0	0	0
T114	0	71	0	0
T158	0	85	0	0
T181	206643	0	0	0
T222	0	114	0	0
T267	0	77	0	0
T276	0	63	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	4957	0	0
T24	56083	0	0	0
T35	589835	15	0	0
T37	0	27	0	0
T38	173301	0	0	0
T40	0	60	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	44	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	18	0	0
T78	250741	0	0	0
T114	0	72	0	0
T158	0	60	0	0
T181	206643	0	0	0
T222	0	137	0	0
T267	0	77	0	0
T276	0	58	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	4972	0	0
T24	56083	0	0	0
T35	589835	23	0	0
T37	0	45	0	0
T38	173301	0	0	0
T40	0	70	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	38	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	10	0	0
T78	250741	0	0	0
T114	0	65	0	0
T158	0	49	0	0
T181	206643	0	0	0
T222	0	108	0	0
T267	0	76	0	0
T276	0	71	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	5011	0	0
T24	56083	0	0	0
T35	589835	19	0	0
T37	0	39	0	0
T38	173301	0	0	0
T40	0	43	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	40	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	4	0	0
T78	250741	0	0	0
T114	0	67	0	0
T158	0	63	0	0
T181	206643	0	0	0
T222	0	114	0	0
T267	0	71	0	0
T276	0	77	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	5044	0	0
T24	56083	0	0	0
T35	589835	24	0	0
T37	0	52	0	0
T38	173301	0	0	0
T40	0	54	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	48	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	2	0	0
T78	250741	0	0	0
T114	0	65	0	0
T158	0	88	0	0
T181	206643	0	0	0
T222	0	107	0	0
T267	0	56	0	0
T276	0	51	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	5061	0	0
T24	56083	0	0	0
T35	589835	27	0	0
T37	0	69	0	0
T38	173301	0	0	0
T40	0	33	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	61	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	7	0	0
T78	250741	0	0	0
T114	0	82	0	0
T158	0	65	0	0
T181	206643	0	0	0
T222	0	115	0	0
T267	0	69	0	0
T276	0	70	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	4871	0	0
T24	56083	0	0	0
T35	589835	15	0	0
T37	0	48	0	0
T38	173301	0	0	0
T40	0	35	0	0
T45	297996	0	0	0
T46	355905	0	0	0
T48	0	33	0	0
T52	333022	0	0	0
T53	28946	0	0	0
T72	66374	0	0	0
T74	0	14	0	0
T78	250741	0	0	0
T114	0	66	0	0
T158	0	55	0	0
T181	206643	0	0	0
T222	0	102	0	0
T267	0	76	0	0
T276	0	78	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	3238	0	0
T2	389148	0	0	0
T3	495174	0	0	0
T14	116426	7	0	0
T15	77072	0	0	0
T16	201251	0	0	0
T17	160777	0	0	0
T18	52985	0	0	0
T19	102130	0	0	0
T20	188058	0	0	0
T25	59534	0	0	0
T37	0	11	0	0
T40	0	9	0	0
T48	0	9	0	0
T81	0	4	0	0
T114	0	41	0	0
T138	0	3	0	0
T264	0	4	0	0
T276	0	36	0	0
T306	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	2522	0	0
T68	18905	0	0	0
T69	174390	0	0	0
T74	152498	20	0	0
T84	0	16	0	0
T120	0	4	0	0
T148	143433	0	0	0
T149	211340	0	0	0
T150	117023	0	0	0
T151	102301	0	0	0
T152	243332	0	0	0
T153	970147	0	0	0
T155	153563	0	0	0
T161	0	7	0	0
T192	0	7	0	0
T194	0	10	0	0
T204	0	14	0	0
T302	0	27	0	0
T307	0	12	0	0
T308	0	6	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	3723	0	0
T68	18905	0	0	0
T69	174390	0	0	0
T74	152498	5	0	0
T84	0	4	0	0
T148	143433	0	0	0
T149	211340	0	0	0
T150	117023	0	0	0
T151	102301	0	0	0
T152	243332	0	0	0
T153	970147	0	0	0
T155	153563	0	0	0
T178	0	2	0	0
T179	0	6	0	0
T192	0	20	0	0
T194	0	19	0	0
T218	0	6	0	0
T246	0	5	0	0
T257	0	4	0	0
T302	0	3	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	1637	0	0
T68	18905	0	0	0
T69	174390	0	0	0
T74	152498	15	0	0
T84	0	16	0	0
T148	143433	0	0	0
T149	211340	0	0	0
T150	117023	0	0	0
T151	102301	0	0	0
T152	243332	0	0	0
T153	970147	0	0	0
T155	153563	0	0	0
T161	0	2	0	0
T192	0	2	0	0
T194	0	17	0	0
T204	0	21	0	0
T261	0	26	0	0
T302	0	3	0	0
T303	0	21	0	0
T304	0	25	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	5020	0	0
T13	30756	0	0	0
T26	235775	79	0	0
T42	24466	0	0	0
T44	128674	0	0	0
T71	20109	0	0	0
T74	0	60	0	0
T75	241284	0	0	0
T76	235877	0	0	0
T77	236213	0	0	0
T84	0	8	0	0
T134	58196	0	0	0
T142	0	41	0	0
T192	0	155	0	0
T226	0	58	0	0
T274	202924	0	0	0
T309	0	73	0	0
T310	0	35	0	0
T311	0	20	0	0
T312	0	84	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	5656	0	0
T32	394876	0	0	0
T35	589835	0	0	0
T42	24466	0	0	0
T44	128674	0	0	0
T71	20109	0	0	0
T72	66374	0	0	0
T74	0	8	0	0
T76	235877	43	0	0
T77	236213	0	0	0
T84	0	8	0	0
T117	0	78	0	0
T180	19345	0	0	0
T192	0	82	0	0
T256	0	75	0	0
T274	202924	0	0	0
T313	0	55	0	0
T314	0	58	0	0
T315	0	51	0	0
T316	0	21	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	4571	0	0
T32	394876	0	0	0
T35	589835	0	0	0
T42	24466	0	0	0
T44	128674	0	0	0
T71	20109	0	0	0
T72	66374	0	0	0
T74	0	10	0	0
T76	235877	36	0	0
T77	236213	0	0	0
T84	0	11	0	0
T117	0	92	0	0
T180	19345	0	0	0
T192	0	69	0	0
T256	0	46	0	0
T274	202924	0	0	0
T313	0	50	0	0
T314	0	90	0	0
T315	0	38	0	0
T316	0	50	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	4736	0	0
T32	394876	0	0	0
T35	589835	0	0	0
T42	24466	0	0	0
T44	128674	0	0	0
T71	20109	0	0	0
T72	66374	0	0	0
T74	0	10	0	0
T76	235877	43	0	0
T77	236213	0	0	0
T117	0	82	0	0
T180	19345	0	0	0
T192	0	88	0	0
T256	0	24	0	0
T274	202924	0	0	0
T313	0	58	0	0
T314	0	84	0	0
T315	0	33	0	0
T316	0	39	0	0
T317	0	59	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	2116	0	0
T68	18905	0	0	0
T69	174390	0	0	0
T74	152498	22	0	0
T84	0	2	0	0
T148	143433	0	0	0
T149	211340	0	0	0
T150	117023	0	0	0
T151	102301	0	0	0
T152	243332	0	0	0
T153	970147	0	0	0
T155	153563	0	0	0
T161	0	7	0	0
T192	0	10	0	0
T194	0	9	0	0
T204	0	5	0	0
T261	0	51	0	0
T302	0	4	0	0
T303	0	16	0	0
T304	0	11	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	1816	0	0
T11	225461	7	0	0
T12	244583	0	0	0
T26	235775	0	0	0
T31	916943	0	0	0
T51	672268	0	0	0
T60	42510	0	0	0
T61	211374	0	0	0
T74	0	10	0	0
T75	241284	0	0	0
T84	0	11	0	0
T128	97129	0	0	0
T134	58196	0	0	0
T142	0	8	0	0
T144	0	3	0	0
T192	0	13	0	0
T211	0	8	0	0
T219	0	6	0	0
T318	0	2	0	0
T319	0	5	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	1930	0	0
T11	225461	2	0	0
T12	244583	0	0	0
T26	235775	0	0	0
T31	916943	0	0	0
T51	672268	0	0	0
T60	42510	0	0	0
T61	211374	0	0	0
T74	0	12	0	0
T75	241284	0	0	0
T84	0	4	0	0
T128	97129	0	0	0
T134	58196	0	0	0
T142	0	2	0	0
T192	0	8	0	0
T211	0	18	0	0
T219	0	11	0	0
T302	0	3	0	0
T318	0	3	0	0
T320	0	6	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	1873	0	0
T11	225461	1	0	0
T12	244583	0	0	0
T26	235775	0	0	0
T31	916943	0	0	0
T51	672268	0	0	0
T60	42510	0	0	0
T61	211374	0	0	0
T74	0	12	0	0
T75	241284	0	0	0
T84	0	10	0	0
T128	97129	0	0	0
T134	58196	0	0	0
T192	0	5	0	0
T211	0	6	0	0
T219	0	6	0	0
T318	0	4	0	0
T319	0	2	0	0
T320	0	11	0	0
T321	0	7	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118555906	1961	0	0
T11	225461	8	0	0
T12	244583	0	0	0
T26	235775	0	0	0
T31	916943	0	0	0
T51	672268	0	0	0
T60	42510	0	0	0
T61	211374	0	0	0
T74	0	5	0	0
T75	241284	0	0	0
T84	0	6	0	0
T128	97129	0	0	0
T134	58196	0	0	0
T142	0	6	0	0
T144	0	1	0	0
T192	0	11	0	0
T211	0	9	0	0
T219	0	17	0	0
T302	0	3	0	0
T318	0	10	0	0