SYSRST_CTRL Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 6.350s 2.112ms 50 50 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 8.350s 2.463ms 50 50 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 7.020s 2.435ms 5 5 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 7.330s 2.521ms 5 5 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 14.890s 6.029ms 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 6.250s 2.050ms 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 2.462m 39.498ms 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 7.720s 2.515ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.510s 2.064ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 6.250s 2.050ms 20 20 100.00
sysrst_ctrl_csr_aliasing 7.720s 2.515ms 5 5 100.00
V1 TOTAL 165 165 100.00
V2 combo_detect sysrst_ctrl_combo_detect 7.587m 181.125ms 50 50 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 10.120m 235.681ms 92 100 92.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 22.890m 504.939ms 50 50 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 39.340s 441.471ms 50 50 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 7.600s 2.514ms 50 50 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 6.530s 2.145ms 50 50 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 1.452m 149.013ms 50 50 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 7.690s 2.611ms 50 50 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 8.132m 3.554s 47 50 94.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 24.650s 41.310ms 2 2 100.00
V2 stress_all sysrst_ctrl_stress_all 12.789m 301.915ms 49 50 98.00
V2 alert_test sysrst_ctrl_alert_test 6.220s 2.013ms 50 50 100.00
V2 intr_test sysrst_ctrl_intr_test 5.960s 2.016ms 50 50 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 7.120s 2.096ms 20 20 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 7.120s 2.096ms 20 20 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 14.890s 6.029ms 5 5 100.00
sysrst_ctrl_csr_rw 6.250s 2.050ms 20 20 100.00
sysrst_ctrl_csr_aliasing 7.720s 2.515ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 29.940s 7.341ms 20 20 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 14.890s 6.029ms 5 5 100.00
sysrst_ctrl_csr_rw 6.250s 2.050ms 20 20 100.00
sysrst_ctrl_csr_aliasing 7.720s 2.515ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 29.940s 7.341ms 20 20 100.00
V2 TOTAL 680 692 98.27
V2S tl_intg_err sysrst_ctrl_sec_cm 1.673m 42.014ms 5 5 100.00
sysrst_ctrl_tl_intg_err 1.749m 42.367ms 20 20 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.749m 42.367ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 4.268m 1.163s 42 50 84.00
V3 TOTAL 42 50 84.00
TOTAL 912 932 97.85

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.90 98.90 96.83 100.00 97.44 98.37 99.71 94.03

Failure Buckets

Past Results