Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12	93.48	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12	93.48	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T23,T9,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T23,T9,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T23,T9,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T23,T9,T43
1	0	Covered	T1,T2,T6
1	1	Covered	T23,T9,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T9,T43
0	1	Covered	T43,T95,T100
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T9,T43
0	1	Covered	T23,T9,T43
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T9,T43
1	-	Covered	T23,T9,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T23,T9,T43
DetectSt	168	Covered	T23,T9,T43
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T23,T9,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T23,T9,T43
DebounceSt->IdleSt	163	Covered	T9,T45,T47
DetectSt->IdleSt	186	Covered	T43,T95,T100
DetectSt->StableSt	191	Covered	T23,T9,T43
IdleSt->DebounceSt	148	Covered	T23,T9,T43
StableSt->IdleSt	206	Covered	T23,T9,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T9,T43
0	1	Covered	T23,T9,T43
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T23,T9,T43
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T9,T43
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T9,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T45,T47
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T9,T43
DetectSt	-	-	-	-	1	-	-	Covered	T43,T95,T100
DetectSt	-	-	-	-	0	1	-	Covered	T23,T9,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T9,T43
StableSt	-	-	-	-	-	-	0	Covered	T23,T9,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	276	0	0
CntIncr_A	8157508	134468	0	0
CntNoWrap_A	8157508	7532008	0	0
DetectStDropOut_A	8157508	3	0	0
DetectedOut_A	8157508	821	0	0
DetectedPulseOut_A	8157508	122	0	0
DisabledIdleSt_A	8157508	7391481	0	0
DisabledNoDetection_A	8157508	7393690	0	0
EnterDebounceSt_A	8157508	154	0	0
EnterDetectSt_A	8157508	125	0	0
EnterStableSt_A	8157508	122	0	0
PulseIsPulse_A	8157508	122	0	0
StayInStableSt	8157508	699	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8157508	6611	0	0
gen_low_level_sva.LowLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	121	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	276	0	0
T9	22998	3	0	0
T10	726	0	0	0
T22	502	0	0	0
T23	697	2	0	0
T42	10980	0	0	0
T43	0	6	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	3	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	134468	0	0
T9	22998	102	0	0
T10	726	0	0	0
T22	502	0	0	0
T23	697	16	0	0
T42	10980	0	0	0
T43	0	210	0	0
T45	0	21	0	0
T46	0	21	0	0
T47	0	53	0	0
T48	0	118	0	0
T49	0	124	0	0
T50	0	51	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T74	0	8343	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532008	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	3	0	0
T31	976	0	0	0
T43	3098	1	0	0
T44	12487	0	0	0
T45	597	0	0	0
T57	1043	0	0	0
T58	504	0	0	0
T65	525	0	0	0
T95	0	1	0	0
T100	0	1	0	0
T101	422	0	0	0
T102	597	0	0	0
T103	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	821	0	0
T9	22998	7	0	0
T10	726	0	0	0
T22	502	0	0	0
T23	697	11	0	0
T42	10980	0	0	0
T43	0	24	0	0
T46	0	6	0	0
T47	0	5	0	0
T48	0	8	0	0
T49	0	10	0	0
T50	0	9	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	12	0	0
T109	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	122	0	0
T9	22998	1	0	0
T10	726	0	0	0
T22	502	0	0	0
T23	697	1	0	0
T42	10980	0	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	1	0	0
T109	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7391481	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7393690	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	154	0	0
T9	22998	2	0	0
T10	726	0	0	0
T22	502	0	0	0
T23	697	1	0	0
T42	10980	0	0	0
T43	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	125	0	0
T9	22998	1	0	0
T10	726	0	0	0
T22	502	0	0	0
T23	697	1	0	0
T42	10980	0	0	0
T43	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	1	0	0
T109	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	122	0	0
T9	22998	1	0	0
T10	726	0	0	0
T22	502	0	0	0
T23	697	1	0	0
T42	10980	0	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	1	0	0
T109	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	122	0	0
T9	22998	1	0	0
T10	726	0	0	0
T22	502	0	0	0
T23	697	1	0	0
T42	10980	0	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	1	0	0
T109	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	699	0	0
T9	22998	6	0	0
T10	726	0	0	0
T22	502	0	0	0
T23	697	10	0	0
T42	10980	0	0	0
T43	0	22	0	0
T46	0	5	0	0
T47	0	4	0	0
T48	0	7	0	0
T49	0	8	0	0
T50	0	8	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	11	0	0
T109	0	6	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	6611	0	0
T1	7769	25	0	0
T2	1045	4	0	0
T3	500	0	0	0
T4	19047	19	0	0
T5	826	1	0	0
T6	375494	5	0	0
T7	592	1	0	0
T8	0	36	0	0
T12	15221	27	0	0
T13	2206	10	0	0
T14	9688	30	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	121	0	0
T9	22998	1	0	0
T10	726	0	0	0
T22	502	0	0	0
T23	697	1	0	0
T42	10980	0	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	1	0	0
T109	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T9,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T2,T9,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T9,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T19
1	0	Covered	T1,T6,T12
1	1	Covered	T2,T9,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T19
0	1	Covered	T48,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T19
0	1	Unreachable
1	0	Covered	T2,T9,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T19
DetectSt	168	Covered	T2,T9,T19
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T2,T9,T19

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T19
DebounceSt->IdleSt	163	Covered	T41,T113,T114
DetectSt->IdleSt	186	Covered	T48,T83,T84
DetectSt->StableSt	191	Covered	T2,T9,T19
IdleSt->DebounceSt	148	Covered	T2,T9,T19
StableSt->IdleSt	206	Covered	T2,T9,T19

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T19
0	1	Covered	T2,T9,T19
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T19
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T19
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T113,T114
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T19
DetectSt	-	-	-	-	1	-	-	Covered	T48,T83,T84
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T19
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	181	0	0
CntIncr_A	8157508	122766	0	0
CntNoWrap_A	8157508	7532103	0	0
DetectStDropOut_A	8157508	21	0	0
DetectedOut_A	8157508	235750	0	0
DetectedPulseOut_A	8157508	56	0	0
DisabledIdleSt_A	8157508	5496509	0	0
DisabledNoDetection_A	8157508	5498768	0	0
EnterDebounceSt_A	8157508	106	0	0
EnterDetectSt_A	8157508	77	0	0
EnterStableSt_A	8157508	56	0	0
PulseIsPulse_A	8157508	56	0	0
StayInStableSt	8157508	235694	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8157508	6611	0	0
gen_low_level_sva.LowLevelEvent_A	8157508	7534546	0	0
gen_sticky_sva.StableStDropOut_A	8157508	1076112	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	181	0	0
T2	1045	2	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	6	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	2	0	0
T35	0	2	0	0
T46	0	2	0	0
T48	0	2	0	0
T57	0	2	0	0
T72	0	2	0	0
T73	0	4	0	0
T74	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	122766	0	0
T2	1045	57	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	255	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	26	0	0
T35	0	13	0	0
T46	0	54	0	0
T48	0	18	0	0
T57	0	12	0	0
T72	0	27	0	0
T73	0	46	0	0
T74	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532103	0	0
T1	7769	7360	0	0
T2	1045	642	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	21	0	0
T29	32422	0	0	0
T35	224924	0	0	0
T48	10589	1	0	0
T49	669	0	0	0
T61	489	0	0	0
T62	498	0	0	0
T63	496	0	0	0
T72	221471	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T115	0	1	0	0
T116	0	3	0	0
T117	0	3	0	0
T118	0	3	0	0
T119	0	2	0	0
T120	0	3	0	0
T121	0	3	0	0
T122	687	0	0	0
T123	793	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	235750	0	0
T2	1045	311	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	1597	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	104	0	0
T35	0	78	0	0
T46	0	120	0	0
T57	0	52	0	0
T72	0	168	0	0
T73	0	205	0	0
T74	0	115	0	0
T110	0	64	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	56	0	0
T2	1045	1	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	3	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	1	0	0
T35	0	1	0	0
T46	0	1	0	0
T57	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	2	0	0
T110	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	5496509	0	0
T1	7769	7360	0	0
T2	1045	32	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	5498768	0	0
T1	7769	7362	0	0
T2	1045	33	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	106	0	0
T2	1045	1	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	3	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	1	0	0
T35	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T57	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	77	0	0
T2	1045	1	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	3	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	1	0	0
T35	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T57	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	56	0	0
T2	1045	1	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	3	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	1	0	0
T35	0	1	0	0
T46	0	1	0	0
T57	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	2	0	0
T110	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	56	0	0
T2	1045	1	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	3	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	1	0	0
T35	0	1	0	0
T46	0	1	0	0
T57	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	2	0	0
T110	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	235694	0	0
T2	1045	310	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	1594	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	103	0	0
T35	0	77	0	0
T46	0	119	0	0
T57	0	51	0	0
T72	0	167	0	0
T73	0	203	0	0
T74	0	113	0	0
T110	0	63	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	6611	0	0
T1	7769	25	0	0
T2	1045	4	0	0
T3	500	0	0	0
T4	19047	19	0	0
T5	826	1	0	0
T6	375494	5	0	0
T7	592	1	0	0
T8	0	36	0	0
T12	15221	27	0	0
T13	2206	10	0	0
T14	9688	30	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1076112	0	0
T2	1045	217	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	359	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	116595	0	0
T35	0	425	0	0
T46	0	193	0	0
T57	0	530	0	0
T72	0	220812	0	0
T73	0	889	0	0
T74	0	272	0	0
T110	0	51	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T6,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T6,T4
1	1	Covered	T2,T6,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T9,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T2,T9,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T9,T19,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T19
1	0	Covered	T6,T4,T5
1	1	Covered	T2,T9,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T19,T57
0	1	Covered	T80,T81,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T19,T57
0	1	Unreachable
1	0	Covered	T9,T19,T57

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T19
DetectSt	168	Covered	T9,T19,T57
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T9,T19,T57

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T19,T57
DebounceSt->IdleSt	163	Covered	T2,T9,T72
DetectSt->IdleSt	186	Covered	T80,T81,T82
DetectSt->StableSt	191	Covered	T9,T19,T57
IdleSt->DebounceSt	148	Covered	T2,T9,T19
StableSt->IdleSt	206	Covered	T9,T19,T57

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T19
0	1	Covered	T2,T9,T19
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T19,T57
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T19
IdleSt	0	-	-	-	-	-	-	Covered	T2,T6,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T19,T57
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T9,T72
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T19
DetectSt	-	-	-	-	1	-	-	Covered	T80,T81,T82
DetectSt	-	-	-	-	0	1	-	Covered	T9,T19,T57
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T19,T57
StableSt	-	-	-	-	-	-	0	Covered	T9,T19,T57
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	165	0	0
CntIncr_A	8157508	458999	0	0
CntNoWrap_A	8157508	7532119	0	0
DetectStDropOut_A	8157508	10	0	0
DetectedOut_A	8157508	811715	0	0
DetectedPulseOut_A	8157508	57	0	0
DisabledIdleSt_A	8157508	5496509	0	0
DisabledNoDetection_A	8157508	5498768	0	0
EnterDebounceSt_A	8157508	100	0	0
EnterDetectSt_A	8157508	67	0	0
EnterStableSt_A	8157508	57	0	0
PulseIsPulse_A	8157508	57	0	0
StayInStableSt	8157508	811658	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_sticky_sva.StableStDropOut_A	8157508	760995	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	165	0	0
T2	1045	4	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	9	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	2	0	0
T35	0	2	0	0
T46	0	2	0	0
T48	0	2	0	0
T57	0	2	0	0
T72	0	4	0	0
T73	0	4	0	0
T74	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	458999	0	0
T2	1045	396	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	218	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	18	0	0
T35	0	53	0	0
T46	0	99	0	0
T48	0	32	0	0
T57	0	95	0	0
T72	0	220936	0	0
T73	0	128	0	0
T74	0	172	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532119	0	0
T1	7769	7360	0	0
T2	1045	640	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	10	0	0
T80	1194	2	0	0
T81	0	1	0	0
T82	0	2	0	0
T124	0	4	0	0
T125	0	1	0	0
T126	523	0	0	0
T127	23084	0	0	0
T128	7610	0	0	0
T129	491	0	0	0
T130	21172	0	0	0
T131	14057	0	0	0
T132	522	0	0	0
T133	2469	0	0	0
T134	668	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	811715	0	0
T9	22998	565	0	0
T10	726	0	0	0
T19	0	61	0	0
T20	490	0	0	0
T22	502	0	0	0
T35	0	330	0	0
T42	10980	0	0	0
T46	0	232	0	0
T48	0	26	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T57	0	414	0	0
T73	0	544	0	0
T74	0	24	0	0
T83	0	29279	0	0
T110	0	70	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	57	0	0
T9	22998	2	0	0
T10	726	0	0	0
T19	0	1	0	0
T20	490	0	0	0
T22	502	0	0	0
T35	0	1	0	0
T42	10980	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T57	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T83	0	2	0	0
T110	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	5496509	0	0
T1	7769	7360	0	0
T2	1045	32	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	5498768	0	0
T1	7769	7362	0	0
T2	1045	33	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	100	0	0
T2	1045	4	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	7	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	1	0	0
T35	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T57	0	1	0	0
T72	0	4	0	0
T73	0	2	0	0
T74	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	67	0	0
T9	22998	2	0	0
T10	726	0	0	0
T19	0	1	0	0
T20	490	0	0	0
T22	502	0	0	0
T35	0	1	0	0
T42	10980	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T57	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T83	0	2	0	0
T110	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	57	0	0
T9	22998	2	0	0
T10	726	0	0	0
T19	0	1	0	0
T20	490	0	0	0
T22	502	0	0	0
T35	0	1	0	0
T42	10980	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T57	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T83	0	2	0	0
T110	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	57	0	0
T9	22998	2	0	0
T10	726	0	0	0
T19	0	1	0	0
T20	490	0	0	0
T22	502	0	0	0
T35	0	1	0	0
T42	10980	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T57	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T83	0	2	0	0
T110	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	811658	0	0
T9	22998	563	0	0
T10	726	0	0	0
T19	0	60	0	0
T20	490	0	0	0
T22	502	0	0	0
T35	0	329	0	0
T42	10980	0	0	0
T46	0	231	0	0
T48	0	25	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T57	0	413	0	0
T73	0	542	0	0
T74	0	23	0	0
T83	0	29277	0	0
T110	0	69	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	760995	0	0
T9	22998	736	0	0
T10	726	0	0	0
T19	0	116664	0	0
T20	490	0	0	0
T22	502	0	0	0
T35	0	129	0	0
T42	10980	0	0	0
T46	0	51	0	0
T48	0	44	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T57	0	102	0	0
T73	0	463	0	0
T74	0	142	0	0
T83	0	185459	0	0
T110	0	56	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T9,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T2,T9,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T9,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T19
1	0	Covered	T1,T6,T12
1	1	Covered	T2,T9,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T57
0	1	Covered	T46,T77,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T57
0	1	Unreachable
1	0	Covered	T2,T9,T57

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T19
DetectSt	168	Covered	T2,T9,T57
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T2,T9,T57

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T57
DebounceSt->IdleSt	163	Covered	T9,T19,T46
DetectSt->IdleSt	186	Covered	T46,T77,T78
DetectSt->StableSt	191	Covered	T2,T9,T57
IdleSt->DebounceSt	148	Covered	T2,T9,T19
StableSt->IdleSt	206	Covered	T2,T9,T57

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T19
0	1	Covered	T2,T9,T19
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T57
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T19
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T57
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T19,T46
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T19
DetectSt	-	-	-	-	1	-	-	Covered	T46,T77,T78
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T57
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T57
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T57
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	169	0	0
CntIncr_A	8157508	233109	0	0
CntNoWrap_A	8157508	7532115	0	0
DetectStDropOut_A	8157508	6	0	0
DetectedOut_A	8157508	340864	0	0
DetectedPulseOut_A	8157508	52	0	0
DisabledIdleSt_A	8157508	5496509	0	0
DisabledNoDetection_A	8157508	5498768	0	0
EnterDebounceSt_A	8157508	113	0	0
EnterDetectSt_A	8157508	58	0	0
EnterStableSt_A	8157508	52	0	0
PulseIsPulse_A	8157508	52	0	0
StayInStableSt	8157508	340812	0	0
gen_high_event_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_sticky_sva.StableStDropOut_A	8157508	1190611	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	169	0	0
T2	1045	2	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	9	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	4	0	0
T35	0	2	0	0
T46	0	5	0	0
T48	0	2	0	0
T57	0	2	0	0
T72	0	2	0	0
T73	0	4	0	0
T74	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	233109	0	0
T2	1045	20	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	457	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	116696	0	0
T35	0	97	0	0
T46	0	36	0	0
T48	0	53	0	0
T57	0	30	0	0
T72	0	82	0	0
T73	0	146	0	0
T74	0	231	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532115	0	0
T1	7769	7360	0	0
T2	1045	642	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	6	0	0
T46	2880	2	0	0
T47	647	0	0	0
T48	10589	0	0	0
T49	669	0	0	0
T61	489	0	0	0
T62	498	0	0	0
T63	496	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T122	687	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	625	0	0	0
T138	439	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	340864	0	0
T2	1045	88	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	742	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T35	0	391	0	0
T48	0	32	0	0
T57	0	214	0	0
T72	0	343	0	0
T73	0	917	0	0
T74	0	118	0	0
T111	0	603	0	0
T112	0	167	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	52	0	0
T2	1045	1	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	2	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T35	0	1	0	0
T48	0	1	0	0
T57	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	5496509	0	0
T1	7769	7360	0	0
T2	1045	32	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	5498768	0	0
T1	7769	7362	0	0
T2	1045	33	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	113	0	0
T2	1045	1	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	7	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T19	0	4	0	0
T35	0	1	0	0
T46	0	3	0	0
T48	0	1	0	0
T57	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	58	0	0
T2	1045	1	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	2	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T35	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T57	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T111	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	52	0	0
T2	1045	1	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	2	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T35	0	1	0	0
T48	0	1	0	0
T57	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	52	0	0
T2	1045	1	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	2	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T35	0	1	0	0
T48	0	1	0	0
T57	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	340812	0	0
T2	1045	87	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	740	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T35	0	390	0	0
T48	0	31	0	0
T57	0	213	0	0
T72	0	342	0	0
T73	0	915	0	0
T74	0	117	0	0
T111	0	602	0	0
T112	0	166	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1190611	0	0
T2	1045	498	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	0	575	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T35	0	44	0	0
T48	0	27	0	0
T57	0	369	0	0
T72	0	220603	0	0
T73	0	102	0	0
T74	0	30	0	0
T111	0	55	0	0
T112	0	261	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T10,T30,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T10,T30,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T10,T30,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T35
1	0	Covered	T1,T2,T6
1	1	Covered	T10,T30,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T30,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T30,T41
0	1	Covered	T41,T79,T139
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T30,T41
1	-	Covered	T41,T79,T139

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T30,T41
DetectSt	168	Covered	T10,T30,T41
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T10,T30,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T30,T41
DebounceSt->IdleSt	163	Covered	T75,T140
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T30,T41
IdleSt->DebounceSt	148	Covered	T10,T30,T41
StableSt->IdleSt	206	Covered	T30,T41,T141

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T30,T41
0	1	Covered	T10,T30,T41
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T30,T41
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T30,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T30,T41
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T30,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T30,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T79,T139
StableSt	-	-	-	-	-	-	0	Covered	T10,T30,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	67	0	0
CntIncr_A	8157508	2595	0	0
CntNoWrap_A	8157508	7532217	0	0
DetectStDropOut_A	8157508	0	0	0
DetectedOut_A	8157508	3640	0	0
DetectedPulseOut_A	8157508	33	0	0
DisabledIdleSt_A	8157508	7341197	0	0
DisabledNoDetection_A	8157508	7343404	0	0
EnterDebounceSt_A	8157508	35	0	0
EnterDetectSt_A	8157508	33	0	0
EnterStableSt_A	8157508	33	0	0
PulseIsPulse_A	8157508	33	0	0
StayInStableSt	8157508	3588	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	67	0	0
T10	726	2	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	2	0	0
T41	0	2	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T75	0	1	0	0
T79	0	2	0	0
T139	0	4	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2595	0	0
T10	726	47	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	31	0	0
T41	0	93	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T75	0	26	0	0
T79	0	76	0	0
T139	0	84	0	0
T141	0	23	0	0
T142	0	55	0	0
T143	0	88	0	0
T144	0	65	0	0
T145	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532217	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	3640	0	0
T10	726	42	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	41	0	0
T41	0	65	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T79	0	2	0	0
T95	0	281	0	0
T139	0	79	0	0
T141	0	37	0	0
T142	0	441	0	0
T143	0	44	0	0
T144	0	117	0	0
T145	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	33	0	0
T10	726	1	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T79	0	1	0	0
T95	0	1	0	0
T139	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7341197	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7343404	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	35	0	0
T10	726	1	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T75	0	1	0	0
T79	0	1	0	0
T139	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	33	0	0
T10	726	1	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T79	0	1	0	0
T95	0	1	0	0
T139	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	33	0	0
T10	726	1	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T79	0	1	0	0
T95	0	1	0	0
T139	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	33	0	0
T10	726	1	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T79	0	1	0	0
T95	0	1	0	0
T139	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	3588	0	0
T10	726	40	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	39	0	0
T41	0	64	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T79	0	1	0	0
T95	0	279	0	0
T139	0	76	0	0
T141	0	35	0	0
T142	0	439	0	0
T143	0	42	0	0
T144	0	115	0	0
T145	402	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	13	0	0
T41	14975	1	0	0
T79	0	1	0	0
T113	1950	0	0	0
T139	0	1	0	0
T142	1011	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	12017	0	0	0
T154	19409	0	0	0
T155	17575	0	0	0
T156	402	0	0	0
T157	404	0	0	0
T158	404	0	0	0
T159	522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T31,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T5,T31,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T31,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T31,T48
1	0	Covered	T1,T12,T4
1	1	Covered	T5,T31,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T31,T35
0	1	Covered	T141,T160
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T31,T35
0	1	Covered	T31,T40,T36
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T31,T35
1	-	Covered	T31,T40,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T31,T35
DetectSt	168	Covered	T5,T31,T35
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T5,T31,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T31,T35
DebounceSt->IdleSt	163	Covered	T141,T75,T95
DetectSt->IdleSt	186	Covered	T141,T160
DetectSt->StableSt	191	Covered	T5,T31,T35
IdleSt->DebounceSt	148	Covered	T5,T31,T35
StableSt->IdleSt	206	Covered	T31,T35,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T31,T35
0	1	Covered	T5,T31,T35
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T31,T35
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T31,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T31,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T141,T95,T161
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T31,T35
DetectSt	-	-	-	-	1	-	-	Covered	T141,T160
DetectSt	-	-	-	-	0	1	-	Covered	T5,T31,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T40,T36
StableSt	-	-	-	-	-	-	0	Covered	T5,T31,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	130	0	0
CntIncr_A	8157508	91631	0	0
CntNoWrap_A	8157508	7532154	0	0
DetectStDropOut_A	8157508	2	0	0
DetectedOut_A	8157508	106301	0	0
DetectedPulseOut_A	8157508	61	0	0
DisabledIdleSt_A	8157508	7270449	0	0
DisabledNoDetection_A	8157508	7272652	0	0
EnterDebounceSt_A	8157508	67	0	0
EnterDetectSt_A	8157508	63	0	0
EnterStableSt_A	8157508	61	0	0
PulseIsPulse_A	8157508	61	0	0
StayInStableSt	8157508	106214	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8157508	2310	0	0
gen_low_level_sva.LowLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	130	0	0
T5	826	2	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T31	0	2	0	0
T32	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T40	0	4	0	0
T41	0	4	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	4	0	0
T141	0	3	0	0
T162	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	91631	0	0
T5	826	69	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T31	0	58	0	0
T32	0	14	0	0
T35	0	37	0	0
T36	0	51	0	0
T40	0	128	0	0
T41	0	186	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	152	0	0
T141	0	107	0	0
T162	0	128	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532154	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	423	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2	0	0
T79	807	0	0	0
T141	8378	1	0	0
T160	0	1	0	0
T163	405	0	0	0
T164	768	0	0	0
T165	442	0	0	0
T166	517	0	0	0
T167	502	0	0	0
T168	22959	0	0	0
T169	406	0	0	0
T170	452	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	106301	0	0
T5	826	150	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T31	0	17	0	0
T32	0	67	0	0
T35	0	186	0	0
T36	0	1	0	0
T40	0	262	0	0
T41	0	177	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	85	0	0
T139	0	32	0	0
T162	0	156	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	61	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	2	0	0
T139	0	2	0	0
T162	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7270449	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	3	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7272652	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	3	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	67	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	2	0	0
T141	0	2	0	0
T162	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	63	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	2	0	0
T141	0	1	0	0
T162	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	61	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	2	0	0
T139	0	2	0	0
T162	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	61	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	2	0	0
T139	0	2	0	0
T162	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	106214	0	0
T5	826	148	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T31	0	16	0	0
T32	0	65	0	0
T35	0	184	0	0
T40	0	259	0	0
T41	0	174	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	82	0	0
T139	0	30	0	0
T144	0	163	0	0
T162	0	153	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2310	0	0
T4	19047	5	0	0
T5	826	1	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	63	0	0
T10	0	1	0	0
T13	2206	6	0	0
T14	9688	0	0	0
T22	0	4	0	0
T23	697	0	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	0	1	0	0
T53	0	5	0	0
T55	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	34	0	0
T31	976	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	597	0	0	0
T58	504	0	0	0
T59	491	0	0	0
T65	525	0	0	0
T66	522	0	0	0
T79	0	1	0	0
T102	597	0	0	0
T103	422	0	0	0
T139	0	2	0	0
T144	0	1	0	0
T146	0	1	0	0
T162	0	1	0	0
T171	0	1	0	0
T172	949	0	0	0
T173	818	0	0	0