Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	90.12	93.48	90.48		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
90.12	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
91.56	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T3
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T3
1	0	Covered	T1,T12,T4
1	1	Covered	T1,T12,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T3
0	1	Covered	T4,T44,T27
1	0	Covered	T75,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T12,T3
1	-	Covered	T1,T3,T4

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T23,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T23,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T23,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T23,T9
1	0	Covered	T1,T2,T6
1	1	Covered	T5,T23,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T23,T9
0	1	Covered	T43,T38,T41
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T23,T9
0	1	Covered	T5,T23,T9
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T23,T9
1	-	Covered	T5,T23,T9

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T14
1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T14
1	0	Covered	T1,T12,T14
1	1	Covered	T1,T12,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T3
0	1	Covered	T1,T8,T29
1	0	Covered	T1,T8,T29

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T3
0	1	Covered	T1,T12,T14
1	0	Covered	T71,T75,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T12,T3
1	-	Covered	T1,T12,T14

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T9,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T9,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T9,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T19
1	0	Covered	T1,T6,T12
1	1	Covered	T2,T9,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T57
0	1	Covered	T46,T77,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T57
0	1	Unreachable
1	0	Covered	T2,T9,T57

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
90.12	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
91.56	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T7,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T10
1	0	Covered	T1,T2,T6
1	1	Covered	T5,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T10
0	1	Covered	T7,T41,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T10
0	1	Covered	T5,T40,T37
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T7,T10
1	-	Covered	T5,T40,T37

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T6,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T6,T4
1	1	Covered	T2,T6,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T9,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T9,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T9,T19,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T19
1	0	Covered	T6,T4,T5
1	1	Covered	T2,T9,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T19,T57
0	1	Covered	T80,T81,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T19,T57
0	1	Unreachable
1	0	Covered	T9,T19,T57

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T9,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T9,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T9,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T19
1	0	Covered	T1,T6,T12
1	1	Covered	T2,T9,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T19
0	1	Covered	T48,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T19
0	1	Unreachable
1	0	Covered	T2,T9,T19

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T23,T9
DetectSt	168	Covered	T5,T23,T9
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T5,T23,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T23,T9
DebounceSt->IdleSt	163	Covered	T9,T45,T47
DetectSt->IdleSt	186	Covered	T43,T48,T83
DetectSt->StableSt	191	Covered	T5,T23,T9
IdleSt->DebounceSt	148	Covered	T5,T23,T9
StableSt->IdleSt	206	Covered	T5,T23,T9

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
90.12	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
91.56	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T23,T9
0	1	Covered	T5,T23,T9
0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T23,T9
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T23,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T23,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T45,T47
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T23,T9
DetectSt	-	-	-	-	1	-	-	Covered	T43,T48,T83
DetectSt	-	-	-	-	0	1	-	Covered	T5,T23,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T12,T3
StableSt	-	-	-	-	-	-	1	Covered	T5,T23,T9
StableSt	-	-	-	-	-	-	0	Covered	T5,T23,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T12
0	1	Covered	T1,T2,T12
0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T12
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T19,T46
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T12
DetectSt	-	-	-	-	1	-	-	Covered	T1,T8,T46
DetectSt	-	-	-	-	0	1	-	Covered	T2,T12,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T12,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T12,T14
StableSt	-	-	-	-	-	-	0	Covered	T2,T12,T3
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	212095208	18090	0	0
CntIncr_A	212095208	2086811	0	0
CntNoWrap_A	212095208	195821294	0	0
DetectStDropOut_A	212095208	2015	0	0
DetectedOut_A	212095208	2059402	0	0
DetectedPulseOut_A	212095208	5951	0	0
DisabledIdleSt_A	212095208	183994648	0	0
DisabledNoDetection_A	212095208	184049156	0	0
EnterDebounceSt_A	212095208	9299	0	0
EnterDetectSt_A	212095208	8818	0	0
EnterStableSt_A	212095208	5951	0	0
PulseIsPulse_A	212095208	5951	0	0
StayInStableSt	212095208	2052461	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	73417572	49047	0	0
gen_high_event_sva.HighLevelEvent_A	40787540	37672730	0	0
gen_high_level_sva.HighLevelEvent_A	138677636	128087282	0	0
gen_low_level_sva.LowLevelEvent_A	73417572	67810914	0	0
gen_not_sticky_sva.StableStDropOut_A	187622684	4732	0	0
gen_sticky_sva.StableStDropOut_A	24472524	3027718	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212095208	18090	0	0
T1	7769	26	0	0
T2	1045	0	0	0
T3	1000	4	0	0
T4	38094	2	0	0
T5	1652	0	0	0
T6	375494	0	0	0
T7	1184	0	0	0
T8	10797	24	0	0
T9	45996	9	0	0
T10	726	0	0	0
T12	15221	22	0	0
T13	4412	1	0	0
T14	19376	8	0	0
T22	502	0	0	0
T23	1394	2	0	0
T27	0	19	0	0
T28	0	2	0	0
T29	0	34	0	0
T42	10980	0	0	0
T43	0	6	0	0
T44	0	5	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	5	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	818	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212095208	2086811	0	0
T1	7769	453	0	0
T2	1045	0	0	0
T3	1000	46	0	0
T4	38094	127	0	0
T5	1652	0	0	0
T6	375494	0	0	0
T7	1184	0	0	0
T8	10797	584	0	0
T9	45996	341	0	0
T10	726	0	0	0
T12	15221	649	0	0
T13	4412	20	0	0
T14	19376	312	0	0
T22	502	0	0	0
T23	1394	16	0	0
T27	0	1592	0	0
T28	0	244	0	0
T29	0	1251	0	0
T42	10980	0	0	0
T43	0	210	0	0
T44	0	348	0	0
T45	0	21	0	0
T46	0	21	0	0
T47	0	53	0	0
T48	0	143	0	0
T49	0	124	0	0
T50	0	51	0	0
T51	818	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T74	0	8343	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212095208	195821294	0	0
T1	201994	191246	0	0
T2	27170	16736	0	0
T3	13000	2570	0	0
T4	495222	462824	0	0
T5	21476	11030	0	0
T6	9762844	9752418	0	0
T7	15392	4956	0	0
T12	395746	384576	0	0
T13	57356	15677	0	0
T14	251888	241346	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212095208	2015	0	0
T1	7769	7	0	0
T31	976	0	0	0
T32	491	0	0	0
T36	551	0	0	0
T37	0	3	0	0
T43	3098	1	0	0
T44	12487	0	0	0
T45	597	0	0	0
T57	1043	0	0	0
T58	504	0	0	0
T65	525	0	0	0
T68	0	12	0	0
T69	0	15	0	0
T70	11656	0	0	0
T71	8613	0	0	0
T75	0	1	0	0
T86	22896	6	0	0
T87	19252	1	0	0
T88	0	1	0	0
T89	0	8	0	0
T90	0	12	0	0
T91	0	17	0	0
T92	0	6	0	0
T93	0	1	0	0
T94	0	13	0	0
T95	0	6	0	0
T96	0	3	0	0
T97	0	12	0	0
T98	0	10	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	422	0	0	0
T102	597	0	0	0
T103	422	0	0	0
T104	494	0	0	0
T105	493	0	0	0
T106	460	0	0	0
T107	750	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212095208	2059402	0	0
T1	7769	0	0	0
T2	1045	0	0	0
T3	3000	79	0	0
T4	114282	25	0	0
T5	4956	0	0	0
T6	375494	0	0	0
T7	3552	0	0	0
T8	64782	1183	0	0
T9	160986	15	0	0
T10	1452	0	0	0
T12	76105	595	0	0
T13	13236	0	0	0
T14	67816	147	0	0
T22	1004	0	0	0
T23	4879	11	0	0
T27	0	55	0	0
T28	0	8	0	0
T29	0	3242	0	0
T42	21960	949	0	0
T43	0	24	0	0
T44	0	10	0	0
T46	0	6	0	0
T47	0	5	0	0
T48	0	12	0	0
T49	0	10	0	0
T50	0	9	0	0
T51	1227	0	0	0
T52	852	0	0	0
T53	1004	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	12	0	0
T108	0	1398	0	0
T109	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212095208	5951	0	0
T1	7769	0	0	0
T2	1045	0	0	0
T3	3000	2	0	0
T4	114282	1	0	0
T5	4956	0	0	0
T6	375494	0	0	0
T7	3552	0	0	0
T8	64782	12	0	0
T9	160986	3	0	0
T10	1452	0	0	0
T12	76105	11	0	0
T13	13236	0	0	0
T14	67816	4	0	0
T22	1004	0	0	0
T23	4879	1	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	17	0	0
T42	21960	17	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	1227	0	0	0
T52	852	0	0	0
T53	1004	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	1	0	0
T108	0	26	0	0
T109	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212095208	183994648	0	0
T1	201994	180793	0	0
T2	27170	14908	0	0
T3	13000	2406	0	0
T4	495222	452112	0	0
T5	21476	7252	0	0
T6	9762844	9752418	0	0
T7	15392	4218	0	0
T12	395746	356523	0	0
T13	57356	15631	0	0
T14	251888	213587	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212095208	184049156	0	0
T1	201994	180839	0	0
T2	27170	14934	0	0
T3	13000	2430	0	0
T4	495222	452299	0	0
T5	21476	7269	0	0
T6	9762844	9752444	0	0
T7	15392	4240	0	0
T12	395746	356611	0	0
T13	57356	15708	0	0
T14	251888	213609	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212095208	9299	0	0
T1	7769	13	0	0
T2	1045	0	0	0
T3	1000	2	0	0
T4	38094	1	0	0
T5	1652	0	0	0
T6	375494	0	0	0
T7	1184	0	0	0
T8	10797	12	0	0
T9	45996	6	0	0
T10	726	0	0	0
T12	15221	11	0	0
T13	4412	1	0	0
T14	19376	4	0	0
T22	502	0	0	0
T23	1394	1	0	0
T27	0	10	0	0
T28	0	1	0	0
T29	0	17	0	0
T42	10980	0	0	0
T43	0	3	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	3	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	818	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212095208	8818	0	0
T1	7769	13	0	0
T2	1045	0	0	0
T3	1000	2	0	0
T4	38094	1	0	0
T5	1652	0	0	0
T6	375494	0	0	0
T7	1184	0	0	0
T8	10797	12	0	0
T9	45996	3	0	0
T10	726	0	0	0
T12	15221	11	0	0
T13	4412	0	0	0
T14	19376	4	0	0
T22	502	0	0	0
T23	1394	1	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	17	0	0
T42	10980	0	0	0
T43	0	3	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	818	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	1	0	0
T86	0	6	0	0
T109	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212095208	5951	0	0
T1	7769	0	0	0
T2	1045	0	0	0
T3	3000	2	0	0
T4	114282	1	0	0
T5	4956	0	0	0
T6	375494	0	0	0
T7	3552	0	0	0
T8	64782	12	0	0
T9	160986	3	0	0
T10	1452	0	0	0
T12	76105	11	0	0
T13	13236	0	0	0
T14	67816	4	0	0
T22	1004	0	0	0
T23	4879	1	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	17	0	0
T42	21960	17	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	1227	0	0	0
T52	852	0	0	0
T53	1004	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	1	0	0
T108	0	26	0	0
T109	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212095208	5951	0	0
T1	7769	0	0	0
T2	1045	0	0	0
T3	3000	2	0	0
T4	114282	1	0	0
T5	4956	0	0	0
T6	375494	0	0	0
T7	3552	0	0	0
T8	64782	12	0	0
T9	160986	3	0	0
T10	1452	0	0	0
T12	76105	11	0	0
T13	13236	0	0	0
T14	67816	4	0	0
T22	1004	0	0	0
T23	4879	1	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	17	0	0
T42	21960	17	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	1227	0	0	0
T52	852	0	0	0
T53	1004	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	1	0	0
T108	0	26	0	0
T109	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	212095208	2052461	0	0
T1	7769	0	0	0
T2	1045	0	0	0
T3	3000	76	0	0
T4	114282	24	0	0
T5	4956	0	0	0
T6	375494	0	0	0
T7	3552	0	0	0
T8	64782	1171	0	0
T9	160986	12	0	0
T10	1452	0	0	0
T12	76105	583	0	0
T13	13236	0	0	0
T14	67816	143	0	0
T22	1004	0	0	0
T23	4879	10	0	0
T27	0	46	0	0
T28	0	7	0	0
T29	0	3219	0	0
T42	21960	932	0	0
T43	0	22	0	0
T44	0	8	0	0
T46	0	5	0	0
T47	0	4	0	0
T48	0	10	0	0
T49	0	8	0	0
T50	0	8	0	0
T51	1227	0	0	0
T52	852	0	0	0
T53	1004	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T85	0	11	0	0
T108	0	1369	0	0
T109	0	6	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73417572	49047	0	0
T1	54383	177	0	0
T2	7315	16	0	0
T3	3500	1	0	0
T4	171423	129	0	0
T5	7434	8	0	0
T6	2628458	20	0	0
T7	5328	9	0	0
T8	21594	209	0	0
T9	45996	474	0	0
T10	0	2	0	0
T12	106547	199	0	0
T13	19854	66	0	0
T14	87192	194	0	0
T22	0	16	0	0
T23	1394	0	0	0
T42	21960	94	0	0
T51	818	0	0	0
T52	0	2	0	0
T53	0	11	0	0
T54	0	6	0	0
T55	0	9	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40787540	37672730	0	0
T1	38845	36810	0	0
T2	5225	3225	0	0
T3	2500	500	0	0
T4	95235	89050	0	0
T5	4130	2130	0	0
T6	1877470	1875470	0	0
T7	2960	960	0	0
T12	76105	74010	0	0
T13	11030	3030	0	0
T14	48440	46440	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138677636	128087282	0	0
T1	132073	125154	0	0
T2	17765	10965	0	0
T3	8500	1700	0	0
T4	323799	302770	0	0
T5	14042	7242	0	0
T6	6383398	6376598	0	0
T7	10064	3264	0	0
T12	258757	251634	0	0
T13	37502	10302	0	0
T14	164696	157896	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73417572	67810914	0	0
T1	69921	66258	0	0
T2	9405	5805	0	0
T3	4500	900	0	0
T4	171423	160290	0	0
T5	7434	3834	0	0
T6	3379446	3375846	0	0
T7	5328	1728	0	0
T12	136989	133218	0	0
T13	19854	5454	0	0
T14	87192	83592	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187622684	4732	0	0
T1	7769	0	0	0
T2	1045	0	0	0
T3	2500	1	0	0
T4	95235	1	0	0
T5	4130	0	0	0
T7	2960	0	0	0
T8	53985	12	0	0
T9	160986	3	0	0
T10	2178	0	0	0
T12	60884	10	0	0
T13	11030	0	0	0
T14	58128	4	0	0
T20	490	0	0	0
T22	1506	0	0	0
T23	4182	1	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	11	0	0
T42	32940	17	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	1636	0	0	0
T52	1278	0	0	0
T53	1506	0	0	0
T54	2130	0	0	0
T55	2668	0	0	0
T85	0	1	0	0
T108	0	23	0	0
T109	0	1	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24472524	3027718	0	0
T2	2090	715	0	0
T3	1000	0	0	0
T4	38094	0	0	0
T5	1652	0	0	0
T6	750988	0	0	0
T7	1184	0	0	0
T8	21594	0	0	0
T9	22998	1670	0	0
T10	726	0	0	0
T12	30442	0	0	0
T13	4412	0	0	0
T14	19376	0	0	0
T19	0	233259	0	0
T20	490	0	0	0
T22	502	0	0	0
T35	0	598	0	0
T42	10980	0	0	0
T46	0	244	0	0
T48	0	71	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T57	0	1001	0	0
T72	0	441415	0	0
T73	0	1454	0	0
T74	0	444	0	0
T83	0	185459	0	0
T110	0	107	0	0
T111	0	55	0	0
T112	0	261	0	0