Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T5,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T7,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T10
1	0	Covered	T1,T2,T6
1	1	Covered	T5,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T10
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T10
0	1	Covered	T5,T40,T142
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T7,T10
1	-	Covered	T5,T40,T142

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T7,T10
DetectSt	168	Covered	T5,T7,T10
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T5,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T7,T10
DebounceSt->IdleSt	163	Covered	T75,T151,T140
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T5,T7,T10
IdleSt->DebounceSt	148	Covered	T5,T7,T10
StableSt->IdleSt	206	Covered	T5,T35,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T7,T10
0	1	Covered	T5,T7,T10
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T10
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T7,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T151,T140
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T7,T10
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T5,T7,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T40,T142
StableSt	-	-	-	-	-	-	0	Covered	T5,T7,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	61	0	0
CntIncr_A	8157508	41302	0	0
CntNoWrap_A	8157508	7532223	0	0
DetectStDropOut_A	8157508	0	0	0
DetectedOut_A	8157508	2617	0	0
DetectedPulseOut_A	8157508	29	0	0
DisabledIdleSt_A	8157508	7391456	0	0
DisabledNoDetection_A	8157508	7393667	0	0
EnterDebounceSt_A	8157508	32	0	0
EnterDetectSt_A	8157508	29	0	0
EnterStableSt_A	8157508	29	0	0
PulseIsPulse_A	8157508	29	0	0
StayInStableSt	8157508	2571	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	61	0	0
T5	826	2	0	0
T7	592	2	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	2	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	2	0	0
T35	0	2	0	0
T40	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T141	0	2	0	0
T142	0	4	0	0
T174	0	2	0	0
T175	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	41302	0	0
T5	826	69	0	0
T7	592	28	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	47	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	14	0	0
T35	0	37	0	0
T40	0	64	0	0
T42	10980	0	0	0
T51	409	0	0	0
T141	0	84	0	0
T142	0	110	0	0
T174	0	37	0	0
T175	0	85	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532223	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	423	0	0
T6	375494	375093	0	0
T7	592	189	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2617	0	0
T5	826	152	0	0
T7	592	41	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	43	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	44	0	0
T35	0	41	0	0
T40	0	42	0	0
T42	10980	0	0	0
T51	409	0	0	0
T141	0	38	0	0
T142	0	190	0	0
T174	0	43	0	0
T175	0	571	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	29	0	0
T5	826	1	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T174	0	1	0	0
T175	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7391456	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	3	0	0
T6	375494	375093	0	0
T7	592	4	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7393667	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	3	0	0
T6	375494	375094	0	0
T7	592	4	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	32	0	0
T5	826	1	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T174	0	1	0	0
T175	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	29	0	0
T5	826	1	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T174	0	1	0	0
T175	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	29	0	0
T5	826	1	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T174	0	1	0	0
T175	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	29	0	0
T5	826	1	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T174	0	1	0	0
T175	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2571	0	0
T5	826	151	0	0
T7	592	39	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	41	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	42	0	0
T35	0	39	0	0
T40	0	41	0	0
T42	10980	0	0	0
T51	409	0	0	0
T141	0	36	0	0
T142	0	188	0	0
T174	0	41	0	0
T175	0	569	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	11	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T40	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T142	0	2	0	0
T148	0	1	0	0
T149	0	1	0	0
T160	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T11,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T5,T11,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T11,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T11,T48
1	0	Covered	T1,T12,T4
1	1	Covered	T5,T11,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T11,T39
0	1	Covered	T179,T180
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T11,T39
0	1	Covered	T5,T142,T79
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T11,T39
1	-	Covered	T5,T142,T79

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T11,T39
DetectSt	168	Covered	T5,T11,T39
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T5,T11,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T11,T39
DebounceSt->IdleSt	163	Covered	T174,T181,T75
DetectSt->IdleSt	186	Covered	T179,T180
DetectSt->StableSt	191	Covered	T5,T11,T39
IdleSt->DebounceSt	148	Covered	T5,T11,T39
StableSt->IdleSt	206	Covered	T5,T142,T141

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T11,T39
0	1	Covered	T5,T11,T39
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T39
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T11,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T11,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T174,T181,T182
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T11,T39
DetectSt	-	-	-	-	1	-	-	Covered	T179,T180
DetectSt	-	-	-	-	0	1	-	Covered	T5,T11,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T142,T79
StableSt	-	-	-	-	-	-	0	Covered	T5,T11,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	120	0	0
CntIncr_A	8157508	62381	0	0
CntNoWrap_A	8157508	7532164	0	0
DetectStDropOut_A	8157508	2	0	0
DetectedOut_A	8157508	65168	0	0
DetectedPulseOut_A	8157508	55	0	0
DisabledIdleSt_A	8157508	7318757	0	0
DisabledNoDetection_A	8157508	7320969	0	0
EnterDebounceSt_A	8157508	64	0	0
EnterDetectSt_A	8157508	57	0	0
EnterStableSt_A	8157508	55	0	0
PulseIsPulse_A	8157508	55	0	0
StayInStableSt	8157508	65085	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8157508	2664	0	0
gen_low_level_sva.LowLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	120	0	0
T5	826	4	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	2	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T33	0	2	0	0
T39	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	2	0	0
T141	0	2	0	0
T142	0	6	0	0
T143	0	2	0	0
T162	0	2	0	0
T174	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	62381	0	0
T5	826	138	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	19	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T33	0	51	0	0
T39	0	32	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	76	0	0
T141	0	23	0	0
T142	0	165	0	0
T143	0	88	0	0
T162	0	64	0	0
T174	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532164	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	421	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2	0	0
T179	547	1	0	0
T180	0	1	0	0
T183	402	0	0	0
T184	7329	0	0	0
T185	1031	0	0	0
T186	426	0	0	0
T187	529	0	0	0
T188	1303	0	0	0
T189	10816	0	0	0
T190	402	0	0	0
T191	489	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	65168	0	0
T5	826	55	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	39	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T33	0	42	0	0
T39	0	45	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	197	0	0
T141	0	37	0	0
T142	0	132	0	0
T143	0	404	0	0
T162	0	329	0	0
T192	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	55	0	0
T5	826	2	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T33	0	1	0	0
T39	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	1	0	0
T141	0	1	0	0
T142	0	3	0	0
T143	0	1	0	0
T162	0	1	0	0
T192	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7318757	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	3	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7320969	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	3	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	64	0	0
T5	826	2	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T33	0	1	0	0
T39	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	1	0	0
T141	0	1	0	0
T142	0	3	0	0
T143	0	1	0	0
T162	0	1	0	0
T174	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	57	0	0
T5	826	2	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T33	0	1	0	0
T39	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	1	0	0
T141	0	1	0	0
T142	0	3	0	0
T143	0	1	0	0
T162	0	1	0	0
T192	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	55	0	0
T5	826	2	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T33	0	1	0	0
T39	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	1	0	0
T141	0	1	0	0
T142	0	3	0	0
T143	0	1	0	0
T162	0	1	0	0
T192	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	55	0	0
T5	826	2	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T33	0	1	0	0
T39	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	1	0	0
T141	0	1	0	0
T142	0	3	0	0
T143	0	1	0	0
T162	0	1	0	0
T192	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	65085	0	0
T5	826	52	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	37	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T33	0	40	0	0
T39	0	43	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	196	0	0
T141	0	35	0	0
T142	0	128	0	0
T143	0	403	0	0
T162	0	327	0	0
T192	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2664	0	0
T4	19047	2	0	0
T5	826	2	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	72	0	0
T10	0	1	0	0
T13	2206	4	0	0
T14	9688	0	0	0
T22	0	6	0	0
T23	697	0	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	0	1	0	0
T53	0	6	0	0
T54	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	26	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T42	10980	0	0	0
T51	409	0	0	0
T79	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0
T171	0	2	0	0
T177	0	1	0	0
T182	0	2	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T7,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T5,T7,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T7,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T10
1	0	Covered	T1,T2,T6
1	1	Covered	T5,T7,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T40,T37
0	1	Covered	T7,T193,T196
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T40,T30
0	1	Covered	T40,T37,T30
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T40,T30
1	-	Covered	T40,T37,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T7,T40
DetectSt	168	Covered	T5,T7,T40
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T5,T40,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T7,T40
DebounceSt->IdleSt	163	Covered	T7,T197,T75
DetectSt->IdleSt	186	Covered	T7,T193,T196
DetectSt->StableSt	191	Covered	T5,T40,T37
IdleSt->DebounceSt	148	Covered	T5,T7,T40
StableSt->IdleSt	206	Covered	T40,T37,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T7,T40
0	1	Covered	T5,T7,T40
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T40
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T7,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T7,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T197,T95
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T7,T40
DetectSt	-	-	-	-	1	-	-	Covered	T7,T193,T196
DetectSt	-	-	-	-	0	1	-	Covered	T5,T40,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T37,T30
StableSt	-	-	-	-	-	-	0	Covered	T5,T40,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	130	0	0
CntIncr_A	8157508	116684	0	0
CntNoWrap_A	8157508	7532154	0	0
DetectStDropOut_A	8157508	4	0	0
DetectedOut_A	8157508	46516	0	0
DetectedPulseOut_A	8157508	57	0	0
DisabledIdleSt_A	8157508	7303985	0	0
DisabledNoDetection_A	8157508	7306182	0	0
EnterDebounceSt_A	8157508	71	0	0
EnterDetectSt_A	8157508	61	0	0
EnterStableSt_A	8157508	57	0	0
PulseIsPulse_A	8157508	57	0	0
StayInStableSt	8157508	46429	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	130	0	0
T5	826	2	0	0
T7	592	3	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T37	0	2	0	0
T40	0	2	0	0
T41	0	4	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	2	0	0
T198	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	116684	0	0
T5	826	69	0	0
T7	592	56	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	31	0	0
T33	0	51	0	0
T34	0	41	0	0
T37	0	62	0	0
T40	0	64	0	0
T41	0	186	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	64	0	0
T198	0	15	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532154	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	423	0	0
T6	375494	375093	0	0
T7	592	188	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	4	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T14	9688	0	0	0
T22	502	0	0	0
T23	697	0	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T180	0	1	0	0
T193	0	1	0	0
T196	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	46516	0	0
T5	826	150	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	21	0	0
T33	0	22	0	0
T34	0	123	0	0
T37	0	1	0	0
T40	0	57	0	0
T41	0	176	0	0
T42	10980	0	0	0
T51	409	0	0	0
T142	0	149	0	0
T162	0	222	0	0
T198	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	57	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T142	0	1	0	0
T162	0	1	0	0
T198	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7303985	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	3	0	0
T6	375494	375093	0	0
T7	592	4	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7306182	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	3	0	0
T6	375494	375094	0	0
T7	592	4	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	71	0	0
T5	826	1	0	0
T7	592	2	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	1	0	0
T198	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	61	0	0
T5	826	1	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	1	0	0
T198	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	57	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T142	0	1	0	0
T162	0	1	0	0
T198	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	57	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T142	0	1	0	0
T162	0	1	0	0
T198	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	46429	0	0
T5	826	148	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	20	0	0
T33	0	21	0	0
T34	0	122	0	0
T40	0	56	0	0
T41	0	174	0	0
T42	10980	0	0	0
T51	409	0	0	0
T142	0	148	0	0
T162	0	221	0	0
T174	0	79	0	0
T198	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	26	0	0
T30	0	1	0	0
T32	491	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	1027	1	0	0
T41	0	2	0	0
T70	11656	0	0	0
T71	8613	0	0	0
T86	22896	0	0	0
T87	19252	0	0	0
T104	494	0	0	0
T105	493	0	0	0
T106	460	0	0	0
T107	750	0	0	0
T139	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T162	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T37,T33,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T37,T33,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T37,T33,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T39,T32
1	0	Covered	T1,T2,T6
1	1	Covered	T37,T33,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T33,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T33,T38
0	1	Covered	T38,T143,T175
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T37,T33,T38
1	-	Covered	T38,T143,T175

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T37,T33,T38
DetectSt	168	Covered	T37,T33,T38
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T37,T33,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T37,T33,T38
DebounceSt->IdleSt	163	Covered	T75,T149,T140
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T37,T33,T38
IdleSt->DebounceSt	148	Covered	T37,T33,T38
StableSt->IdleSt	206	Covered	T37,T38,T143

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T37,T33,T38
0	1	Covered	T37,T33,T38
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T37,T33,T38
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T37,T33,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T37,T33,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T149,T140
DebounceSt	-	0	0	-	-	-	-	Covered	T37,T33,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T37,T33,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T143,T175
StableSt	-	-	-	-	-	-	0	Covered	T37,T33,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	83	0	0
CntIncr_A	8157508	18325	0	0
CntNoWrap_A	8157508	7532201	0	0
DetectStDropOut_A	8157508	0	0	0
DetectedOut_A	8157508	2372	0	0
DetectedPulseOut_A	8157508	40	0	0
DisabledIdleSt_A	8157508	7391523	0	0
DisabledNoDetection_A	8157508	7393729	0	0
EnterDebounceSt_A	8157508	43	0	0
EnterDetectSt_A	8157508	40	0	0
EnterStableSt_A	8157508	40	0	0
PulseIsPulse_A	8157508	40	0	0
StayInStableSt	8157508	2314	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8157508	6333	0	0
gen_low_level_sva.LowLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	83	0	0
T30	21045	0	0	0
T33	0	2	0	0
T34	18044	0	0	0
T37	9356	2	0	0
T38	0	4	0	0
T74	19288	0	0	0
T75	0	1	0	0
T85	671	0	0	0
T88	15512	0	0	0
T108	15744	0	0	0
T110	3953	0	0	0
T142	0	2	0	0
T143	0	2	0	0
T146	0	2	0	0
T175	0	2	0	0
T176	0	4	0	0
T197	0	2	0	0
T199	523	0	0	0
T200	532	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	18325	0	0
T30	21045	0	0	0
T33	0	51	0	0
T34	18044	0	0	0
T37	9356	62	0	0
T38	0	106	0	0
T74	19288	0	0	0
T75	0	27	0	0
T85	671	0	0	0
T88	15512	0	0	0
T108	15744	0	0	0
T110	3953	0	0	0
T142	0	55	0	0
T143	0	88	0	0
T146	0	83	0	0
T175	0	85	0	0
T176	0	60	0	0
T197	0	26	0	0
T199	523	0	0	0
T200	532	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532201	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2372	0	0
T30	21045	0	0	0
T33	0	42	0	0
T34	18044	0	0	0
T37	9356	45	0	0
T38	0	68	0	0
T74	19288	0	0	0
T85	671	0	0	0
T88	15512	0	0	0
T108	15744	0	0	0
T110	3953	0	0	0
T142	0	141	0	0
T143	0	62	0	0
T146	0	127	0	0
T171	0	60	0	0
T175	0	40	0	0
T176	0	83	0	0
T197	0	44	0	0
T199	523	0	0	0
T200	532	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	40	0	0
T30	21045	0	0	0
T33	0	1	0	0
T34	18044	0	0	0
T37	9356	1	0	0
T38	0	2	0	0
T74	19288	0	0	0
T85	671	0	0	0
T88	15512	0	0	0
T108	15744	0	0	0
T110	3953	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0
T171	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T197	0	1	0	0
T199	523	0	0	0
T200	532	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7391523	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7393729	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	43	0	0
T30	21045	0	0	0
T33	0	1	0	0
T34	18044	0	0	0
T37	9356	1	0	0
T38	0	2	0	0
T74	19288	0	0	0
T75	0	1	0	0
T85	671	0	0	0
T88	15512	0	0	0
T108	15744	0	0	0
T110	3953	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0
T175	0	1	0	0
T176	0	2	0	0
T197	0	1	0	0
T199	523	0	0	0
T200	532	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	40	0	0
T30	21045	0	0	0
T33	0	1	0	0
T34	18044	0	0	0
T37	9356	1	0	0
T38	0	2	0	0
T74	19288	0	0	0
T85	671	0	0	0
T88	15512	0	0	0
T108	15744	0	0	0
T110	3953	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0
T171	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T197	0	1	0	0
T199	523	0	0	0
T200	532	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	40	0	0
T30	21045	0	0	0
T33	0	1	0	0
T34	18044	0	0	0
T37	9356	1	0	0
T38	0	2	0	0
T74	19288	0	0	0
T85	671	0	0	0
T88	15512	0	0	0
T108	15744	0	0	0
T110	3953	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0
T171	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T197	0	1	0	0
T199	523	0	0	0
T200	532	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	40	0	0
T30	21045	0	0	0
T33	0	1	0	0
T34	18044	0	0	0
T37	9356	1	0	0
T38	0	2	0	0
T74	19288	0	0	0
T85	671	0	0	0
T88	15512	0	0	0
T108	15744	0	0	0
T110	3953	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0
T171	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T197	0	1	0	0
T199	523	0	0	0
T200	532	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2314	0	0
T30	21045	0	0	0
T33	0	40	0	0
T34	18044	0	0	0
T37	9356	43	0	0
T38	0	66	0	0
T74	19288	0	0	0
T85	671	0	0	0
T88	15512	0	0	0
T108	15744	0	0	0
T110	3953	0	0	0
T142	0	139	0	0
T143	0	61	0	0
T146	0	126	0	0
T171	0	57	0	0
T175	0	39	0	0
T176	0	80	0	0
T197	0	42	0	0
T199	523	0	0	0
T200	532	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	6333	0	0
T1	7769	28	0	0
T2	1045	4	0	0
T3	500	0	0	0
T4	19047	17	0	0
T5	826	0	0	0
T6	375494	5	0	0
T7	592	2	0	0
T8	0	29	0	0
T9	0	94	0	0
T12	15221	31	0	0
T13	2206	8	0	0
T14	9688	29	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	21	0	0
T38	6935	2	0	0
T143	0	1	0	0
T146	0	1	0	0
T162	802	0	0	0
T171	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T182	0	1	0	0
T193	0	1	0	0
T196	0	1	0	0
T201	424	0	0	0
T202	555	0	0	0
T203	503	0	0	0
T204	408	0	0	0
T205	418	0	0	0
T206	36233	0	0	0
T207	408	0	0	0
T208	525	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T12,T3
1	1	Covered	T1,T12,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T5,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T7,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T10
1	0	Covered	T1,T12,T3
1	1	Covered	T5,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T10
0	1	Covered	T79,T180
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T10
0	1	Covered	T5,T35,T40
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T7,T10
1	-	Covered	T5,T35,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T7,T10
DetectSt	168	Covered	T5,T7,T10
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T5,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T7,T10
DebounceSt->IdleSt	163	Covered	T38,T75,T209
DetectSt->IdleSt	186	Covered	T79,T180
DetectSt->StableSt	191	Covered	T5,T7,T10
IdleSt->DebounceSt	148	Covered	T5,T7,T10
StableSt->IdleSt	206	Covered	T5,T35,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T7,T10
0	1	Covered	T5,T7,T10
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T10
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T12,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T7,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T209,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T7,T10
DetectSt	-	-	-	-	1	-	-	Covered	T79,T180
DetectSt	-	-	-	-	0	1	-	Covered	T5,T7,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T35,T40
StableSt	-	-	-	-	-	-	0	Covered	T5,T7,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	147	0	0
CntIncr_A	8157508	55193	0	0
CntNoWrap_A	8157508	7532137	0	0
DetectStDropOut_A	8157508	2	0	0
DetectedOut_A	8157508	6709	0	0
DetectedPulseOut_A	8157508	70	0	0
DisabledIdleSt_A	8157508	7419415	0	0
DisabledNoDetection_A	8157508	7421611	0	0
EnterDebounceSt_A	8157508	78	0	0
EnterDetectSt_A	8157508	72	0	0
EnterStableSt_A	8157508	70	0	0
PulseIsPulse_A	8157508	70	0	0
StayInStableSt	8157508	6598	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	147	0	0
T5	826	4	0	0
T7	592	2	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	2	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	4	0	0
T38	0	2	0	0
T40	0	4	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	55193	0	0
T5	826	138	0	0
T7	592	28	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	47	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	14	0	0
T33	0	51	0	0
T34	0	41	0	0
T35	0	74	0	0
T38	0	3454	0	0
T40	0	128	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532137	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	421	0	0
T6	375494	375093	0	0
T7	592	189	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2	0	0
T79	807	1	0	0
T166	517	0	0	0
T167	502	0	0	0
T168	22959	0	0	0
T169	406	0	0	0
T170	452	0	0	0
T180	0	1	0	0
T210	502	0	0	0
T211	615	0	0	0
T212	40675	0	0	0
T213	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	6709	0	0
T5	826	165	0	0
T7	592	139	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	131	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	67	0	0
T33	0	43	0	0
T34	0	123	0	0
T35	0	217	0	0
T38	0	93	0	0
T40	0	261	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	70	0	0
T5	826	2	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T38	0	1	0	0
T40	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7419415	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	3	0	0
T6	375494	375093	0	0
T7	592	4	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7421611	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	3	0	0
T6	375494	375094	0	0
T7	592	4	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	78	0	0
T5	826	2	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	72	0	0
T5	826	2	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T38	0	1	0	0
T40	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	70	0	0
T5	826	2	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T38	0	1	0	0
T40	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	70	0	0
T5	826	2	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T38	0	1	0	0
T40	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	6598	0	0
T5	826	162	0	0
T7	592	137	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	129	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T32	0	65	0	0
T33	0	41	0	0
T34	0	122	0	0
T35	0	214	0	0
T38	0	92	0	0
T40	0	258	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	28	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	1	0	0
T171	0	2	0	0
T176	0	1	0	0
T193	0	2	0	0
T214	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T3
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T5,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T36,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T31,T48
1	0	Covered	T1,T12,T4
1	1	Covered	T5,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T36,T34
0	1	Covered	T171,T148
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T36,T34
0	1	Covered	T5,T142,T171
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T36,T34
1	-	Covered	T5,T142,T171

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T35,T36
DetectSt	168	Covered	T5,T36,T34
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T5,T36,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T36,T34
DebounceSt->IdleSt	163	Covered	T35,T75
DetectSt->IdleSt	186	Covered	T171,T148
DetectSt->StableSt	191	Covered	T5,T36,T34
IdleSt->DebounceSt	148	Covered	T5,T35,T36
StableSt->IdleSt	206	Covered	T5,T34,T142

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T35,T36
0	1	Covered	T5,T35,T36
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T36,T34
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T36,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T35
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T171,T148
DetectSt	-	-	-	-	0	1	-	Covered	T5,T36,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T142,T171
StableSt	-	-	-	-	-	-	0	Covered	T5,T36,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	68	0	0
CntIncr_A	8157508	1845	0	0
CntNoWrap_A	8157508	7532216	0	0
DetectStDropOut_A	8157508	2	0	0
DetectedOut_A	8157508	2353	0	0
DetectedPulseOut_A	8157508	31	0	0
DisabledIdleSt_A	8157508	7385051	0	0
DisabledNoDetection_A	8157508	7387258	0	0
EnterDebounceSt_A	8157508	35	0	0
EnterDetectSt_A	8157508	33	0	0
EnterStableSt_A	8157508	31	0	0
PulseIsPulse_A	8157508	31	0	0
StayInStableSt	8157508	2303	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8157508	6032	0	0
gen_low_level_sva.LowLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	68	0	0
T5	826	2	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T75	0	1	0	0
T142	0	2	0	0
T143	0	2	0	0
T146	0	2	0	0
T162	0	2	0	0
T181	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1845	0	0
T5	826	69	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	41	0	0
T35	0	37	0	0
T36	0	51	0	0
T42	10980	0	0	0
T51	409	0	0	0
T75	0	26	0	0
T142	0	55	0	0
T143	0	88	0	0
T146	0	83	0	0
T162	0	64	0	0
T181	0	55	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532216	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	423	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2	0	0
T76	24306	0	0	0
T148	0	1	0	0
T171	82727	1	0	0
T179	547	0	0	0
T183	402	0	0	0
T184	7329	0	0	0
T185	1031	0	0	0
T215	1050	0	0	0
T216	880	0	0	0
T217	418	0	0	0
T218	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2353	0	0
T5	826	43	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	213	0	0
T36	0	38	0	0
T42	10980	0	0	0
T51	409	0	0	0
T142	0	40	0	0
T143	0	43	0	0
T146	0	376	0	0
T162	0	121	0	0
T171	0	3	0	0
T181	0	40	0	0
T219	0	125	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	31	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0
T162	0	1	0	0
T171	0	1	0	0
T181	0	1	0	0
T219	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7385051	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	3	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7387258	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	3	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	35	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T75	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0
T162	0	1	0	0
T181	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	33	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0
T162	0	1	0	0
T171	0	2	0	0
T181	0	1	0	0
T219	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	31	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0
T162	0	1	0	0
T171	0	1	0	0
T181	0	1	0	0
T219	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	31	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0
T162	0	1	0	0
T171	0	1	0	0
T181	0	1	0	0
T219	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2303	0	0
T5	826	42	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	211	0	0
T36	0	36	0	0
T42	10980	0	0	0
T51	409	0	0	0
T142	0	39	0	0
T143	0	41	0	0
T146	0	374	0	0
T162	0	119	0	0
T171	0	2	0	0
T181	0	38	0	0
T219	0	123	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	6032	0	0
T1	7769	22	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	16	0	0
T5	826	1	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	22	0	0
T9	0	87	0	0
T12	15221	25	0	0
T13	2206	5	0	0
T14	9688	25	0	0
T22	0	6	0	0
T42	0	32	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	11	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T42	10980	0	0	0
T51	409	0	0	0
T142	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T171	0	1	0	0
T196	0	2	0	0
T220	0	1	0	0
T221	0	1	0	0
T222	0	1	0	0