Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T12,T3
1	1	Covered	T1,T12,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T31,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T5,T31,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T31,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T11,T31
1	0	Covered	T1,T12,T3
1	1	Covered	T5,T31,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T31,T35
0	1	Covered	T41,T182,T223
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T31,T35
0	1	Covered	T31,T35,T30
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T31,T35
1	-	Covered	T31,T35,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T31,T35
DetectSt	168	Covered	T5,T31,T35
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T5,T31,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T31,T35
DebounceSt->IdleSt	163	Covered	T38,T141,T75
DetectSt->IdleSt	186	Covered	T41,T182,T223
DetectSt->StableSt	191	Covered	T5,T31,T35
IdleSt->DebounceSt	148	Covered	T5,T31,T35
StableSt->IdleSt	206	Covered	T31,T35,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T31,T35
0	1	Covered	T5,T31,T35
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T31,T35
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T31,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T12,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T31,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T141,T182,T149
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T31,T35
DetectSt	-	-	-	-	1	-	-	Covered	T41,T182,T223
DetectSt	-	-	-	-	0	1	-	Covered	T5,T31,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T35,T30
StableSt	-	-	-	-	-	-	0	Covered	T5,T31,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	137	0	0
CntIncr_A	8157508	7365	0	0
CntNoWrap_A	8157508	7532147	0	0
DetectStDropOut_A	8157508	6	0	0
DetectedOut_A	8157508	5763	0	0
DetectedPulseOut_A	8157508	60	0	0
DisabledIdleSt_A	8157508	7424025	0	0
DisabledNoDetection_A	8157508	7426226	0	0
EnterDebounceSt_A	8157508	72	0	0
EnterDetectSt_A	8157508	66	0	0
EnterStableSt_A	8157508	60	0	0
PulseIsPulse_A	8157508	60	0	0
StayInStableSt	8157508	5674	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	137	0	0
T5	826	2	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	2	0	0
T31	0	4	0	0
T33	0	2	0	0
T35	0	4	0	0
T38	0	4	0	0
T39	0	2	0	0
T41	0	6	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	2	0	0
T198	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7365	0	0
T5	826	69	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	31	0	0
T31	0	116	0	0
T33	0	51	0	0
T35	0	74	0	0
T38	0	3507	0	0
T39	0	32	0	0
T41	0	251	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	64	0	0
T198	0	15	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532147	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	423	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	6	0	0
T41	14975	2	0	0
T113	1950	0	0	0
T142	1011	0	0	0
T153	12017	0	0	0
T154	19409	0	0	0
T155	17575	0	0	0
T156	402	0	0	0
T157	404	0	0	0
T158	404	0	0	0
T159	522	0	0	0
T180	0	1	0	0
T182	0	1	0	0
T221	0	1	0	0
T223	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	5763	0	0
T5	826	263	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	22	0	0
T31	0	372	0	0
T33	0	43	0	0
T35	0	62	0	0
T38	0	186	0	0
T39	0	99	0	0
T41	0	169	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	230	0	0
T198	0	57	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	60	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T33	0	1	0	0
T35	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	1	0	0
T198	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7424025	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	3	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7426226	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	3	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	72	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T33	0	1	0	0
T35	0	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T41	0	3	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	1	0	0
T198	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	66	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T33	0	1	0	0
T35	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	3	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	1	0	0
T198	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	60	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T33	0	1	0	0
T35	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	1	0	0
T198	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	60	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T33	0	1	0	0
T35	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	1	0	0
T198	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	5674	0	0
T5	826	261	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T30	0	21	0	0
T31	0	369	0	0
T33	0	41	0	0
T35	0	59	0	0
T38	0	184	0	0
T39	0	97	0	0
T41	0	167	0	0
T42	10980	0	0	0
T51	409	0	0	0
T162	0	228	0	0
T198	0	55	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	30	0	0
T30	0	1	0	0
T31	976	1	0	0
T35	0	1	0	0
T38	0	2	0	0
T45	597	0	0	0
T58	504	0	0	0
T59	491	0	0	0
T65	525	0	0	0
T66	522	0	0	0
T102	597	0	0	0
T103	422	0	0	0
T139	0	1	0	0
T142	0	2	0	0
T172	949	0	0	0
T173	818	0	0	0
T179	0	1	0	0
T193	0	1	0	0
T216	0	1	0	0
T224	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T3
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T35,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T35,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T35,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T35,T36
1	0	Covered	T1,T12,T3
1	1	Covered	T35,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Covered	T225
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Covered	T35,T142,T95
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T36,T37
1	-	Covered	T35,T142,T95

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T36,T37
DetectSt	168	Covered	T35,T36,T37
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T35,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T36,T37
DebounceSt->IdleSt	163	Covered	T75,T81,T161
DetectSt->IdleSt	186	Covered	T225
DetectSt->StableSt	191	Covered	T35,T36,T37
IdleSt->DebounceSt	148	Covered	T35,T36,T37
StableSt->IdleSt	206	Covered	T35,T37,T142

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T35,T36,T37
0	1	Covered	T35,T36,T37
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T37
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T161
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	1	-	-	Covered	T225
DetectSt	-	-	-	-	0	1	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T142,T95
StableSt	-	-	-	-	-	-	0	Covered	T35,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	70	0	0
CntIncr_A	8157508	2389	0	0
CntNoWrap_A	8157508	7532214	0	0
DetectStDropOut_A	8157508	1	0	0
DetectedOut_A	8157508	2668	0	0
DetectedPulseOut_A	8157508	33	0	0
DisabledIdleSt_A	8157508	7429283	0	0
DisabledNoDetection_A	8157508	7431499	0	0
EnterDebounceSt_A	8157508	37	0	0
EnterDetectSt_A	8157508	34	0	0
EnterStableSt_A	8157508	33	0	0
PulseIsPulse_A	8157508	33	0	0
StayInStableSt	8157508	2617	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8157508	5924	0	0
gen_low_level_sva.LowLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	70	0	0
T29	32422	0	0	0
T35	224924	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T39	540	0	0	0
T50	686	0	0	0
T72	221471	0	0	0
T73	2328	0	0	0
T75	0	1	0	0
T95	0	4	0	0
T142	0	4	0	0
T146	0	4	0	0
T171	0	2	0	0
T179	0	2	0	0
T226	0	2	0	0
T227	402	0	0	0
T228	407	0	0	0
T229	502	0	0	0
T230	424	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2389	0	0
T29	32422	0	0	0
T35	224924	37	0	0
T36	0	51	0	0
T37	0	62	0	0
T39	540	0	0	0
T50	686	0	0	0
T72	221471	0	0	0
T73	2328	0	0	0
T75	0	26	0	0
T95	0	192	0	0
T142	0	110	0	0
T146	0	166	0	0
T171	0	10	0	0
T179	0	47	0	0
T226	0	94	0	0
T227	402	0	0	0
T228	407	0	0	0
T229	502	0	0	0
T230	424	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532214	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1	0	0
T120	1752	0	0	0
T151	10842	0	0	0
T222	5606	0	0	0
T225	13772	1	0	0
T231	402	0	0	0
T232	1326	0	0	0
T233	511	0	0	0
T234	17202	0	0	0
T235	443133	0	0	0
T236	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2668	0	0
T29	32422	0	0	0
T35	224924	187	0	0
T36	0	38	0	0
T37	0	46	0	0
T39	540	0	0	0
T50	686	0	0	0
T72	221471	0	0	0
T73	2328	0	0	0
T95	0	267	0	0
T142	0	286	0	0
T146	0	293	0	0
T171	0	55	0	0
T179	0	42	0	0
T182	0	14	0	0
T226	0	37	0	0
T227	402	0	0	0
T228	407	0	0	0
T229	502	0	0	0
T230	424	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	33	0	0
T29	32422	0	0	0
T35	224924	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	540	0	0	0
T50	686	0	0	0
T72	221471	0	0	0
T73	2328	0	0	0
T95	0	2	0	0
T142	0	2	0	0
T146	0	2	0	0
T171	0	1	0	0
T179	0	1	0	0
T182	0	1	0	0
T226	0	1	0	0
T227	402	0	0	0
T228	407	0	0	0
T229	502	0	0	0
T230	424	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7429283	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	3	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7431499	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	3	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	37	0	0
T29	32422	0	0	0
T35	224924	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	540	0	0	0
T50	686	0	0	0
T72	221471	0	0	0
T73	2328	0	0	0
T75	0	1	0	0
T95	0	2	0	0
T142	0	2	0	0
T146	0	2	0	0
T171	0	1	0	0
T179	0	1	0	0
T226	0	1	0	0
T227	402	0	0	0
T228	407	0	0	0
T229	502	0	0	0
T230	424	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	34	0	0
T29	32422	0	0	0
T35	224924	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	540	0	0	0
T50	686	0	0	0
T72	221471	0	0	0
T73	2328	0	0	0
T95	0	2	0	0
T142	0	2	0	0
T146	0	2	0	0
T171	0	1	0	0
T179	0	1	0	0
T182	0	1	0	0
T226	0	1	0	0
T227	402	0	0	0
T228	407	0	0	0
T229	502	0	0	0
T230	424	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	33	0	0
T29	32422	0	0	0
T35	224924	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	540	0	0	0
T50	686	0	0	0
T72	221471	0	0	0
T73	2328	0	0	0
T95	0	2	0	0
T142	0	2	0	0
T146	0	2	0	0
T171	0	1	0	0
T179	0	1	0	0
T182	0	1	0	0
T226	0	1	0	0
T227	402	0	0	0
T228	407	0	0	0
T229	502	0	0	0
T230	424	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	33	0	0
T29	32422	0	0	0
T35	224924	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	540	0	0	0
T50	686	0	0	0
T72	221471	0	0	0
T73	2328	0	0	0
T95	0	2	0	0
T142	0	2	0	0
T146	0	2	0	0
T171	0	1	0	0
T179	0	1	0	0
T182	0	1	0	0
T226	0	1	0	0
T227	402	0	0	0
T228	407	0	0	0
T229	502	0	0	0
T230	424	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2617	0	0
T29	32422	0	0	0
T35	224924	186	0	0
T36	0	36	0	0
T37	0	44	0	0
T39	540	0	0	0
T50	686	0	0	0
T72	221471	0	0	0
T73	2328	0	0	0
T95	0	264	0	0
T142	0	283	0	0
T146	0	290	0	0
T171	0	53	0	0
T179	0	40	0	0
T182	0	13	0	0
T226	0	35	0	0
T227	402	0	0	0
T228	407	0	0	0
T229	502	0	0	0
T230	424	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	5924	0	0
T1	7769	26	0	0
T2	1045	0	0	0
T3	500	1	0	0
T4	19047	18	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	1	0	0
T8	0	23	0	0
T9	0	79	0	0
T12	15221	26	0	0
T13	2206	7	0	0
T14	9688	26	0	0
T42	0	32	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	14	0	0
T29	32422	0	0	0
T35	224924	1	0	0
T39	540	0	0	0
T50	686	0	0	0
T72	221471	0	0	0
T73	2328	0	0	0
T95	0	1	0	0
T142	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T161	0	1	0	0
T180	0	2	0	0
T182	0	1	0	0
T227	402	0	0	0
T228	407	0	0	0
T229	502	0	0	0
T230	424	0	0	0
T237	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T12,T3
1	1	Covered	T1,T12,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T10,T39,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T10,T39,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T10,T39,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T39,T36
1	0	Covered	T1,T12,T3
1	1	Covered	T10,T39,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T39,T36
0	1	Covered	T179,T151
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T39,T36
0	1	Covered	T10,T39,T139
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T39,T36
1	-	Covered	T10,T39,T139

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T39,T36
DetectSt	168	Covered	T10,T39,T36
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T10,T39,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T39,T36
DebounceSt->IdleSt	163	Covered	T192,T75,T238
DetectSt->IdleSt	186	Covered	T179,T151
DetectSt->StableSt	191	Covered	T10,T39,T36
IdleSt->DebounceSt	148	Covered	T10,T39,T36
StableSt->IdleSt	206	Covered	T10,T39,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T39,T36
0	1	Covered	T10,T39,T36
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T39,T36
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T39,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T12,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T39,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T192,T238,T140
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T39,T36
DetectSt	-	-	-	-	1	-	-	Covered	T179,T151
DetectSt	-	-	-	-	0	1	-	Covered	T10,T39,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T39,T139
StableSt	-	-	-	-	-	-	0	Covered	T10,T39,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	110	0	0
CntIncr_A	8157508	61976	0	0
CntNoWrap_A	8157508	7532174	0	0
DetectStDropOut_A	8157508	2	0	0
DetectedOut_A	8157508	33015	0	0
DetectedPulseOut_A	8157508	51	0	0
DisabledIdleSt_A	8157508	7315625	0	0
DisabledNoDetection_A	8157508	7317840	0	0
EnterDebounceSt_A	8157508	57	0	0
EnterDetectSt_A	8157508	53	0	0
EnterStableSt_A	8157508	51	0	0
PulseIsPulse_A	8157508	51	0	0
StayInStableSt	8157508	32938	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	110	0	0
T10	726	4	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	2	0	0
T33	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T39	0	2	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T139	0	4	0	0
T141	0	2	0	0
T143	0	2	0	0
T145	402	0	0	0
T197	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	61976	0	0
T10	726	94	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	31	0	0
T33	0	51	0	0
T36	0	51	0	0
T37	0	62	0	0
T39	0	32	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T139	0	84	0	0
T141	0	23	0	0
T143	0	88	0	0
T145	402	0	0	0
T197	0	26	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532174	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2	0	0
T151	0	1	0	0
T179	547	1	0	0
T183	402	0	0	0
T184	7329	0	0	0
T185	1031	0	0	0
T186	426	0	0	0
T187	529	0	0	0
T188	1303	0	0	0
T189	10816	0	0	0
T190	402	0	0	0
T191	489	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	33015	0	0
T10	726	134	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	209	0	0
T33	0	42	0	0
T36	0	39	0	0
T37	0	108	0	0
T39	0	21	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T139	0	114	0	0
T141	0	62	0	0
T143	0	191	0	0
T145	402	0	0	0
T197	0	70	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	51	0	0
T10	726	2	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T139	0	2	0	0
T141	0	1	0	0
T143	0	1	0	0
T145	402	0	0	0
T197	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7315625	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7317840	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	57	0	0
T10	726	2	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T139	0	2	0	0
T141	0	1	0	0
T143	0	1	0	0
T145	402	0	0	0
T197	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	53	0	0
T10	726	2	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T139	0	2	0	0
T141	0	1	0	0
T143	0	1	0	0
T145	402	0	0	0
T197	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	51	0	0
T10	726	2	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T139	0	2	0	0
T141	0	1	0	0
T143	0	1	0	0
T145	402	0	0	0
T197	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	51	0	0
T10	726	2	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T139	0	2	0	0
T141	0	1	0	0
T143	0	1	0	0
T145	402	0	0	0
T197	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	32938	0	0
T10	726	131	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T30	0	207	0	0
T33	0	40	0	0
T36	0	37	0	0
T37	0	106	0	0
T39	0	20	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T139	0	111	0	0
T141	0	60	0	0
T143	0	190	0	0
T145	402	0	0	0
T197	0	68	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	24	0	0
T10	726	1	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T39	0	1	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T139	0	1	0	0
T143	0	1	0	0
T145	402	0	0	0
T146	0	1	0	0
T171	0	1	0	0
T175	0	2	0	0
T176	0	1	0	0
T216	0	1	0	0
T219	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T3
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T10,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T5,T10,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T5,T10,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T48
1	0	Covered	T1,T12,T4
1	1	Covered	T5,T10,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T34
0	1	Covered	T10,T38,T142
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T10,T34
1	-	Covered	T10,T38,T142

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T10,T34
DetectSt	168	Covered	T5,T10,T34
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T5,T10,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T10,T34
DebounceSt->IdleSt	163	Covered	T75,T151
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T5,T10,T34
IdleSt->DebounceSt	148	Covered	T5,T10,T34
StableSt->IdleSt	206	Covered	T10,T34,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T10,T34
0	1	Covered	T5,T10,T34
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T34
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T10,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T10,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T151
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T10,T34
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T5,T10,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T38,T142
StableSt	-	-	-	-	-	-	0	Covered	T5,T10,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	88	0	0
CntIncr_A	8157508	46086	0	0
CntNoWrap_A	8157508	7532196	0	0
DetectStDropOut_A	8157508	0	0	0
DetectedOut_A	8157508	3820	0	0
DetectedPulseOut_A	8157508	43	0	0
DisabledIdleSt_A	8157508	7423905	0	0
DisabledNoDetection_A	8157508	7426113	0	0
EnterDebounceSt_A	8157508	45	0	0
EnterDetectSt_A	8157508	43	0	0
EnterStableSt_A	8157508	43	0	0
PulseIsPulse_A	8157508	43	0	0
StayInStableSt	8157508	3753	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8157508	5951	0	0
gen_low_level_sva.LowLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	88	0	0
T5	826	2	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	2	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	2	0	0
T38	0	4	0	0
T42	10980	0	0	0
T51	409	0	0	0
T75	0	1	0	0
T139	0	2	0	0
T141	0	2	0	0
T142	0	2	0	0
T144	0	2	0	0
T162	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	46086	0	0
T5	826	69	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	47	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	41	0	0
T38	0	106	0	0
T42	10980	0	0	0
T51	409	0	0	0
T75	0	28	0	0
T139	0	42	0	0
T141	0	84	0	0
T142	0	55	0	0
T144	0	65	0	0
T162	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532196	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	423	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	3820	0	0
T5	826	150	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	39	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	127	0	0
T38	0	124	0	0
T42	10980	0	0	0
T51	409	0	0	0
T139	0	40	0	0
T141	0	38	0	0
T142	0	44	0	0
T144	0	44	0	0
T146	0	376	0	0
T162	0	122	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	43	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	1	0	0
T38	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T139	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T162	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7423905	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	3	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7426113	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	3	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	45	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	1	0	0
T38	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T75	0	1	0	0
T139	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T144	0	1	0	0
T162	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	43	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	1	0	0
T38	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T139	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T162	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	43	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	1	0	0
T38	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T139	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T162	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	43	0	0
T5	826	1	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	1	0	0
T38	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T139	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T162	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	3753	0	0
T5	826	148	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	38	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T34	0	125	0	0
T38	0	121	0	0
T42	10980	0	0	0
T51	409	0	0	0
T139	0	39	0	0
T141	0	36	0	0
T142	0	43	0	0
T144	0	42	0	0
T146	0	374	0	0
T162	0	120	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	5951	0	0
T1	7769	26	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	14	0	0
T5	826	1	0	0
T6	375494	0	0	0
T7	592	1	0	0
T8	0	27	0	0
T9	0	79	0	0
T12	15221	36	0	0
T13	2206	6	0	0
T14	9688	24	0	0
T42	0	30	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	18	0	0
T10	726	1	0	0
T20	490	0	0	0
T22	502	0	0	0
T24	688	0	0	0
T38	0	1	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T64	525	0	0	0
T139	0	1	0	0
T142	0	1	0	0
T145	402	0	0	0
T147	0	1	0	0
T149	0	2	0	0
T180	0	1	0	0
T182	0	1	0	0
T193	0	1	0	0
T239	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T7,T11,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T7,T11,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T7,T11,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T31
1	0	Covered	T1,T2,T6
1	1	Covered	T7,T11,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T31
0	1	Covered	T151
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T31
0	1	Covered	T31,T40,T34
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T11,T31
1	-	Covered	T31,T40,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T11,T31
DetectSt	168	Covered	T7,T11,T31
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T7,T11,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T11,T31
DebounceSt->IdleSt	163	Covered	T7,T37,T30
DetectSt->IdleSt	186	Covered	T151
DetectSt->StableSt	191	Covered	T7,T11,T31
IdleSt->DebounceSt	148	Covered	T7,T11,T31
StableSt->IdleSt	206	Covered	T31,T40,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T11,T31
0	1	Covered	T7,T11,T31
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T31
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T11,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T11,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T37,T30
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T11,T31
DetectSt	-	-	-	-	1	-	-	Covered	T151
DetectSt	-	-	-	-	0	1	-	Covered	T7,T11,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T40,T34
StableSt	-	-	-	-	-	-	0	Covered	T7,T11,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	98	0	0
CntIncr_A	8157508	6274	0	0
CntNoWrap_A	8157508	7532186	0	0
DetectStDropOut_A	8157508	1	0	0
DetectedOut_A	8157508	3922	0	0
DetectedPulseOut_A	8157508	45	0	0
DisabledIdleSt_A	8157508	7511605	0	0
DisabledNoDetection_A	8157508	7513817	0	0
EnterDebounceSt_A	8157508	53	0	0
EnterDetectSt_A	8157508	46	0	0
EnterStableSt_A	8157508	45	0	0
PulseIsPulse_A	8157508	45	0	0
StayInStableSt	8157508	3859	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	98	0	0
T7	592	3	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	2	0	0
T14	9688	0	0	0
T22	502	0	0	0
T23	697	0	0	0
T30	0	3	0	0
T31	0	4	0	0
T34	0	2	0	0
T37	0	1	0	0
T40	0	4	0	0
T41	0	4	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T141	0	1	0	0
T162	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	6274	0	0
T7	592	56	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	19	0	0
T14	9688	0	0	0
T22	502	0	0	0
T23	697	0	0	0
T30	0	93	0	0
T31	0	116	0	0
T34	0	41	0	0
T37	0	62	0	0
T38	0	3400	0	0
T40	0	128	0	0
T41	0	130	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T162	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532186	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	188	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1	0	0
T120	1752	0	0	0
T151	10842	1	0	0
T222	5606	0	0	0
T232	1326	0	0	0
T233	511	0	0	0
T234	17202	0	0	0
T235	443133	0	0	0
T236	493	0	0	0
T240	37807	0	0	0
T241	528	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	3922	0	0
T7	592	41	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	59	0	0
T14	9688	0	0	0
T22	502	0	0	0
T23	697	0	0	0
T30	0	40	0	0
T31	0	375	0	0
T34	0	123	0	0
T40	0	153	0	0
T41	0	64	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T162	0	121	0	0
T175	0	237	0	0
T242	0	68	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	45	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	1	0	0
T14	9688	0	0	0
T22	502	0	0	0
T23	697	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T34	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T162	0	1	0	0
T175	0	2	0	0
T242	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7511605	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	4	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7513817	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	4	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	53	0	0
T7	592	2	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	1	0	0
T14	9688	0	0	0
T22	502	0	0	0
T23	697	0	0	0
T30	0	2	0	0
T31	0	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T162	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	46	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	1	0	0
T14	9688	0	0	0
T22	502	0	0	0
T23	697	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T34	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T162	0	1	0	0
T175	0	2	0	0
T242	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	45	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	1	0	0
T14	9688	0	0	0
T22	502	0	0	0
T23	697	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T34	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T162	0	1	0	0
T175	0	2	0	0
T242	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	45	0	0
T7	592	1	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	1	0	0
T14	9688	0	0	0
T22	502	0	0	0
T23	697	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T34	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T162	0	1	0	0
T175	0	2	0	0
T242	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	3859	0	0
T7	592	39	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T10	726	0	0	0
T11	0	57	0	0
T14	9688	0	0	0
T22	502	0	0	0
T23	697	0	0	0
T30	0	38	0	0
T31	0	372	0	0
T34	0	122	0	0
T40	0	151	0	0
T41	0	62	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T162	0	119	0	0
T175	0	234	0	0
T242	0	66	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	26	0	0
T31	976	1	0	0
T34	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T45	597	0	0	0
T58	504	0	0	0
T59	491	0	0	0
T65	525	0	0	0
T66	522	0	0	0
T102	597	0	0	0
T103	422	0	0	0
T172	949	0	0	0
T173	818	0	0	0
T175	0	1	0	0
T193	0	1	0	0
T196	0	2	0	0
T216	0	1	0	0
T219	0	1	0	0
T224	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T31,T32,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T31,T32,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T31,T32,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T31,T48
1	0	Covered	T1,T2,T6
1	1	Covered	T31,T32,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T33
0	1	Covered	T38,T41
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T33
0	1	Covered	T31,T175,T95
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T32,T33
1	-	Covered	T31,T175,T95

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T31,T32,T33
DetectSt	168	Covered	T31,T32,T33
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T31,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T32,T33
DebounceSt->IdleSt	163	Covered	T75,T81,T239
DetectSt->IdleSt	186	Covered	T38,T41
DetectSt->StableSt	191	Covered	T31,T32,T33
IdleSt->DebounceSt	148	Covered	T31,T32,T33
StableSt->IdleSt	206	Covered	T31,T38,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T31,T32,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T32,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T239,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T32,T33
DetectSt	-	-	-	-	1	-	-	Covered	T38,T41
DetectSt	-	-	-	-	0	1	-	Covered	T31,T32,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T175,T95
StableSt	-	-	-	-	-	-	0	Covered	T31,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	67	0	0
CntIncr_A	8157508	2613	0	0
CntNoWrap_A	8157508	7532217	0	0
DetectStDropOut_A	8157508	2	0	0
DetectedOut_A	8157508	2401	0	0
DetectedPulseOut_A	8157508	30	0	0
DisabledIdleSt_A	8157508	7346208	0	0
DisabledNoDetection_A	8157508	7348415	0	0
EnterDebounceSt_A	8157508	37	0	0
EnterDetectSt_A	8157508	32	0	0
EnterStableSt_A	8157508	30	0	0
PulseIsPulse_A	8157508	30	0	0
StayInStableSt	8157508	2354	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8157508	6611	0	0
gen_low_level_sva.LowLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	67	0	0
T31	976	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T38	0	4	0	0
T41	0	4	0	0
T45	597	0	0	0
T58	504	0	0	0
T59	491	0	0	0
T65	525	0	0	0
T66	522	0	0	0
T75	0	1	0	0
T79	0	2	0	0
T95	0	2	0	0
T102	597	0	0	0
T103	422	0	0	0
T142	0	2	0	0
T172	949	0	0	0
T173	818	0	0	0
T175	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2613	0	0
T31	976	58	0	0
T32	0	14	0	0
T33	0	51	0	0
T38	0	106	0	0
T41	0	186	0	0
T45	597	0	0	0
T58	504	0	0	0
T59	491	0	0	0
T65	525	0	0	0
T66	522	0	0	0
T75	0	27	0	0
T79	0	76	0	0
T95	0	96	0	0
T102	597	0	0	0
T103	422	0	0	0
T142	0	55	0	0
T172	949	0	0	0
T173	818	0	0	0
T175	0	85	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7532217	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2	0	0
T38	6935	1	0	0
T41	0	1	0	0
T162	802	0	0	0
T201	424	0	0	0
T202	555	0	0	0
T203	503	0	0	0
T204	408	0	0	0
T205	418	0	0	0
T206	36233	0	0	0
T207	408	0	0	0
T208	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2401	0	0
T31	976	16	0	0
T32	0	43	0	0
T33	0	42	0	0
T38	0	30	0	0
T41	0	199	0	0
T45	597	0	0	0
T58	504	0	0	0
T59	491	0	0	0
T65	525	0	0	0
T66	522	0	0	0
T79	0	46	0	0
T95	0	137	0	0
T102	597	0	0	0
T103	422	0	0	0
T142	0	40	0	0
T171	0	84	0	0
T172	949	0	0	0
T173	818	0	0	0
T175	0	162	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	30	0	0
T31	976	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T45	597	0	0	0
T58	504	0	0	0
T59	491	0	0	0
T65	525	0	0	0
T66	522	0	0	0
T79	0	1	0	0
T95	0	1	0	0
T102	597	0	0	0
T103	422	0	0	0
T142	0	1	0	0
T171	0	2	0	0
T172	949	0	0	0
T173	818	0	0	0
T175	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7346208	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7348415	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	37	0	0
T31	976	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	2	0	0
T41	0	2	0	0
T45	597	0	0	0
T58	504	0	0	0
T59	491	0	0	0
T65	525	0	0	0
T66	522	0	0	0
T75	0	1	0	0
T79	0	1	0	0
T95	0	1	0	0
T102	597	0	0	0
T103	422	0	0	0
T142	0	1	0	0
T172	949	0	0	0
T173	818	0	0	0
T175	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	32	0	0
T31	976	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	2	0	0
T41	0	2	0	0
T45	597	0	0	0
T58	504	0	0	0
T59	491	0	0	0
T65	525	0	0	0
T66	522	0	0	0
T79	0	1	0	0
T95	0	1	0	0
T102	597	0	0	0
T103	422	0	0	0
T142	0	1	0	0
T171	0	2	0	0
T172	949	0	0	0
T173	818	0	0	0
T175	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	30	0	0
T31	976	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T45	597	0	0	0
T58	504	0	0	0
T59	491	0	0	0
T65	525	0	0	0
T66	522	0	0	0
T79	0	1	0	0
T95	0	1	0	0
T102	597	0	0	0
T103	422	0	0	0
T142	0	1	0	0
T171	0	2	0	0
T172	949	0	0	0
T173	818	0	0	0
T175	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	30	0	0
T31	976	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T45	597	0	0	0
T58	504	0	0	0
T59	491	0	0	0
T65	525	0	0	0
T66	522	0	0	0
T79	0	1	0	0
T95	0	1	0	0
T102	597	0	0	0
T103	422	0	0	0
T142	0	1	0	0
T171	0	2	0	0
T172	949	0	0	0
T173	818	0	0	0
T175	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2354	0	0
T31	976	15	0	0
T32	0	41	0	0
T33	0	40	0	0
T38	0	28	0	0
T41	0	197	0	0
T45	597	0	0	0
T58	504	0	0	0
T59	491	0	0	0
T65	525	0	0	0
T66	522	0	0	0
T79	0	44	0	0
T95	0	136	0	0
T102	597	0	0	0
T103	422	0	0	0
T142	0	38	0	0
T171	0	81	0	0
T172	949	0	0	0
T173	818	0	0	0
T175	0	161	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	6611	0	0
T1	7769	25	0	0
T2	1045	4	0	0
T3	500	0	0	0
T4	19047	19	0	0
T5	826	1	0	0
T6	375494	5	0	0
T7	592	1	0	0
T8	0	36	0	0
T12	15221	27	0	0
T13	2206	10	0	0
T14	9688	30	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	12	0	0
T31	976	1	0	0
T45	597	0	0	0
T58	504	0	0	0
T59	491	0	0	0
T65	525	0	0	0
T66	522	0	0	0
T95	0	1	0	0
T102	597	0	0	0
T103	422	0	0	0
T151	0	1	0	0
T171	0	1	0	0
T172	949	0	0	0
T173	818	0	0	0
T175	0	1	0	0
T178	0	1	0	0
T182	0	2	0	0
T214	0	1	0	0
T220	0	2	0	0
T243	0	1	0	0