Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T14
1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T14
1	0	Covered	T1,T12,T14
1	1	Covered	T1,T12,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T3
0	1	Covered	T1,T68,T69
1	0	Covered	T1,T75,T97

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T3,T14
0	1	Covered	T12,T14,T8
1	0	Covered	T75,T76,T127

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T3,T14
1	-	Covered	T12,T14,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T3
DetectSt	168	Covered	T1,T12,T3
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T12,T3,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T3
DebounceSt->IdleSt	163	Covered	T92,T75,T56
DetectSt->IdleSt	186	Covered	T1,T68,T69
DetectSt->StableSt	191	Covered	T12,T3,T14
IdleSt->DebounceSt	148	Covered	T1,T12,T3
StableSt->IdleSt	206	Covered	T12,T14,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T12,T3
0	1	Covered	T1,T12,T3
0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T12,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T92,T75,T56
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T3
DetectSt	-	-	-	-	1	-	-	Covered	T1,T68,T69
DetectSt	-	-	-	-	0	1	-	Covered	T12,T3,T14
DetectSt	-	-	-	-	0	0	-	Covered	T1,T12,T3
StableSt	-	-	-	-	-	-	1	Covered	T12,T14,T8
StableSt	-	-	-	-	-	-	0	Covered	T12,T3,T14
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	3229	0	0
CntIncr_A	8157508	111133	0	0
CntNoWrap_A	8157508	7529055	0	0
DetectStDropOut_A	8157508	381	0	0
DetectedOut_A	8157508	108993	0	0
DetectedPulseOut_A	8157508	1092	0	0
DisabledIdleSt_A	8157508	7027242	0	0
DisabledNoDetection_A	8157508	7029251	0	0
EnterDebounceSt_A	8157508	1619	0	0
EnterDetectSt_A	8157508	1610	0	0
EnterStableSt_A	8157508	1092	0	0
PulseIsPulse_A	8157508	1092	0	0
StayInStableSt	8157508	107741	0	0
gen_high_event_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	913	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	3229	0	0
T1	7769	26	0	0
T2	1045	0	0	0
T3	500	2	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	20	0	0
T12	15221	22	0	0
T13	2206	0	0	0
T14	9688	8	0	0
T29	0	22	0	0
T42	0	34	0	0
T68	0	24	0	0
T69	0	30	0	0
T70	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	111133	0	0
T1	7769	453	0	0
T2	1045	0	0	0
T3	500	21	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	510	0	0
T12	15221	649	0	0
T13	2206	0	0	0
T14	9688	312	0	0
T29	0	759	0	0
T42	0	1224	0	0
T68	0	557	0	0
T69	0	877	0	0
T70	0	1305	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7529055	0	0
T1	7769	7334	0	0
T2	1045	644	0	0
T3	500	97	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14776	0	0
T13	2206	603	0	0
T14	9688	9279	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	381	0	0
T1	7769	7	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T68	0	12	0	0
T69	0	15	0	0
T75	0	1	0	0
T91	0	17	0	0
T92	0	6	0	0
T94	0	13	0	0
T96	0	3	0	0
T97	0	12	0	0
T244	0	22	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	108993	0	0
T3	500	74	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	1049	0	0
T9	22998	0	0	0
T12	15221	595	0	0
T13	2206	0	0	0
T14	9688	147	0	0
T23	697	0	0	0
T29	0	2839	0	0
T42	0	949	0	0
T70	0	2472	0	0
T71	0	2145	0	0
T108	0	1319	0	0
T245	0	867	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1092	0	0
T3	500	1	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	10	0	0
T9	22998	0	0	0
T12	15221	11	0	0
T13	2206	0	0	0
T14	9688	4	0	0
T23	697	0	0	0
T29	0	11	0	0
T42	0	17	0	0
T70	0	15	0	0
T71	0	24	0	0
T108	0	24	0	0
T245	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7027242	0	0
T1	7769	5404	0	0
T2	1045	644	0	0
T3	500	4	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	9352	0	0
T13	2206	603	0	0
T14	9688	3466	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7029251	0	0
T1	7769	5405	0	0
T2	1045	645	0	0
T3	500	4	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	9354	0	0
T13	2206	606	0	0
T14	9688	3466	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1619	0	0
T1	7769	13	0	0
T2	1045	0	0	0
T3	500	1	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	10	0	0
T12	15221	11	0	0
T13	2206	0	0	0
T14	9688	4	0	0
T29	0	11	0	0
T42	0	17	0	0
T68	0	12	0	0
T69	0	15	0	0
T70	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1610	0	0
T1	7769	13	0	0
T2	1045	0	0	0
T3	500	1	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	10	0	0
T12	15221	11	0	0
T13	2206	0	0	0
T14	9688	4	0	0
T29	0	11	0	0
T42	0	17	0	0
T68	0	12	0	0
T69	0	15	0	0
T70	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1092	0	0
T3	500	1	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	10	0	0
T9	22998	0	0	0
T12	15221	11	0	0
T13	2206	0	0	0
T14	9688	4	0	0
T23	697	0	0	0
T29	0	11	0	0
T42	0	17	0	0
T70	0	15	0	0
T71	0	24	0	0
T108	0	24	0	0
T245	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1092	0	0
T3	500	1	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	10	0	0
T9	22998	0	0	0
T12	15221	11	0	0
T13	2206	0	0	0
T14	9688	4	0	0
T23	697	0	0	0
T29	0	11	0	0
T42	0	17	0	0
T70	0	15	0	0
T71	0	24	0	0
T108	0	24	0	0
T245	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	107741	0	0
T3	500	72	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	1039	0	0
T9	22998	0	0	0
T12	15221	583	0	0
T13	2206	0	0	0
T14	9688	143	0	0
T23	697	0	0	0
T29	0	2822	0	0
T42	0	932	0	0
T70	0	2457	0	0
T71	0	2121	0	0
T108	0	1293	0	0
T245	0	844	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	913	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	10	0	0
T9	22998	0	0	0
T12	15221	10	0	0
T13	2206	0	0	0
T14	9688	4	0	0
T23	697	0	0	0
T29	0	5	0	0
T42	0	17	0	0
T70	0	15	0	0
T71	0	24	0	0
T108	0	22	0	0
T245	0	23	0	0
T246	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T3
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T3,T4,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T3,T4,T13

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T3,T4,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T3,T4
1	0	Covered	T1,T12,T4
1	1	Covered	T3,T4,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T8
0	1	Covered	T86,T87,T37
1	0	Covered	T75,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T8
0	1	Covered	T3,T4,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T8
1	-	Covered	T3,T4,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T13
DetectSt	168	Covered	T3,T4,T8
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T3,T4,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T8
DebounceSt->IdleSt	163	Covered	T13,T9,T44
DetectSt->IdleSt	186	Covered	T86,T87,T37
DetectSt->StableSt	191	Covered	T3,T4,T8
IdleSt->DebounceSt	148	Covered	T3,T4,T13
StableSt->IdleSt	206	Covered	T3,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T13
0	1	Covered	T3,T4,T13
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T13
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T9,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T13
DetectSt	-	-	-	-	1	-	-	Covered	T86,T87,T37
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T8
DetectSt	-	-	-	-	0	0	-	Covered	T3,T4,T8
StableSt	-	-	-	-	-	-	1	Covered	T3,T4,T8
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	1107	0	0
CntIncr_A	8157508	57423	0	0
CntNoWrap_A	8157508	7531177	0	0
DetectStDropOut_A	8157508	112	0	0
DetectedOut_A	8157508	16474	0	0
DetectedPulseOut_A	8157508	396	0	0
DisabledIdleSt_A	8157508	7134360	0	0
DisabledNoDetection_A	8157508	7135882	0	0
EnterDebounceSt_A	8157508	597	0	0
EnterDetectSt_A	8157508	512	0	0
EnterStableSt_A	8157508	396	0	0
PulseIsPulse_A	8157508	396	0	0
StayInStableSt	8157508	16026	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	342	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1107	0	0
T3	500	2	0	0
T4	19047	2	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	4	0	0
T9	22998	6	0	0
T13	2206	1	0	0
T14	9688	0	0	0
T23	697	0	0	0
T27	0	19	0	0
T28	0	2	0	0
T29	0	12	0	0
T44	0	5	0	0
T48	0	2	0	0
T51	409	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	57423	0	0
T3	500	25	0	0
T4	19047	127	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	74	0	0
T9	22998	239	0	0
T13	2206	20	0	0
T14	9688	0	0	0
T23	697	0	0	0
T27	0	1592	0	0
T28	0	244	0	0
T29	0	492	0	0
T44	0	348	0	0
T48	0	25	0	0
T51	409	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7531177	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	97	0	0
T4	19047	17800	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	602	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	112	0	0
T32	491	0	0	0
T36	551	0	0	0
T37	0	3	0	0
T70	11656	0	0	0
T71	8613	0	0	0
T86	22896	6	0	0
T87	19252	1	0	0
T88	0	1	0	0
T89	0	8	0	0
T90	0	12	0	0
T93	0	1	0	0
T95	0	5	0	0
T98	0	10	0	0
T99	0	1	0	0
T104	494	0	0	0
T105	493	0	0	0
T106	460	0	0	0
T107	750	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	16474	0	0
T3	500	5	0	0
T4	19047	25	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	134	0	0
T9	22998	8	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T27	0	55	0	0
T28	0	8	0	0
T29	0	403	0	0
T44	0	10	0	0
T48	0	4	0	0
T51	409	0	0	0
T108	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	396	0	0
T3	500	1	0	0
T4	19047	1	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	2	0	0
T9	22998	2	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	6	0	0
T44	0	2	0	0
T48	0	1	0	0
T51	409	0	0	0
T108	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7134360	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	26	0	0
T4	19047	14222	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14204	0	0
T13	2206	556	0	0
T14	9688	9140	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7135882	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	26	0	0
T4	19047	14223	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14207	0	0
T13	2206	558	0	0
T14	9688	9141	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	597	0	0
T3	500	1	0	0
T4	19047	1	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	2	0	0
T9	22998	4	0	0
T13	2206	1	0	0
T14	9688	0	0	0
T23	697	0	0	0
T27	0	10	0	0
T28	0	1	0	0
T29	0	6	0	0
T44	0	3	0	0
T48	0	1	0	0
T51	409	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	512	0	0
T3	500	1	0	0
T4	19047	1	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	2	0	0
T9	22998	2	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	6	0	0
T44	0	2	0	0
T48	0	1	0	0
T51	409	0	0	0
T86	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	396	0	0
T3	500	1	0	0
T4	19047	1	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	2	0	0
T9	22998	2	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	6	0	0
T44	0	2	0	0
T48	0	1	0	0
T51	409	0	0	0
T108	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	396	0	0
T3	500	1	0	0
T4	19047	1	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	2	0	0
T9	22998	2	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	6	0	0
T44	0	2	0	0
T48	0	1	0	0
T51	409	0	0	0
T108	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	16026	0	0
T3	500	4	0	0
T4	19047	24	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	132	0	0
T9	22998	6	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T27	0	46	0	0
T28	0	7	0	0
T29	0	397	0	0
T44	0	8	0	0
T48	0	3	0	0
T51	409	0	0	0
T108	0	76	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	342	0	0
T3	500	1	0	0
T4	19047	1	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	2	0	0
T9	22998	2	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T27	0	9	0	0
T28	0	1	0	0
T29	0	6	0	0
T44	0	2	0	0
T48	0	1	0	0
T51	409	0	0	0
T108	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T14
1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T14
1	0	Covered	T1,T12,T14
1	1	Covered	T1,T12,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T14
0	1	Covered	T1,T8,T29
1	0	Covered	T1,T8,T29

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T42
0	1	Covered	T12,T14,T42
1	0	Covered	T71,T75,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T14,T42
1	-	Covered	T12,T14,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T14
DetectSt	168	Covered	T1,T12,T14
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T12,T14,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T14
DebounceSt->IdleSt	163	Covered	T92,T75,T56
DetectSt->IdleSt	186	Covered	T1,T8,T29
DetectSt->StableSt	191	Covered	T12,T14,T42
IdleSt->DebounceSt	148	Covered	T1,T12,T14
StableSt->IdleSt	206	Covered	T12,T14,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T12,T14
0	1	Covered	T1,T12,T14
0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T14
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T14
IdleSt	0	-	-	-	-	-	-	Covered	T1,T12,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T92,T75,T56
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T14
DetectSt	-	-	-	-	1	-	-	Covered	T1,T8,T29
DetectSt	-	-	-	-	0	1	-	Covered	T12,T14,T42
DetectSt	-	-	-	-	0	0	-	Covered	T1,T12,T14
StableSt	-	-	-	-	-	-	1	Covered	T12,T14,T42
StableSt	-	-	-	-	-	-	0	Covered	T12,T14,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	2979	0	0
CntIncr_A	8157508	96588	0	0
CntNoWrap_A	8157508	7529305	0	0
DetectStDropOut_A	8157508	390	0	0
DetectedOut_A	8157508	78076	0	0
DetectedPulseOut_A	8157508	964	0	0
DisabledIdleSt_A	8157508	7048804	0	0
DisabledNoDetection_A	8157508	7050856	0	0
EnterDebounceSt_A	8157508	1496	0	0
EnterDetectSt_A	8157508	1483	0	0
EnterStableSt_A	8157508	964	0	0
PulseIsPulse_A	8157508	964	0	0
StayInStableSt	8157508	76993	0	0
gen_high_event_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	828	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2979	0	0
T1	7769	18	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	22	0	0
T12	15221	28	0	0
T13	2206	0	0	0
T14	9688	52	0	0
T29	0	10	0	0
T42	0	16	0	0
T68	0	14	0	0
T69	0	44	0	0
T70	0	54	0	0
T71	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	96588	0	0
T1	7769	314	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	626	0	0
T12	15221	966	0	0
T13	2206	0	0	0
T14	9688	2262	0	0
T29	0	635	0	0
T42	0	584	0	0
T68	0	323	0	0
T69	0	1287	0	0
T70	0	2214	0	0
T71	0	1976	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7529305	0	0
T1	7769	7342	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14770	0	0
T13	2206	603	0	0
T14	9688	9235	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	390	0	0
T1	7769	5	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	4	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T29	0	2	0	0
T68	0	7	0	0
T69	0	22	0	0
T75	0	1	0	0
T91	0	26	0	0
T92	0	6	0	0
T168	0	4	0	0
T247	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	78076	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T12	15221	594	0	0
T13	2206	0	0	0
T14	9688	2076	0	0
T23	697	0	0	0
T42	0	233	0	0
T70	0	1870	0	0
T71	0	507	0	0
T108	0	1656	0	0
T153	0	118	0	0
T155	0	526	0	0
T245	0	1025	0	0
T246	0	1399	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	964	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T12	15221	14	0	0
T13	2206	0	0	0
T14	9688	26	0	0
T23	697	0	0	0
T42	0	8	0	0
T70	0	27	0	0
T71	0	26	0	0
T108	0	29	0	0
T153	0	3	0	0
T155	0	11	0	0
T245	0	13	0	0
T246	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7048804	0	0
T1	7769	5404	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	9338	0	0
T13	2206	603	0	0
T14	9688	2038	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7050856	0	0
T1	7769	5405	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	9340	0	0
T13	2206	606	0	0
T14	9688	2038	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1496	0	0
T1	7769	9	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	11	0	0
T12	15221	14	0	0
T13	2206	0	0	0
T14	9688	26	0	0
T29	0	5	0	0
T42	0	8	0	0
T68	0	7	0	0
T69	0	22	0	0
T70	0	27	0	0
T71	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1483	0	0
T1	7769	9	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	11	0	0
T12	15221	14	0	0
T13	2206	0	0	0
T14	9688	26	0	0
T29	0	5	0	0
T42	0	8	0	0
T68	0	7	0	0
T69	0	22	0	0
T70	0	27	0	0
T71	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	964	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T12	15221	14	0	0
T13	2206	0	0	0
T14	9688	26	0	0
T23	697	0	0	0
T42	0	8	0	0
T70	0	27	0	0
T71	0	26	0	0
T108	0	29	0	0
T153	0	3	0	0
T155	0	11	0	0
T245	0	13	0	0
T246	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	964	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T12	15221	14	0	0
T13	2206	0	0	0
T14	9688	26	0	0
T23	697	0	0	0
T42	0	8	0	0
T70	0	27	0	0
T71	0	26	0	0
T108	0	29	0	0
T153	0	3	0	0
T155	0	11	0	0
T245	0	13	0	0
T246	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	76993	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T12	15221	579	0	0
T13	2206	0	0	0
T14	9688	2050	0	0
T23	697	0	0	0
T42	0	225	0	0
T70	0	1843	0	0
T71	0	481	0	0
T108	0	1625	0	0
T153	0	115	0	0
T155	0	515	0	0
T245	0	1012	0	0
T246	0	1384	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	828	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T12	15221	13	0	0
T13	2206	0	0	0
T14	9688	26	0	0
T23	697	0	0	0
T42	0	8	0	0
T70	0	27	0	0
T71	0	11	0	0
T108	0	27	0	0
T153	0	3	0	0
T155	0	11	0	0
T245	0	13	0	0
T246	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T4
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T4
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T4,T14,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T4,T14,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T4,T14,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T4,T14
1	0	Covered	T1,T12,T4
1	1	Covered	T4,T14,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T14,T9
0	1	Covered	T4,T44,T37
1	0	Covered	T75,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T9,T27
0	1	Covered	T14,T9,T27
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T9,T27
1	-	Covered	T14,T9,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T14,T9
DetectSt	168	Covered	T4,T14,T9
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T14,T9,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T14,T9
DebounceSt->IdleSt	163	Covered	T9,T44,T88
DetectSt->IdleSt	186	Covered	T4,T44,T37
DetectSt->StableSt	191	Covered	T14,T9,T27
IdleSt->DebounceSt	148	Covered	T4,T14,T9
StableSt->IdleSt	206	Covered	T14,T9,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T14,T9
0	1	Covered	T4,T14,T9
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T14,T9
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T14,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T14,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T44,T88
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T14,T9
DetectSt	-	-	-	-	1	-	-	Covered	T4,T44,T37
DetectSt	-	-	-	-	0	1	-	Covered	T14,T9,T27
DetectSt	-	-	-	-	0	0	-	Covered	T4,T14,T9
StableSt	-	-	-	-	-	-	1	Covered	T14,T9,T27
StableSt	-	-	-	-	-	-	0	Covered	T14,T9,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	919	0	0
CntIncr_A	8157508	52366	0	0
CntNoWrap_A	8157508	7531365	0	0
DetectStDropOut_A	8157508	42	0	0
DetectedOut_A	8157508	15522	0	0
DetectedPulseOut_A	8157508	388	0	0
DisabledIdleSt_A	8157508	7166096	0	0
DisabledNoDetection_A	8157508	7167715	0	0
EnterDebounceSt_A	8157508	486	0	0
EnterDetectSt_A	8157508	435	0	0
EnterStableSt_A	8157508	388	0	0
PulseIsPulse_A	8157508	388	0	0
StayInStableSt	8157508	15081	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	332	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	919	0	0
T4	19047	16	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	5	0	0
T13	2206	0	0	0
T14	9688	4	0	0
T23	697	0	0	0
T27	0	4	0	0
T28	0	10	0	0
T37	0	10	0	0
T42	10980	0	0	0
T44	0	10	0	0
T51	409	0	0	0
T86	0	14	0	0
T87	0	12	0	0
T108	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	52366	0	0
T4	19047	1222	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	427	0	0
T13	2206	0	0	0
T14	9688	126	0	0
T23	697	0	0	0
T27	0	308	0	0
T28	0	815	0	0
T37	0	374	0	0
T42	10980	0	0	0
T44	0	716	0	0
T51	409	0	0	0
T86	0	1897	0	0
T87	0	222	0	0
T108	0	180	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7531365	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17786	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14798	0	0
T13	2206	603	0	0
T14	9688	9283	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	42	0	0
T4	19047	8	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T37	0	5	0	0
T42	10980	0	0	0
T44	0	4	0	0
T51	409	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T93	0	1	0	0
T248	0	6	0	0
T249	0	7	0	0
T250	0	5	0	0
T251	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	15522	0	0
T8	10797	0	0	0
T9	22998	18	0	0
T10	726	0	0	0
T14	9688	141	0	0
T22	502	0	0	0
T23	697	0	0	0
T27	0	39	0	0
T28	0	447	0	0
T30	0	153	0	0
T34	0	28	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T86	0	57	0	0
T87	0	71	0	0
T88	0	29	0	0
T108	0	54	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	388	0	0
T8	10797	0	0	0
T9	22998	2	0	0
T10	726	0	0	0
T14	9688	2	0	0
T22	502	0	0	0
T23	697	0	0	0
T27	0	2	0	0
T28	0	5	0	0
T30	0	2	0	0
T34	0	3	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T86	0	7	0	0
T87	0	6	0	0
T88	0	4	0	0
T108	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7166096	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	14222	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14205	0	0
T13	2206	603	0	0
T14	9688	7211	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7167715	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	14223	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14208	0	0
T13	2206	606	0	0
T14	9688	7212	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	486	0	0
T4	19047	8	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	3	0	0
T13	2206	0	0	0
T14	9688	2	0	0
T23	697	0	0	0
T27	0	2	0	0
T28	0	5	0	0
T37	0	5	0	0
T42	10980	0	0	0
T44	0	6	0	0
T51	409	0	0	0
T86	0	7	0	0
T87	0	6	0	0
T108	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	435	0	0
T4	19047	8	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	0	0	0
T9	22998	2	0	0
T13	2206	0	0	0
T14	9688	2	0	0
T23	697	0	0	0
T27	0	2	0	0
T28	0	5	0	0
T37	0	5	0	0
T42	10980	0	0	0
T44	0	4	0	0
T51	409	0	0	0
T86	0	7	0	0
T87	0	6	0	0
T108	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	388	0	0
T8	10797	0	0	0
T9	22998	2	0	0
T10	726	0	0	0
T14	9688	2	0	0
T22	502	0	0	0
T23	697	0	0	0
T27	0	2	0	0
T28	0	5	0	0
T30	0	2	0	0
T34	0	3	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T86	0	7	0	0
T87	0	6	0	0
T88	0	4	0	0
T108	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	388	0	0
T8	10797	0	0	0
T9	22998	2	0	0
T10	726	0	0	0
T14	9688	2	0	0
T22	502	0	0	0
T23	697	0	0	0
T27	0	2	0	0
T28	0	5	0	0
T30	0	2	0	0
T34	0	3	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T86	0	7	0	0
T87	0	6	0	0
T88	0	4	0	0
T108	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	15081	0	0
T8	10797	0	0	0
T9	22998	16	0	0
T10	726	0	0	0
T14	9688	139	0	0
T22	502	0	0	0
T23	697	0	0	0
T27	0	37	0	0
T28	0	442	0	0
T30	0	151	0	0
T34	0	25	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T86	0	50	0	0
T87	0	65	0	0
T88	0	25	0	0
T108	0	50	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	332	0	0
T8	10797	0	0	0
T9	22998	2	0	0
T10	726	0	0	0
T14	9688	1	0	0
T22	502	0	0	0
T23	697	0	0	0
T27	0	2	0	0
T28	0	5	0	0
T30	0	2	0	0
T34	0	3	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T86	0	7	0	0
T87	0	6	0	0
T88	0	4	0	0
T252	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T14
1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T14
1	0	Covered	T1,T12,T14
1	1	Covered	T1,T12,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T14
0	1	Covered	T1,T68,T69
1	0	Covered	T1,T70,T245

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T8
0	1	Covered	T12,T14,T8
1	0	Covered	T75,T253

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T14,T8
1	-	Covered	T12,T14,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T14
DetectSt	168	Covered	T1,T12,T14
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T12,T14,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T14
DebounceSt->IdleSt	163	Covered	T92,T75,T56
DetectSt->IdleSt	186	Covered	T1,T68,T69
DetectSt->StableSt	191	Covered	T12,T14,T8
IdleSt->DebounceSt	148	Covered	T1,T12,T14
StableSt->IdleSt	206	Covered	T12,T14,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T12,T14
0	1	Covered	T1,T12,T14
0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T14
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T14
IdleSt	0	-	-	-	-	-	-	Covered	T1,T12,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T92,T75,T56
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T14
DetectSt	-	-	-	-	1	-	-	Covered	T1,T68,T69
DetectSt	-	-	-	-	0	1	-	Covered	T12,T14,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T12,T14
StableSt	-	-	-	-	-	-	1	Covered	T12,T14,T8
StableSt	-	-	-	-	-	-	0	Covered	T12,T14,T8
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	3192	0	0
CntIncr_A	8157508	117195	0	0
CntNoWrap_A	8157508	7529092	0	0
DetectStDropOut_A	8157508	490	0	0
DetectedOut_A	8157508	68078	0	0
DetectedPulseOut_A	8157508	795	0	0
DisabledIdleSt_A	8157508	7056816	0	0
DisabledNoDetection_A	8157508	7058874	0	0
EnterDebounceSt_A	8157508	1603	0	0
EnterDetectSt_A	8157508	1589	0	0
EnterStableSt_A	8157508	795	0	0
PulseIsPulse_A	8157508	795	0	0
StayInStableSt	8157508	67170	0	0
gen_high_event_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	677	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	3192	0	0
T1	7769	52	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	12	0	0
T12	15221	62	0	0
T13	2206	0	0	0
T14	9688	28	0	0
T29	0	22	0	0
T42	0	48	0	0
T68	0	44	0	0
T69	0	52	0	0
T70	0	28	0	0
T71	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	117195	0	0
T1	7769	918	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	294	0	0
T12	15221	1736	0	0
T13	2206	0	0	0
T14	9688	1176	0	0
T29	0	968	0	0
T42	0	1968	0	0
T68	0	1037	0	0
T69	0	1529	0	0
T70	0	2084	0	0
T71	0	696	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7529092	0	0
T1	7769	7308	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14736	0	0
T13	2206	603	0	0
T14	9688	9259	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	490	0	0
T1	7769	18	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T68	0	22	0	0
T69	0	26	0	0
T75	0	1	0	0
T91	0	25	0	0
T92	0	24	0	0
T94	0	12	0	0
T96	0	30	0	0
T244	0	25	0	0
T247	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	68078	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	371	0	0
T9	22998	0	0	0
T12	15221	1719	0	0
T13	2206	0	0	0
T14	9688	427	0	0
T23	697	0	0	0
T29	0	1561	0	0
T42	0	1246	0	0
T71	0	198	0	0
T108	0	1827	0	0
T153	0	420	0	0
T155	0	2277	0	0
T246	0	877	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	795	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	6	0	0
T9	22998	0	0	0
T12	15221	31	0	0
T13	2206	0	0	0
T14	9688	14	0	0
T23	697	0	0	0
T29	0	11	0	0
T42	0	24	0	0
T71	0	8	0	0
T108	0	22	0	0
T153	0	8	0	0
T155	0	20	0	0
T246	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7056816	0	0
T1	7769	5404	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	9179	0	0
T13	2206	603	0	0
T14	9688	3436	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7058874	0	0
T1	7769	5405	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	9181	0	0
T13	2206	606	0	0
T14	9688	3436	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1603	0	0
T1	7769	26	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	6	0	0
T12	15221	31	0	0
T13	2206	0	0	0
T14	9688	14	0	0
T29	0	11	0	0
T42	0	24	0	0
T68	0	22	0	0
T69	0	26	0	0
T70	0	14	0	0
T71	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1589	0	0
T1	7769	26	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	6	0	0
T12	15221	31	0	0
T13	2206	0	0	0
T14	9688	14	0	0
T29	0	11	0	0
T42	0	24	0	0
T68	0	22	0	0
T69	0	26	0	0
T70	0	14	0	0
T71	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	795	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	6	0	0
T9	22998	0	0	0
T12	15221	31	0	0
T13	2206	0	0	0
T14	9688	14	0	0
T23	697	0	0	0
T29	0	11	0	0
T42	0	24	0	0
T71	0	8	0	0
T108	0	22	0	0
T153	0	8	0	0
T155	0	20	0	0
T246	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	795	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	6	0	0
T9	22998	0	0	0
T12	15221	31	0	0
T13	2206	0	0	0
T14	9688	14	0	0
T23	697	0	0	0
T29	0	11	0	0
T42	0	24	0	0
T71	0	8	0	0
T108	0	22	0	0
T153	0	8	0	0
T155	0	20	0	0
T246	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	67170	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	363	0	0
T9	22998	0	0	0
T12	15221	1687	0	0
T13	2206	0	0	0
T14	9688	413	0	0
T23	697	0	0	0
T29	0	1545	0	0
T42	0	1221	0	0
T71	0	190	0	0
T108	0	1803	0	0
T153	0	412	0	0
T155	0	2255	0	0
T246	0	869	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	677	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	4	0	0
T9	22998	0	0	0
T12	15221	30	0	0
T13	2206	0	0	0
T14	9688	14	0	0
T23	697	0	0	0
T29	0	6	0	0
T42	0	23	0	0
T71	0	8	0	0
T108	0	20	0	0
T153	0	8	0	0
T155	0	18	0	0
T246	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T14
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T14
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T12,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T12,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T12,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T8
1	0	Covered	T1,T12,T4
1	1	Covered	T12,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T8,T9
0	1	Covered	T27,T34,T90
1	0	Covered	T75,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T8,T9
0	1	Covered	T9,T29,T28
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T8,T9
1	-	Covered	T9,T29,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T8,T9
DetectSt	168	Covered	T12,T8,T9
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T12,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T8,T9
DebounceSt->IdleSt	163	Covered	T42,T27,T28
DetectSt->IdleSt	186	Covered	T27,T34,T90
DetectSt->StableSt	191	Covered	T12,T8,T9
IdleSt->DebounceSt	148	Covered	T12,T8,T9
StableSt->IdleSt	206	Covered	T12,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T8,T9
0	1	Covered	T12,T8,T9
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T8,T9
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T27,T28
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T27,T34,T90
DetectSt	-	-	-	-	0	1	-	Covered	T12,T8,T9
DetectSt	-	-	-	-	0	0	-	Covered	T12,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T9,T29,T28
StableSt	-	-	-	-	-	-	0	Covered	T12,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	786	0	0
CntIncr_A	8157508	42011	0	0
CntNoWrap_A	8157508	7531498	0	0
DetectStDropOut_A	8157508	47	0	0
DetectedOut_A	8157508	15114	0	0
DetectedPulseOut_A	8157508	320	0	0
DisabledIdleSt_A	8157508	7179846	0	0
DisabledNoDetection_A	8157508	7181484	0	0
EnterDebounceSt_A	8157508	415	0	0
EnterDetectSt_A	8157508	372	0	0
EnterStableSt_A	8157508	320	0	0
PulseIsPulse_A	8157508	320	0	0
StayInStableSt	8157508	14757	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	283	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	786	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	4	0	0
T9	22998	2	0	0
T12	15221	2	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T27	0	22	0	0
T28	0	15	0	0
T29	0	8	0	0
T37	0	2	0	0
T42	0	3	0	0
T86	0	1	0	0
T87	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	42011	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	104	0	0
T9	22998	93	0	0
T12	15221	44	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T27	0	1896	0	0
T28	0	1227	0	0
T29	0	360	0	0
T37	0	59	0	0
T42	0	111	0	0
T86	0	228	0	0
T87	0	287	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7531498	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14796	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	47	0	0
T27	25391	10	0	0
T28	23056	0	0	0
T34	0	4	0	0
T68	4966	0	0	0
T90	0	5	0	0
T254	0	2	0	0
T255	0	2	0	0
T256	0	1	0	0
T257	0	1	0	0
T258	0	10	0	0
T259	0	5	0	0
T260	0	3	0	0
T261	426	0	0	0
T262	516	0	0	0
T263	967	0	0	0
T264	438	0	0	0
T265	402	0	0	0
T266	152365	0	0	0
T267	978	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	15114	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	100	0	0
T9	22998	86	0	0
T12	15221	52	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T28	0	614	0	0
T29	0	233	0	0
T30	0	250	0	0
T37	0	15	0	0
T42	0	27	0	0
T87	0	58	0	0
T108	0	30	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	320	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	2	0	0
T9	22998	1	0	0
T12	15221	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T28	0	7	0	0
T29	0	4	0	0
T30	0	4	0	0
T37	0	1	0	0
T42	0	1	0	0
T87	0	7	0	0
T108	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7179846	0	0
T1	7769	7360	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	13080	0	0
T13	2206	603	0	0
T14	9688	8860	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7181484	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	13083	0	0
T13	2206	606	0	0
T14	9688	8861	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	415	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	2	0	0
T9	22998	1	0	0
T12	15221	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T27	0	12	0	0
T28	0	8	0	0
T29	0	4	0	0
T37	0	1	0	0
T42	0	2	0	0
T86	0	1	0	0
T87	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	372	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	2	0	0
T9	22998	1	0	0
T12	15221	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T27	0	10	0	0
T28	0	7	0	0
T29	0	4	0	0
T37	0	1	0	0
T42	0	1	0	0
T87	0	7	0	0
T108	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	320	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	2	0	0
T9	22998	1	0	0
T12	15221	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T28	0	7	0	0
T29	0	4	0	0
T30	0	4	0	0
T37	0	1	0	0
T42	0	1	0	0
T87	0	7	0	0
T108	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	320	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	2	0	0
T9	22998	1	0	0
T12	15221	1	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T28	0	7	0	0
T29	0	4	0	0
T30	0	4	0	0
T37	0	1	0	0
T42	0	1	0	0
T87	0	7	0	0
T108	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	14757	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T7	592	0	0	0
T8	10797	96	0	0
T9	22998	85	0	0
T12	15221	50	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T23	697	0	0	0
T28	0	607	0	0
T29	0	229	0	0
T30	0	246	0	0
T37	0	14	0	0
T42	0	25	0	0
T87	0	51	0	0
T108	0	29	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	283	0	0
T9	22998	1	0	0
T10	726	0	0	0
T20	490	0	0	0
T22	502	0	0	0
T28	0	7	0	0
T29	0	4	0	0
T30	0	4	0	0
T37	0	1	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T55	1334	0	0	0
T74	0	1	0	0
T87	0	7	0	0
T88	0	2	0	0
T108	0	1	0	0
T252	0	3	0	0